diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt | 5866 |
1 files changed, 2991 insertions, 2875 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 6eaff03eb..e64b12ad0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,181 +1,178 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.379675 # Number of seconds simulated -sim_ticks 47379674621500 # Number of ticks simulated -final_tick 47379674621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.422278 # Number of seconds simulated +sim_ticks 47422277747000 # Number of ticks simulated +final_tick 47422277747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105231 # Simulator instruction rate (inst/s) -host_op_rate 123773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5339286706 # Simulator tick rate (ticks/s) -host_mem_usage 910192 # Number of bytes of host memory used -host_seconds 8873.78 # Real time elapsed on the host -sim_insts 933798389 # Number of instructions simulated -sim_ops 1098335322 # Number of ops (including micro ops) simulated +host_inst_rate 91986 # Simulator instruction rate (inst/s) +host_op_rate 108182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4717167353 # Simulator tick rate (ticks/s) +host_mem_usage 870208 # Number of bytes of host memory used +host_seconds 10053.13 # Real time elapsed on the host +sim_insts 924745220 # Number of instructions simulated +sim_ops 1087564829 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 353088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 523648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1152800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 18354072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 38298624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 338240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 462784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 532064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 12967328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 29162240 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 472128 # Number of bytes read from this memory -system.physmem.bytes_read::total 102617016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1152800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 532064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1684864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 56488832 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 66623564 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 34275268 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory -system.physmem.bytes_written::total 164218256 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 5517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 33965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 286804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 598416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 5285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 7231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 202629 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 455660 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7377 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1619423 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 882638 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1043270 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 535552 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2568188 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 7452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 11052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 24331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 387383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 808334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 7139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 9768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 273690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 615501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9965 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2165845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 24331 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 35561 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1192259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1406163 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 723417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 144167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3466006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1192259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 7452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 11052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 24331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1793546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 808334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 7139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 9768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 997107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 615501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 154132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5631851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1619423 # Number of read requests accepted -system.physmem.writeReqs 2568188 # Number of write requests accepted -system.physmem.readBursts 1619423 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2568188 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 103371328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 271744 # Total number of bytes read from write queue -system.physmem.bytesWritten 158872640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 102617016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 164218256 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4246 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 85771 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 103144 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 111705 # Per bank write bursts -system.physmem.perBankRdBursts::1 107185 # Per bank write bursts -system.physmem.perBankRdBursts::2 95216 # Per bank write bursts -system.physmem.perBankRdBursts::3 93593 # Per bank write bursts -system.physmem.perBankRdBursts::4 97040 # Per bank write bursts -system.physmem.perBankRdBursts::5 109538 # Per bank write bursts -system.physmem.perBankRdBursts::6 103640 # Per bank write bursts -system.physmem.perBankRdBursts::7 104459 # Per bank write bursts -system.physmem.perBankRdBursts::8 87345 # Per bank write bursts -system.physmem.perBankRdBursts::9 119689 # Per bank write bursts -system.physmem.perBankRdBursts::10 87550 # Per bank write bursts -system.physmem.perBankRdBursts::11 102455 # Per bank write bursts -system.physmem.perBankRdBursts::12 98167 # Per bank write bursts -system.physmem.perBankRdBursts::13 96293 # Per bank write bursts -system.physmem.perBankRdBursts::14 97699 # Per bank write bursts -system.physmem.perBankRdBursts::15 103603 # Per bank write bursts -system.physmem.perBankWrBursts::0 151797 # Per bank write bursts -system.physmem.perBankWrBursts::1 157102 # Per bank write bursts -system.physmem.perBankWrBursts::2 173467 # Per bank write bursts -system.physmem.perBankWrBursts::3 129226 # Per bank write bursts -system.physmem.perBankWrBursts::4 217724 # Per bank write bursts -system.physmem.perBankWrBursts::5 151423 # Per bank write bursts -system.physmem.perBankWrBursts::6 153455 # Per bank write bursts -system.physmem.perBankWrBursts::7 181552 # Per bank write bursts -system.physmem.perBankWrBursts::8 127836 # Per bank write bursts -system.physmem.perBankWrBursts::9 166575 # Per bank write bursts -system.physmem.perBankWrBursts::10 140595 # Per bank write bursts -system.physmem.perBankWrBursts::11 139064 # Per bank write bursts -system.physmem.perBankWrBursts::12 135611 # Per bank write bursts -system.physmem.perBankWrBursts::13 129688 # Per bank write bursts -system.physmem.perBankWrBursts::14 173219 # Per bank write bursts -system.physmem.perBankWrBursts::15 154051 # Per bank write bursts +system.physmem.bytes_read::cpu0.dtb.walker 123008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 83392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1145824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12461528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 54523392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 250240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 244864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 679904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13804768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 35481280 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 451200 # Number of bytes read from this memory +system.physmem.bytes_read::total 119249400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1145824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 679904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1825728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 92428416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::total 92449232 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 33856 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 194733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 851928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3826 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 215714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 554395 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7050 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1879304 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1444194 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1446797 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 24162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 262778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1149742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 5277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 5163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 291103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 748199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2514628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 24162 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 38499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1949051 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1949489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1949051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 24162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 263217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1149742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 5277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 5163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 291103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 748199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4464118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1879304 # Number of read requests accepted +system.physmem.writeReqs 1600997 # Number of write requests accepted +system.physmem.readBursts 1879304 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1600997 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 120227392 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48064 # Total number of bytes read from write queue +system.physmem.bytesWritten 101998144 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 119249400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 102318032 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 751 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7249 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 97584 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 111371 # Per bank write bursts +system.physmem.perBankRdBursts::1 133364 # Per bank write bursts +system.physmem.perBankRdBursts::2 107237 # Per bank write bursts +system.physmem.perBankRdBursts::3 129396 # Per bank write bursts +system.physmem.perBankRdBursts::4 116369 # Per bank write bursts +system.physmem.perBankRdBursts::5 129089 # Per bank write bursts +system.physmem.perBankRdBursts::6 116664 # Per bank write bursts +system.physmem.perBankRdBursts::7 120571 # Per bank write bursts +system.physmem.perBankRdBursts::8 118226 # Per bank write bursts +system.physmem.perBankRdBursts::9 133705 # Per bank write bursts +system.physmem.perBankRdBursts::10 98234 # Per bank write bursts +system.physmem.perBankRdBursts::11 110272 # Per bank write bursts +system.physmem.perBankRdBursts::12 110364 # Per bank write bursts +system.physmem.perBankRdBursts::13 124983 # Per bank write bursts +system.physmem.perBankRdBursts::14 111960 # Per bank write bursts +system.physmem.perBankRdBursts::15 106748 # Per bank write bursts +system.physmem.perBankWrBursts::0 99185 # Per bank write bursts +system.physmem.perBankWrBursts::1 109011 # Per bank write bursts +system.physmem.perBankWrBursts::2 97054 # Per bank write bursts +system.physmem.perBankWrBursts::3 108172 # Per bank write bursts +system.physmem.perBankWrBursts::4 98286 # Per bank write bursts +system.physmem.perBankWrBursts::5 106076 # Per bank write bursts +system.physmem.perBankWrBursts::6 100140 # Per bank write bursts +system.physmem.perBankWrBursts::7 103851 # Per bank write bursts +system.physmem.perBankWrBursts::8 98795 # Per bank write bursts +system.physmem.perBankWrBursts::9 98239 # Per bank write bursts +system.physmem.perBankWrBursts::10 89198 # Per bank write bursts +system.physmem.perBankWrBursts::11 97505 # Per bank write bursts +system.physmem.perBankWrBursts::12 95822 # Per bank write bursts +system.physmem.perBankWrBursts::13 102116 # Per bank write bursts +system.physmem.perBankWrBursts::14 95043 # Per bank write bursts +system.physmem.perBankWrBursts::15 95228 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 280 # Number of times write queue was full causing retry -system.physmem.totGap 47379673169000 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 47422276363500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1598053 # Read request sizes (log2) +system.physmem.readPktSize::6 1857934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2565585 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 575288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 378276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 198870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 124070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 84552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 66107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 57559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 42131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 14414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 7965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 5242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1598394 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 506038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 360780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 256406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 156907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 129304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 95738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 81613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 74114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 66527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 41507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 23594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 21466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -191,159 +188,184 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 50077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 80336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 91349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 103691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 113552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 135687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 144994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 161556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 168861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 188844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 173768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 166459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 153274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 157126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 123678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 118188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 114281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 106686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 15195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 674 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 968355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 270.813741 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.322670 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.242545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 500729 51.71% 51.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 182951 18.89% 70.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 62910 6.50% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 30320 3.13% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 27676 2.86% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15651 1.62% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 12433 1.28% 85.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15606 1.61% 87.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 120079 12.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 968355 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 90300 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.886467 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 201.343157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 90297 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 90300 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 90300 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.490421 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 23.640759 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.748039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 56859 62.97% 62.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 8057 8.92% 71.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 12273 13.59% 85.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 3990 4.42% 89.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1898 2.10% 92.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 944 1.05% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2681 2.97% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1258 1.39% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 729 0.81% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 233 0.26% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 328 0.36% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 174 0.19% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 473 0.52% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 16 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 44 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 33 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 34 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 77 0.09% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 57 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 40 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 6 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 21 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 22 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 90300 # Writes before turning the bus around for reads -system.physmem.totQLat 65880977516 # Total ticks spent queuing -system.physmem.totMemAccLat 96165546266 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8075885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 40788.70 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 23051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 51054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 76742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 83422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 99100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 114191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 124207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 117512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 121939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 125600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 118087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 27656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 21524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 15466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 10008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 975956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.699905 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.562466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 280.517231 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 518192 53.10% 53.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 197775 20.26% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 73464 7.53% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 39205 4.02% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 32875 3.37% 88.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 20645 2.12% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14690 1.51% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16974 1.74% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62136 6.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 975956 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 85700 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.919883 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.914571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 85693 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 85700 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 85700 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.596511 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.559355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.221946 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 76419 89.17% 89.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4825 5.63% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 861 1.00% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 776 0.91% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 493 0.58% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 0.16% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 117 0.14% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 137 0.16% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 585 0.68% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 72 0.08% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 76 0.09% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 72 0.08% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 110 0.13% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 48 0.06% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 42 0.05% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 81 0.09% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 124 0.14% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 28 0.03% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 35 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 50 0.06% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 194 0.23% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 14 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 23 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 54 0.06% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 16 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 21 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 26 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 106 0.12% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 28 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 8 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 15 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 15 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 11 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 85700 # Writes before turning the bus around for reads +system.physmem.totQLat 131185455773 # Total ticks spent queuing +system.physmem.totMemAccLat 166408324523 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9392765000 # Total ticks spent in databus transfers +system.physmem.avgQLat 69833.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 59538.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.47 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 88583.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.63 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing -system.physmem.readRowHits 1266207 # Number of row buffer hits during reads -system.physmem.writeRowHits 1862998 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes -system.physmem.avgGap 11314248.90 # Average gap between requests -system.physmem.pageHitRate 76.37 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45458713155000 # Time in different power states -system.physmem.memoryStateTime::REF 1582111440000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing +system.physmem.readRowHits 1529879 # Number of row buffer hits during reads +system.physmem.writeRowHits 966437 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.64 # Row buffer hit rate for writes +system.physmem.avgGap 13625912.35 # Average gap between requests +system.physmem.pageHitRate 71.89 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 45568926392500 # Time in different power states +system.physmem.memoryStateTime::REF 1583533900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 338849669500 # Time in different power states +system.physmem.memoryStateTime::ACT 269814192000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3771472320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3549283920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2057847000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1936613250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 6414501600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 6183847800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 8526034080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 7559820720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3094609976640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3094609976640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1215510046335 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1201972779180 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27361567580250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27373442376000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31692457458225 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31689254697510 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.904083 # Core power per rank (mW) -system.physmem.averagePower::1 668.836485 # Core power per rank (mW) +system.physmem.actEnergy::0 3837713040 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 3540506760 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 2093990250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1931824125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 7519675800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 7132967400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 5325102000 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 5002210080 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3097392308400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3097392308400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1175879799405 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1172220553305 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 27421890099000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 27425099964000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 31713938687895 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 31712320334070 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.756196 # Core power per rank (mW) +system.physmem.averagePower::1 668.722070 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -376,15 +398,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 146587108 # Number of BP lookups -system.cpu0.branchPred.condPredicted 96932064 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7164901 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 103453764 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 67642054 # Number of BTB hits +system.cpu0.branchPred.lookups 136692903 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91051024 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6675955 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 96641264 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 62499971 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.383850 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20270932 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 203679 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 64.672137 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18343531 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 188881 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -409,25 +431,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 106134781 # DTB read hits -system.cpu0.dtb.read_misses 438400 # DTB read misses -system.cpu0.dtb.write_hits 87107060 # DTB write hits -system.cpu0.dtb.write_misses 166320 # DTB write misses -system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 98285730 # DTB read hits +system.cpu0.dtb.read_misses 371363 # DTB read misses +system.cpu0.dtb.write_hits 82429878 # DTB write hits +system.cpu0.dtb.write_misses 160428 # DTB write misses +system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 41289 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 449 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7213 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34259 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 6211 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 39737 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106573181 # DTB read accesses -system.cpu0.dtb.write_accesses 87273380 # DTB write accesses +system.cpu0.dtb.perms_faults 37781 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 98657093 # DTB read accesses +system.cpu0.dtb.write_accesses 82590306 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 193241841 # DTB hits -system.cpu0.dtb.misses 604720 # DTB misses -system.cpu0.dtb.accesses 193846561 # DTB accesses +system.cpu0.dtb.hits 180715608 # DTB hits +system.cpu0.dtb.misses 531791 # DTB misses +system.cpu0.dtb.accesses 181247399 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -449,519 +471,533 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 230537480 # ITB inst hits -system.cpu0.itb.inst_misses 86000 # ITB inst misses +system.cpu0.itb.inst_hits 214588445 # ITB inst hits +system.cpu0.itb.inst_misses 81035 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29668 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24176 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 226388 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 217359 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 230623480 # ITB inst accesses -system.cpu0.itb.hits 230537480 # DTB hits -system.cpu0.itb.misses 86000 # DTB misses -system.cpu0.itb.accesses 230623480 # DTB accesses -system.cpu0.numCycles 786965482 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 214669480 # ITB inst accesses +system.cpu0.itb.hits 214588445 # DTB hits +system.cpu0.itb.misses 81035 # DTB misses +system.cpu0.itb.accesses 214669480 # DTB accesses +system.cpu0.numCycles 723605959 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 90387711 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 647691070 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 146587108 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 87912986 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 665690431 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15471710 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1846295 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 143165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6476529 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 786234 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 320116 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 230311190 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1742140 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 773386336 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.980975 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.219702 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 84128505 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 603958712 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 136692903 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 80843502 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 610845531 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14389096 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1590613 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 145998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6064926 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 691327 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 308415 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 214371554 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1629958 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 26989 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 710969863 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.995603 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.223531 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 409957196 53.01% 53.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 140998975 18.23% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 49617031 6.42% 77.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 172813134 22.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 371943625 52.31% 52.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 132005479 18.57% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 45223870 6.36% 77.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 161796889 22.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 773386336 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.186269 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.823023 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 108593313 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 378356513 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 240969730 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39977542 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5489238 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21224089 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2292433 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 668689408 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 25030555 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5489238 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 146312922 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 57383456 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 250430469 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 242520551 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 71249700 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 650266707 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6336504 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 9477139 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 381865 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 840506 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 33815177 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 14484 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 619540415 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1001273329 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 768127423 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 806411 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 558016180 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 61524234 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16309942 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14158531 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 81487680 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 106551444 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90697387 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9851628 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8566406 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 626998472 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16435650 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 631073777 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2910747 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54340762 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 37568320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 303534 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 773386336 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.815988 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.066561 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 710969863 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.188905 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.834651 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 100859820 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 341670501 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 226894689 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 36450722 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5094131 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19684552 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2143149 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 625299942 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23465263 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5094131 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 135677386 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 49836875 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 228336608 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 227963533 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 64061330 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 608231586 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 5949574 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 8548374 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 231810 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 263882 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 30185355 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 12581 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 579905224 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 937754781 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 718843517 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 1013139 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 522903039 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 57002179 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15055979 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13152707 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 73956769 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 99026206 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85770687 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8763922 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7686093 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 586686508 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15156086 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 590156830 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2681738 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 50409396 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 34542071 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 266225 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 710969863 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.830073 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.072195 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 429333552 55.51% 55.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 143479671 18.55% 74.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 122471651 15.84% 89.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 69760577 9.02% 98.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8335355 1.08% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5527 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 390297771 54.90% 54.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 132320625 18.61% 73.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 115120103 16.19% 89.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 65333726 9.19% 98.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7893369 1.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 4269 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 773386336 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 710969863 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 65856729 45.73% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 73447 0.05% 45.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 22232 0.02% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 47 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37876967 26.30% 72.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 40192311 27.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61459839 45.63% 45.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 50531 0.04% 45.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 24866 0.02% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 22 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 34471783 25.59% 71.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 38693635 28.73% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 431505224 68.38% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1606072 0.25% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 80666 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 12 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 46680 0.01% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 109370672 17.33% 85.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88464450 14.02% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 403696370 68.40% 68.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1373917 0.23% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 72713 0.01% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 2 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 82685 0.01% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 101222055 17.15% 85.82% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83709039 14.18% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 631073777 # Type of FU issued -system.cpu0.iq.rate 0.801908 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 144021733 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228217 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2181305203 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 697468177 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 613392938 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1161167 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 463347 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 426941 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 774373560 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 721950 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2923759 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 590156830 # Type of FU issued +system.cpu0.iq.rate 0.815578 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 134700676 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228246 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2027250728 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 651818194 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 574107974 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1415207 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 570288 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 525567 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 723981962 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 875543 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2649036 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13150556 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17424 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 157648 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6172607 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12005066 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15997 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 137574 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5832630 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2931375 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4759724 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2633268 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 3783846 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5489238 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8266633 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 4717216 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 643560247 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5094131 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6289107 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 4809356 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 601961701 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 106551444 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90697387 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13867290 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 61805 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4582618 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 157648 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2155844 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3101202 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5257046 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 622852330 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 106129153 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7624905 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 99026206 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85770687 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12881584 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 63147 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4682481 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 137574 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1984191 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2898838 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4883029 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 582493668 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 98279194 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7144205 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 126125 # number of nop insts executed -system.cpu0.iew.exec_refs 193235409 # number of memory reference insts executed -system.cpu0.iew.exec_branches 117777762 # Number of branches executed -system.cpu0.iew.exec_stores 87106256 # Number of stores executed -system.cpu0.iew.exec_rate 0.791461 # Inst execution rate -system.cpu0.iew.wb_sent 614619625 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 613819879 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 298670143 # num instructions producing a value -system.cpu0.iew.wb_consumers 489758313 # num instructions consuming a value +system.cpu0.iew.exec_nop 119107 # number of nop insts executed +system.cpu0.iew.exec_refs 180711366 # number of memory reference insts executed +system.cpu0.iew.exec_branches 110157991 # Number of branches executed +system.cpu0.iew.exec_stores 82432172 # Number of stores executed +system.cpu0.iew.exec_rate 0.804987 # Inst execution rate +system.cpu0.iew.wb_sent 575359382 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 574633541 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 278757047 # num instructions producing a value +system.cpu0.iew.wb_consumers 457962623 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.779983 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609832 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.794125 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.608690 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 50622338 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16132116 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4918284 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 763797135 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.766621 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.569865 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 46943290 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14889861 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4575538 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 702085405 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.780670 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.579297 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 508551807 66.58% 66.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 131505056 17.22% 83.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 56862924 7.44% 91.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 18814885 2.46% 93.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13980697 1.83% 95.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9342143 1.22% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6309382 0.83% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 4063980 0.53% 98.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14366261 1.88% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 463334360 65.99% 65.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 122538358 17.45% 83.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 53278812 7.59% 91.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18006181 2.56% 93.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13261797 1.89% 95.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8597155 1.22% 96.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5895517 0.84% 97.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3809437 0.54% 98.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13363788 1.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 763797135 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 498729441 # Number of instructions committed -system.cpu0.commit.committedOps 585543302 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 702085405 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 466411686 # Number of instructions committed +system.cpu0.commit.committedOps 548096953 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 177925668 # Number of memory references committed -system.cpu0.commit.loads 93400888 # Number of loads committed -system.cpu0.commit.membars 4075726 # Number of memory barriers committed -system.cpu0.commit.branches 111746625 # Number of branches committed -system.cpu0.commit.fp_insts 417930 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 537600399 # Number of committed integer instructions. -system.cpu0.commit.function_calls 15117239 # Number of function calls committed. +system.cpu0.commit.refs 166959196 # Number of memory references committed +system.cpu0.commit.loads 87021139 # Number of loads committed +system.cpu0.commit.membars 3711025 # Number of memory barriers committed +system.cpu0.commit.branches 104496556 # Number of branches committed +system.cpu0.commit.fp_insts 513447 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 502627891 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13679873 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 406177320 69.37% 69.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1336444 0.23% 69.60% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 63141 0.01% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 40729 0.01% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 93400888 15.95% 85.56% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84524780 14.44% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 379865208 69.31% 69.31% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1141082 0.21% 69.51% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 57492 0.01% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 73933 0.01% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 87021139 15.88% 85.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 79938057 14.58% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 585543302 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14366261 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 548096953 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13363788 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1380974813 # The number of ROB reads -system.cpu0.rob.rob_writes 1281884282 # The number of ROB writes -system.cpu0.timesIdled 846185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 13579146 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93972383800 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 498729441 # Number of Instructions Simulated -system.cpu0.committedOps 585543302 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.577941 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.577941 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.633737 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.633737 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 735405419 # number of integer regfile reads -system.cpu0.int_regfile_writes 437369435 # number of integer regfile writes -system.cpu0.fp_regfile_reads 697220 # number of floating regfile reads -system.cpu0.fp_regfile_writes 340900 # number of floating regfile writes -system.cpu0.cc_regfile_reads 134840784 # number of cc regfile reads -system.cpu0.cc_regfile_writes 135500502 # number of cc regfile writes -system.cpu0.misc_regfile_reads 3071586051 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16203449 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6421778 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.783649 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 165065902 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6422290 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.702032 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 1279505618 # The number of ROB reads +system.cpu0.rob.rob_writes 1198929363 # The number of ROB writes +system.cpu0.timesIdled 780048 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 12636096 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94120949562 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 466411686 # Number of Instructions Simulated +system.cpu0.committedOps 548096953 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.551432 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.551432 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.644566 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.644566 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 688144011 # number of integer regfile reads +system.cpu0.int_regfile_writes 408577767 # number of integer regfile writes +system.cpu0.fp_regfile_reads 842658 # number of floating regfile reads +system.cpu0.fp_regfile_writes 455584 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127446024 # number of cc regfile reads +system.cpu0.cc_regfile_writes 128164594 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2855519856 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15107964 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 5838402 # number of replacements +system.cpu0.dcache.tags.tagsinuse 504.465464 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155155227 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5838912 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.572626 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.783649 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983952 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983952 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 369226254 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 369226254 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86280065 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86280065 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73574281 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73574281 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 230862 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 230862 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1040668 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 1040668 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1948592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1948592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1987329 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1987329 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 159854346 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 159854346 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 160085208 # number of overall hits -system.cpu0.dcache.overall_hits::total 160085208 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7331765 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7331765 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7708797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7708797 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740087 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 740087 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 294779 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 294779 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 214098 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 214098 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15040562 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15040562 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15780649 # number of overall misses -system.cpu0.dcache.overall_misses::total 15780649 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 115068880578 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 115068880578 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 135208359707 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 135208359707 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4223400082 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4223400082 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4534810216 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4534810216 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4219500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4219500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 250277240285 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 250277240285 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 250277240285 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 93611830 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 93611830 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81283078 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81283078 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 970949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 970949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1040668 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1040668 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2243371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2243371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2201427 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2201427 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 174894908 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 174894908 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 175865857 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 175865857 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078321 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.078321 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.094839 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.094839 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762231 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762231 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131400 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131400 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097254 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097254 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085998 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.085998 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089731 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.089731 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.465464 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985284 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.985284 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 346167633 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 346167633 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80535549 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80535549 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69641264 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69641264 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207056 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 207056 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 203093 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 203093 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877400 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1877400 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1900232 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1900232 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 150176813 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 150176813 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150383869 # number of overall hits +system.cpu0.dcache.overall_hits::total 150383869 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6642832 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6642832 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7191098 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7191098 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 692118 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 692118 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 798159 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 798159 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 243998 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 243998 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 184133 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 184133 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13833930 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13833930 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 14526048 # number of overall misses +system.cpu0.dcache.overall_misses::total 14526048 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 99514286008 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 99514286008 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 115098035706 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 115098035706 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 53560236062 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 53560236062 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3359260407 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3359260407 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3823760481 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3823760481 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2172500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2172500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 214612321714 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 214612321714 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 214612321714 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 214612321714 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87178381 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 87178381 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76832362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76832362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899174 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 899174 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1001252 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1001252 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2121398 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2121398 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2084365 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2084365 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 164010743 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 164010743 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164909917 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164909917 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076198 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.076198 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093595 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.093595 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769726 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769726 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.797161 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.797161 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115018 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115018 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088340 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088340 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084348 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084348 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088085 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088085 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14980.701907 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14980.701907 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16005.627472 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 16005.627472 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 67104.719814 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 67104.719814 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13767.573533 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13767.573533 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20766.296541 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20766.296541 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 17082084 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 19003690 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 950552 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 748671 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.970699 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 25.383232 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 1040668 # number of fast writes performed +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15513.474603 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15513.474603 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14774.309001 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14774.309001 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 16118603 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 16176348 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 692801 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 696412 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.265848 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 23.228129 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3548346 # number of writebacks -system.cpu0.dcache.writebacks::total 3548346 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3808172 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3808172 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6155071 # 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number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 733570 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 143839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 143839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 214091 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 214091 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5055777 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5055777 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5789347 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5789347 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48006705459 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48006705459 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27570008615 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27570008615 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18661725527 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18661725527 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 57519686561 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57519686561 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1764532424 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1764532424 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4095364784 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4095364784 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4027500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4027500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75576714074 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 75576714074 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94238439601 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 94238439601 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5807383412 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5807383412 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5600359921 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5600359921 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11407743333 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11407743333 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018850 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018850 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755519 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755519 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064117 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064117 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097251 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097251 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028908 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028908 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032919 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032919 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3975125 # number of writebacks +system.cpu0.dcache.writebacks::total 3975125 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3497983 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3497983 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5763188 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 5763188 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4492 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4492 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123982 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123982 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9261171 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9261171 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9261171 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9261171 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3144849 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3144849 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1427910 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1427910 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685927 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 685927 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 793667 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 793667 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120016 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120016 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 184129 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 184129 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4572759 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4572759 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5258686 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5258686 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40981205496 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40981205496 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22755476630 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22755476630 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17996613568 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17996613568 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 51855736982 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 51855736982 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1434297417 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1434297417 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3446370519 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3446370519 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2070500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2070500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63736682126 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 63736682126 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81733295694 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 81733295694 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5581760391 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5581760391 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5277895398 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5277895398 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10859655789 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10859655789 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036074 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036074 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018585 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018585 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762841 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762841 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.792675 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.792675 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056574 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056574 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027881 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027881 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031888 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031888 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13031.215647 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13031.215647 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15936.212107 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15936.212107 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26236.922541 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26236.922541 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 65336.894418 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 65336.894418 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11950.885024 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11950.885024 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18717.152209 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18717.152209 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13938.342722 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13938.342722 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15542.532050 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15542.532050 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -969,447 +1005,463 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6503720 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.971418 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 223511778 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6504232 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.364054 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8400074750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.971418 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999944 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 6042830 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.967320 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 208050611 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6043342 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.426417 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 11201042000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.967320 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999936 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999936 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 467078613 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 467078613 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 223511778 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 223511778 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 223511778 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 223511778 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 223511778 # number of overall hits -system.cpu0.icache.overall_hits::total 223511778 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6775226 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6775226 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6775226 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6775226 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6775226 # number of overall misses -system.cpu0.icache.overall_misses::total 6775226 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 58809305620 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 58809305620 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 58809305620 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 58809305620 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 58809305620 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 58809305620 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 230287004 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 230287004 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 230287004 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 230287004 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 230287004 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 230287004 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029421 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029421 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029421 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029421 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029421 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029421 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8680.050764 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8680.050764 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8680.050764 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8680.050764 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4711788 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 167 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 607280 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 434737408 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 434737408 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 208050611 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 208050611 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 208050611 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 208050611 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 208050611 # number of overall hits +system.cpu0.icache.overall_hits::total 208050611 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6296413 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6296413 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6296413 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6296413 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6296413 # number of overall misses +system.cpu0.icache.overall_misses::total 6296413 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55127710497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 55127710497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 55127710497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 55127710497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 55127710497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 55127710497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 214347024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 214347024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 214347024 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 214347024 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 214347024 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 214347024 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029375 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029375 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029375 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029375 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029375 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029375 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8755.415265 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8755.415265 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8755.415265 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8755.415265 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8755.415265 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4477144 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 62 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 570538 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.758839 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 167 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.847232 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 62 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 270621 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 270621 # 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number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6043360 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6043360 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6043360 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6043360 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6043360 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6043360 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 44707631164 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 44707631164 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 44707631164 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 44707631164 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 44707631164 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 44707631164 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699559498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699559498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028246 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028246 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028246 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7325.153650 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7325.153650 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7325.153650 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028194 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028194 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028194 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028194 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7397.810351 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7397.810351 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7397.810351 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 59245032 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2351166 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 52469358 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1249562 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 60184765 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4393414 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 48808124 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 3087530 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 200789 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2974157 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4925432 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 452633 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3443064 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5114963 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3747306 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16276.136731 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 13593053 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3763332 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.611973 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 6997709500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4266.822439 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 59.073583 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.998615 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 875.814301 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3003.067946 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8009.359846 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.260426 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003606 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003784 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.053455 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.183293 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.488853 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.993417 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8909 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7022 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 203 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3635 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3246 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1573 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 759 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2892 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2491 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 768 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.543762 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.428589 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 294843936 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 294843936 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 600493 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 260281521 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4356544455 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37784374528 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 191389904056 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 234173879151 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1519173000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5544879586 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7064052586 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5346512529 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5346512529 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5327096604 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6846269604 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5036994556 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5036994556 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519173000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10891392115 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12410565115 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.266067 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.118006 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10364091160 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11883264160 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.278529 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.122077 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.524845 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.524845 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.818029 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.818029 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.129074 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.129074 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.503091 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.503091 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.790514 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.790514 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.200020 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.200020 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026536 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.251089 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.126143 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026536 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251089 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.185504 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.185504 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128447 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025853 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054478 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.030416 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256912 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.354862 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 30124.578689 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29676.550699 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 35601.440437 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.943421 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17421.943421 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13837.367604 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13837.367604 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 181083.277778 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 181083.277778 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40961.276755 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40961.276755 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31451.797521 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34126.366499 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.417806 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27642.980057 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27083.574890 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55593.563487 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32521.484628 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32521.484628 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17427.856472 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17427.856472 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13830.282341 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13830.282341 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 237500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 237500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 33377.085578 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 33377.085578 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27996.319261 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27623.193404 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27028.195327 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23700.443675 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28605.109356 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55593.563487 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47109.300568 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1419,69 +1471,69 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 15637085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 12009481 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33046 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33046 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3548344 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4365503 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1683195 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1040668 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 461767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 386684 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 535373 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1436156 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1297014 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 13051451 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18246800 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419537 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1341455 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 33059243 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 416613216 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 664873226 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1541384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4934904 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1087962730 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 9586812 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27467610 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.337349 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.472805 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 15173335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11005084 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31316 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31316 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3975122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 5222365 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 963549 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 792291 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 491639 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 333223 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 494297 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1332515 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1202467 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12129286 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16997895 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390025 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1185916 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30703122 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 387114336 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 641181457 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1414144 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4287888 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1033997825 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 10518238 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27441081 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.371527 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.483213 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 18201451 66.27% 66.27% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 9266159 33.73% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 17245975 62.85% 62.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 10195106 37.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27467610 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 13754094390 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 27441081 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 13452656135 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 197445482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 192867736 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9792438220 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9099601288 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9396795912 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8421572630 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 228193109 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 213967447 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 726243001 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 651243914 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 126883394 # Number of BP lookups -system.cpu1.branchPred.condPredicted 85166335 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6223569 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 90014178 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 58475937 # Number of BTB hits +system.cpu1.branchPred.lookups 133961841 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89061347 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6618163 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 94585757 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 62217505 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 64.963029 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16774062 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 171946 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.778936 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 18340774 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 186545 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1505,25 +1557,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 93423769 # DTB read hits -system.cpu1.dtb.read_misses 385141 # DTB read misses -system.cpu1.dtb.write_hits 77506370 # DTB write hits -system.cpu1.dtb.write_misses 166753 # DTB write misses -system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 98830623 # DTB read hits +system.cpu1.dtb.read_misses 443426 # DTB read misses +system.cpu1.dtb.write_hits 80619639 # DTB write hits +system.cpu1.dtb.write_misses 165440 # DTB write misses +system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 38053 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 411 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6413 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 44150 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 612 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6848 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 42956 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 93808910 # DTB read accesses -system.cpu1.dtb.write_accesses 77673123 # DTB write accesses +system.cpu1.dtb.perms_faults 42554 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 99274049 # DTB read accesses +system.cpu1.dtb.write_accesses 80785079 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 170930139 # DTB hits -system.cpu1.dtb.misses 551894 # DTB misses -system.cpu1.dtb.accesses 171482033 # DTB accesses +system.cpu1.dtb.hits 179450262 # DTB hits +system.cpu1.dtb.misses 608866 # DTB misses +system.cpu1.dtb.accesses 180059128 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1545,519 +1597,533 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 200532583 # ITB inst hits -system.cpu1.itb.inst_misses 85074 # ITB inst misses +system.cpu1.itb.inst_hits 211899162 # ITB inst hits +system.cpu1.itb.inst_misses 88988 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44806 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 32114 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 221691 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 230833 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 200617657 # ITB inst accesses -system.cpu1.itb.hits 200532583 # DTB hits -system.cpu1.itb.misses 85074 # DTB misses -system.cpu1.itb.accesses 200617657 # DTB accesses -system.cpu1.numCycles 671498045 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 211988150 # ITB inst accesses +system.cpu1.itb.hits 211899162 # DTB hits +system.cpu1.itb.misses 88988 # DTB misses +system.cpu1.itb.accesses 211988150 # DTB accesses +system.cpu1.numCycles 705261968 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 76057268 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 563958948 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 126883394 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 75249999 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 570112426 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13401984 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1796129 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 140886 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6366912 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 711415 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 284551 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 200289545 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1511940 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28568 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 662170579 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.001134 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.225253 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 81258744 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 595261780 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 133961841 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 80558279 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 597026773 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14270848 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1888771 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 137791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6543938 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 793820 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 311963 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 211646234 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1619349 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28847 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 695097224 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.005850 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.225976 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 344731960 52.06% 52.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 123888404 18.71% 70.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 41617512 6.29% 77.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 151932703 22.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 360486788 51.86% 51.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 129920524 18.69% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 44826389 6.45% 77.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 159863523 23.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 662170579 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.188956 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.839852 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 93652150 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 319101856 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 208055943 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 36600277 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4760353 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17735520 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1981049 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 585316730 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21686226 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4760353 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 127273008 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 44978505 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 215016897 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 210494675 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 59647141 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 569572737 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5483527 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8310630 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 236317 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 296206 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 25698514 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 13591 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 543172602 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 884661173 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 673765883 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 933137 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 489609146 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 53563450 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15680851 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13859127 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 73666324 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 93680638 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 80687792 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8658535 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7660349 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 547737456 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15869030 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 553093233 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2542275 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 47705580 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32628806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 263861 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 662170579 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.835273 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.067651 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 695097224 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.189946 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.844029 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 99752260 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 332349824 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 219841712 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 38085588 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5067840 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18995502 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2109796 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 616514692 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22877728 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5067840 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 135033848 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 48639647 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 225189127 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 222148294 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 59018468 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 599774214 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5804898 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8803158 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 361913 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 923044 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 23085631 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 14113 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 571116000 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 927515458 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 708750961 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 721490 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 514023695 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 57092304 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 16265387 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 14239236 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76589893 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 99537313 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 83963206 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 9607701 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 8257946 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 576970515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 16478044 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 581773999 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2685793 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 50643585 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 34938077 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 295595 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 695097224 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.836968 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.068825 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 358036858 54.07% 54.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 130663379 19.73% 73.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 105371554 15.91% 89.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 60712008 9.17% 98.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7383178 1.11% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3602 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 375720628 54.05% 54.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 136500819 19.64% 73.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 111041420 15.97% 89.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 64151608 9.23% 98.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7678235 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4508 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 6 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 662170579 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 695097224 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 55137578 43.73% 43.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 43337 0.03% 43.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 11462 0.01% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 21 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 33948572 26.92% 70.70% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 36949037 29.30% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 58467261 44.14% 44.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 65736 0.05% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 8975 0.01% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 28 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 36077917 27.24% 71.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 37847209 28.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 376818141 68.13% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1181294 0.21% 68.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 70304 0.01% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 78003 0.01% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 96248927 17.40% 85.77% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 78696516 14.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 396486231 68.15% 68.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1392625 0.24% 68.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 78812 0.01% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 42928 0.01% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 101899765 17.52% 85.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 81873638 14.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 553093233 # Type of FU issued -system.cpu1.iq.rate 0.823671 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 126090007 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227972 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1895671563 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 610922154 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 537423673 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1317762 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 530370 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 489519 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 678367586 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 815653 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2464833 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 581773999 # Type of FU issued +system.cpu1.iq.rate 0.824905 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 132467126 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227695 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1992741902 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 643831652 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 565540483 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1056239 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 418449 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 388115 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 713583395 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 657730 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2682619 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11666973 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 15967 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 141534 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5620813 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12570649 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16823 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 158978 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5834378 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2485085 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4066782 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2724944 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3729174 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4760353 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6088373 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2643428 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 563729528 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 5067840 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 8144414 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2028582 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 593577386 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 93680638 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 80687792 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13644540 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 61293 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2520664 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 141534 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1916152 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2651693 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4567845 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 545961284 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 93419699 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6590982 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 99537313 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 83963206 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 14010879 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 57965 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1901764 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 158978 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2040667 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2820650 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4861317 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 574179310 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 98827451 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6993764 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 123042 # number of nop insts executed -system.cpu1.iew.exec_refs 170926883 # number of memory reference insts executed -system.cpu1.iew.exec_branches 102016204 # Number of branches executed -system.cpu1.iew.exec_stores 77507184 # Number of stores executed -system.cpu1.iew.exec_rate 0.813050 # Inst execution rate -system.cpu1.iew.wb_sent 538581721 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 537913192 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 259879872 # num instructions producing a value -system.cpu1.iew.wb_consumers 425846883 # num instructions consuming a value +system.cpu1.iew.exec_nop 128827 # number of nop insts executed +system.cpu1.iew.exec_refs 179445358 # number of memory reference insts executed +system.cpu1.iew.exec_branches 107524158 # Number of branches executed +system.cpu1.iew.exec_stores 80617907 # Number of stores executed +system.cpu1.iew.exec_rate 0.814136 # Inst execution rate +system.cpu1.iew.wb_sent 566651750 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 565928598 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 274900610 # num instructions producing a value +system.cpu1.iew.wb_consumers 450009146 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.801064 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610266 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.802437 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610878 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 44555907 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15605169 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4282930 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 653744993 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.784392 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.576833 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 47337627 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 16182449 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4550579 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 686146419 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.786229 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.582193 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 427404365 65.38% 65.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 119117281 18.22% 83.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 49133324 7.52% 91.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16524443 2.53% 93.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11998035 1.84% 95.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8093886 1.24% 96.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5471403 0.84% 97.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3473274 0.53% 98.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12528982 1.92% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 448874592 65.42% 65.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 124520992 18.15% 83.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 51724584 7.54% 91.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 17115210 2.49% 93.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12441515 1.81% 95.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8692682 1.27% 96.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5812900 0.85% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3666336 0.53% 98.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 13297608 1.94% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 653744993 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 435068948 # Number of instructions committed -system.cpu1.commit.committedOps 512792020 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 686146419 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 458333534 # Number of instructions committed +system.cpu1.commit.committedOps 539467876 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 157080643 # Number of memory references committed -system.cpu1.commit.loads 82013664 # Number of loads committed -system.cpu1.commit.membars 3580423 # Number of memory barriers committed -system.cpu1.commit.branches 96770677 # Number of branches committed -system.cpu1.commit.fp_insts 477739 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 470356347 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12430117 # Number of function calls committed. +system.cpu1.commit.refs 165095491 # Number of memory references committed +system.cpu1.commit.loads 86966664 # Number of loads committed +system.cpu1.commit.membars 3858042 # Number of memory barriers committed +system.cpu1.commit.branches 101991370 # Number of branches committed +system.cpu1.commit.fp_insts 379596 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 495494093 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13607824 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 354618766 69.15% 69.15% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 966577 0.19% 69.34% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 56200 0.01% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 69792 0.01% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82013664 15.99% 85.36% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 75066979 14.64% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 373132612 69.17% 69.17% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1140635 0.21% 69.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 62088 0.01% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 37050 0.01% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 86966664 16.12% 85.52% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78128827 14.48% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 512792020 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12528982 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 539467876 # Class of committed instruction +system.cpu1.commit.bw_lim_events 13297608 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1194813735 # The number of ROB reads -system.cpu1.rob.rob_writes 1123082959 # The number of ROB writes -system.cpu1.timesIdled 724798 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 9327466 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94087851225 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 435068948 # Number of Instructions Simulated -system.cpu1.committedOps 512792020 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.543429 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.543429 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.647908 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.647908 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 645605353 # number of integer regfile reads -system.cpu1.int_regfile_writes 381721004 # number of integer regfile writes -system.cpu1.fp_regfile_reads 775313 # number of floating regfile reads -system.cpu1.fp_regfile_writes 445860 # number of floating regfile writes -system.cpu1.cc_regfile_reads 118711593 # number of cc regfile reads -system.cpu1.cc_regfile_writes 119446570 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2680324661 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15740060 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5270583 # number of replacements -system.cpu1.dcache.tags.tagsinuse 418.735038 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 145844611 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5271093 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.668761 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8472891797000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 418.735038 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.817842 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.817842 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 326008687 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 326008687 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76031229 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76031229 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 65289331 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 65289331 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171825 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 171825 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 535551 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 535551 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1744878 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1744878 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734724 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1734724 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 141320560 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141320560 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 141492385 # number of overall hits -system.cpu1.dcache.overall_hits::total 141492385 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6360074 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6360074 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7315323 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7315323 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 690767 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 690767 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 239985 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 239985 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206300 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 206300 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13675397 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13675397 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14366164 # number of overall misses -system.cpu1.dcache.overall_misses::total 14366164 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96502365280 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 96502365280 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 122289774326 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 122289774326 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3384586861 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3384586861 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4391846948 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4391846948 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4067000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4067000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 218792139606 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 218792139606 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82391303 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82391303 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72604654 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72604654 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 862592 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 862592 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 535551 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 535551 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1984863 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1984863 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1941024 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1941024 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154995957 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154995957 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155858549 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155858549 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077194 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.077194 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.100756 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.100756 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.800804 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.800804 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120908 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120908 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088231 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.088231 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092174 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.092174 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16716.934348 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14103.326712 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 1255653176 # The number of ROB reads +system.cpu1.rob.rob_writes 1182522736 # The number of ROB writes +system.cpu1.timesIdled 784634 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 10164744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94139293558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 458333534 # Number of Instructions Simulated +system.cpu1.committedOps 539467876 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.538753 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.538753 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.649877 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.649877 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 678371688 # number of integer regfile reads +system.cpu1.int_regfile_writes 402814905 # number of integer regfile writes +system.cpu1.fp_regfile_reads 627803 # number of floating regfile reads +system.cpu1.fp_regfile_writes 323588 # number of floating regfile writes +system.cpu1.cc_regfile_reads 123299886 # number of cc regfile reads +system.cpu1.cc_regfile_writes 123979632 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2817640596 # number of misc regfile reads +system.cpu1.misc_regfile_writes 16155257 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5719154 # number of replacements +system.cpu1.dcache.tags.tagsinuse 428.720007 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153241322 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5719665 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 26.792010 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8515430590500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.720007 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837344 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.837344 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 342874086 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 342874086 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 80584085 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 80584085 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68058878 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68058878 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187635 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187635 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 112453 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 112453 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1764554 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1764554 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1816897 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1816897 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 148642963 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 148642963 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 148830598 # number of overall hits +system.cpu1.dcache.overall_hits::total 148830598 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6869643 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6869643 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7494314 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7494314 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 706318 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 706318 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 458418 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 458418 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288948 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 288948 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190861 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 190861 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 14363957 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 14363957 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 15070275 # number of overall misses +system.cpu1.dcache.overall_misses::total 15070275 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 105402463849 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 105402463849 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 121649241613 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 121649241613 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 17403154350 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 17403154350 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4078869410 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 4078869410 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3937390159 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3937390159 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1956500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1956500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 227051705462 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 227051705462 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 227051705462 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 227051705462 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87453728 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87453728 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75553192 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 75553192 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 893953 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 893953 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 570871 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 570871 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2053502 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2053502 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2007758 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2007758 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 163006920 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 163006920 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 163900873 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 163900873 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099193 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.099193 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790106 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790106 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.803015 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.803015 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140710 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140710 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095062 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095062 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088119 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.088119 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.091947 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.091947 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.222908 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.222908 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16232.205057 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16232.205057 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 37963.505687 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 37963.505687 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14116.274935 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14116.274935 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20629.621342 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20629.621342 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15998.960733 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 8615413 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17976416 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 462301 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 741969 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.635938 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 24.227988 # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 535551 # number of fast writes performed +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15807.044358 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15807.044358 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15066.195239 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15066.195239 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4622048 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18188306 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 368036 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 754235 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.558684 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 24.114906 # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3043634 # number of writebacks -system.cpu1.dcache.writebacks::total 3043634 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3366977 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3366977 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5934775 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5934775 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 123858 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 123858 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9301752 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9301752 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9301752 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9301752 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2993097 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2993097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1369794 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1369794 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 690691 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 690691 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116127 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116127 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206288 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 206288 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4362891 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4362891 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5053582 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5053582 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38940153004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38940153004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23265516814 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23265516814 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16955467787 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16955467787 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 29882890933 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 29882890933 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1431846930 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1431846930 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3970245052 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3970245052 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3877000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3877000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62205669818 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 62205669818 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79161137605 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 79161137605 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 568928684 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 568928684 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 634602446 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 634602446 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1203531130 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1203531130 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036328 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036328 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018866 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018866 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800716 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800716 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058506 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058506 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106278 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106278 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028148 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028148 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032424 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032424 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13009.986981 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13009.986981 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16984.682963 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16984.682963 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24548.557585 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24548.557585 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.008783 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.008783 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.127026 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.127026 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3658567 # number of writebacks +system.cpu1.dcache.writebacks::total 3658567 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3579229 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3579229 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6058526 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 6058526 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3270 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3270 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 146042 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 146042 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9637755 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9637755 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9637755 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9637755 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3290414 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3290414 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1435788 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1435788 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706224 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 706224 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 455148 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 455148 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 142906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 142906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 190858 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 190858 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4726202 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4726202 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5432426 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5432426 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44800014998 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44800014998 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23381887855 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23381887855 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16359112476 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16359112476 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 16414544257 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 16414544257 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1722097666 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1722097666 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3546227841 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3546227841 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1864500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1864500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68181902853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 68181902853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84541015329 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 84541015329 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 790979694 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 790979694 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 944680456 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 944680456 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1735660150 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1735660150 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037625 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037625 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019004 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019004 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790001 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790001 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.797287 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.797287 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069591 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069591 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095060 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095060 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028994 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028994 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033145 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033145 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13615.312541 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13615.312541 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16285.055910 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16285.055910 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23164.197869 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23164.197869 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 36064.190674 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 36064.190674 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12050.562370 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12050.562370 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18580.451650 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18580.451650 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14257.901428 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14257.901428 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15664.361953 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15664.361953 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14426.362405 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14426.362405 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15562.294881 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15562.294881 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2065,446 +2131,464 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5515063 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.927395 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 194540892 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5515575 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 35.271190 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8512592975000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.927395 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980327 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980327 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5881686 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.904324 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 205507195 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5882198 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.937143 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8555135625500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.904324 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980282 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980282 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 371 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 406089111 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 406089111 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 194540892 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 194540892 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 194540892 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 194540892 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 194540892 # number of overall hits -system.cpu1.icache.overall_hits::total 194540892 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5745874 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5745874 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5745874 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5745874 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5745874 # number of overall misses -system.cpu1.icache.overall_misses::total 5745874 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 49972720911 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 49972720911 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 49972720911 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 49972720911 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 49972720911 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 49972720911 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 200286766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 200286766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 200286766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 200286766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 200286766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 200286766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028688 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028688 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028688 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028688 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028688 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028688 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8697.148756 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8697.148756 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8697.148756 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8697.148756 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 4058036 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 429168724 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 429168724 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 205507195 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 205507195 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 205507195 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 205507195 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 205507195 # number of overall hits +system.cpu1.icache.overall_hits::total 205507195 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6136058 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6136058 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6136058 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6136058 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6136058 # number of overall misses +system.cpu1.icache.overall_misses::total 6136058 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53889413624 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 53889413624 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 53889413624 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 53889413624 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 53889413624 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 53889413624 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 211643253 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 211643253 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 211643253 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 211643253 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 211643253 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 211643253 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028992 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028992 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028992 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028992 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028992 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028992 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8782.415946 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8782.415946 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8782.415946 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8782.415946 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8782.415946 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 4496430 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 525950 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 574651 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.715631 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.824627 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 230295 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 230295 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 230295 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 230295 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 230295 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 230295 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5515579 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5515579 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5515579 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5515579 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5515579 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5515579 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 40507461081 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 40507461081 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 40507461081 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 40507461081 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 40507461081 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 40507461081 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6176248 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6176248 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6176248 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6176248 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027538 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027538 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027538 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7344.190171 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 253840 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 253840 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 253840 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 253840 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 253840 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 253840 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5882218 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5882218 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5882218 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5882218 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5882218 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5882218 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43727434357 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 43727434357 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43727434357 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 43727434357 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43727434357 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 43727434357 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6637997 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6637997 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6637997 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6637997 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027793 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027793 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027793 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7433.834373 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7433.834373 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7433.834373 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 50505684 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2064047 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 44628493 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 907161 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 56932742 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2823095 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 47812216 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2677811 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 133845 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2772138 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4283124 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 382726 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3236886 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4916498 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3436745 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13730.844001 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11600969 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3452900 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.359776 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9794240275500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4681.996556 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.505551 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 81.585621 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.676687 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2582.188700 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5714.890886 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.285766 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004303 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004980 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036601 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.157604 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.348809 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.838064 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9001 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7069 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 110 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 838 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3805 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2947 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1301 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 786 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3475 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2116 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 647 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.549377 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.431458 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 248779915 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 248779915 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532626 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 172045 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5284751 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2703668 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8693090 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3043623 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3043623 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 90999 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 90999 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33582 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 33582 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 896481 # 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number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 12743 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 230826 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1092537 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1351909 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 10 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 129352 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 129352 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172689 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 172689 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 17 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 17 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 163956146412 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6077501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 736923302 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 743000803 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 890555024 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 890555024 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6077501 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1627478326 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1633555827 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.279663 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.127597 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.587027 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.587027 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.837195 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.837195 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.198134 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.198134 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.574830 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.574830 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.781453 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.781453 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.196584 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.196584 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135000 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.180399 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.180399 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132931 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026299 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060986 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033413 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.257106 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.382456 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26775.298889 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26588.275709 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32053.702935 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17563.550939 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17563.550939 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13637.442900 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13637.442900 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183352.941176 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183352.941176 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36902.824973 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36902.824973 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28138.464180 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30671.695797 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.401623 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27705.527306 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27112.291240 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36830.440224 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31073.249872 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31073.249872 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17075.365387 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17075.365387 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13826.798875 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13826.798875 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 213785.714286 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 213785.714286 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33235.203246 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33235.203246 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27951.592092 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34315.404261 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39885.781008 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22249.599385 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28587.212018 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36830.440224 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33891.685533 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2514,66 +2598,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 14195138 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10319504 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5540 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5540 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3043633 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 4072942 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1683351 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 535551 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 440112 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 381311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 495883 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1326326 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1162072 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11031290 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15072798 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 408972 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1223990 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27737050 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352998000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 552975725 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1478304 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4387432 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 911839461 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10107713 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 25138246 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.388398 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.487386 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 15325840 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 11081361 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 7210 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 7210 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3658566 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 4807205 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 18 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 637593 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 454086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 471082 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 336358 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 477965 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1352070 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1222067 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11764566 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16293479 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 431287 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1341589 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 29830921 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 376462768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 612089908 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1574800 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4897784 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 995025260 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10166385 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 26584709 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.370632 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.482974 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15374612 61.16% 61.16% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 9763634 38.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 16731578 62.94% 62.94% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 9853131 37.06% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 25138246 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11278575992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 26584709 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12493291014 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 196968741 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175961487 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8281966249 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8832336643 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7967439656 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8528127192 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 225433169 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 235484276 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 677266087 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 730977975 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40417 # Transaction distribution -system.iobus.trans_dist::ReadResp 40417 # Transaction distribution -system.iobus.trans_dist::WriteReq 136643 # Transaction distribution -system.iobus.trans_dist::WriteResp 136782 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 139 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40396 # Transaction distribution +system.iobus.trans_dist::ReadResp 40396 # Transaction distribution +system.iobus.trans_dist::WriteReq 136775 # Transaction distribution +system.iobus.trans_dist::WriteResp 30047 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2588,13 +2672,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354398 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48148 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2609,13 +2693,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156169 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497071 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36581000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2643,678 +2727,710 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 982013630 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1043032876 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93018000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179230570 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179190812 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115615 # number of replacements -system.iocache.tags.tagsinuse 11.386738 # Cycle average of tags in use +system.iocache.tags.replacements 115581 # number of replacements +system.iocache.tags.tagsinuse 11.295325 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9111214571000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.838966 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.547771 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239935 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.471736 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.711671 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9153631711000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.835501 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.459825 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239719 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466239 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705958 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042022 # Number of tag accesses -system.iocache.tags.data_accesses 1042022 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 1040757 # Number of tag accesses +system.iocache.tags.data_accesses 1040757 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 139 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 139 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8889 # number of demand (read+write) misses -system.iocache.demand_misses::total 8929 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8872 # number of demand (read+write) misses +system.iocache.demand_misses::total 8912 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8889 # number of overall misses -system.iocache.overall_misses::total 8929 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5695000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1981823591 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1987518591 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8872 # number of overall misses +system.iocache.overall_misses::total 8912 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1960529318 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1966236318 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 365000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 365000 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6060000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1981823591 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1987883591 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6060000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1981823591 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1987883591 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28841569746 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28841569746 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6072000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1960529318 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1966601318 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6072000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1960529318 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1966601318 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106867 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106867 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8872 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8912 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8872 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8912 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001301 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.001301 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 153918.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 222952.367083 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 222666.210060 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 220979.409152 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 220702.246941 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 121666.666667 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 222952.367083 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 222632.275843 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 222952.367083 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 222632.275843 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55347 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270234.331628 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270234.331628 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151800 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 220668.909111 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151800 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 220979.409152 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 220668.909111 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 224453 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27297 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.081421 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.222625 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 106728 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8872 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8912 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3771000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1519438621 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1523209621 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1499010380 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1502793380 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 209000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 209000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6630698579 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6630698579 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3980000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1519438621 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1523418621 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3980000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1519438621 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1523418621 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23291152308 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23291152308 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3992000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1499010380 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1503002380 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3992000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1499010380 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1503002380 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 101918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170934.708179 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 170648.624356 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168959.691163 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 168682.610843 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.071172 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.071172 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99800 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 168959.691163 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 168649.279623 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1387044 # number of replacements -system.l2c.tags.tagsinuse 64427.808632 # Cycle average of tags in use -system.l2c.tags.total_refs 7620997 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1449367 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.258155 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10003.170740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.441651 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.424548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 921.507825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8419.959281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24297.060802 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 189.151688 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 259.454485 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 442.813505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5057.928398 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14404.895708 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.152636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003714 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.014061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.128478 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370744 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003959 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.006757 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.077178 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.219801 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983090 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33631 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 302 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 28390 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 2393 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1787 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 216 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 21604 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.513168 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004608 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.433197 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 91165244 # Number of tag accesses -system.l2c.tags.data_accesses 91165244 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 7553 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4301 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 170694 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 696092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1825935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 8223 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5157 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 162945 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 691200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1816536 # number of ReadReq hits -system.l2c.ReadReq_hits::total 5388636 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2284318 # number of Writeback hits -system.l2c.Writeback_hits::total 2284318 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 28567 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31425 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 59992 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8944 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7440 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16384 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53362 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53750 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107112 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7553 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4301 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 170694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 749454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1825935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 8223 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5157 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 162945 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 744950 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1816536 # number of demand (read+write) hits -system.l2c.demand_hits::total 5495748 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7553 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4301 # number of overall hits -system.l2c.overall_hits::cpu0.inst 170694 # number of overall hits -system.l2c.overall_hits::cpu0.data 749454 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1825935 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 8223 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5157 # number of overall hits -system.l2c.overall_hits::cpu1.inst 162945 # number of overall hits -system.l2c.overall_hits::cpu1.data 744950 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1816536 # number of overall hits -system.l2c.overall_hits::total 5495748 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5517 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 8182 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 12718 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 197063 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 598730 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 5285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 7231 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 8328 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 136549 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 456002 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1435605 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 38751 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 39177 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77928 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4753250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1380792752 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11742279495 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.168066 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.181431 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.226536 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.384707 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.291075 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.341951 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.524241 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.552613 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.537838 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.553898 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.558488 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.556222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.464945 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.475672 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.470280 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.202855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.214002 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.233479 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.175477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.171245 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.068189 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.202855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.299552 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.307173 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.394840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.214002 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.206057 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.233479 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 83613.975559 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78300.094379 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 138960.075245 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 26965.564241 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27931.878814 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 27341.166584 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10302.647357 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.691394 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10275.094224 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10301.097202 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10284.711472 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10292.768070 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71179.305627 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69289.702936 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70228.797041 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80274.212183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76083.115009 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 135016.780662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79673.516129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79369.146585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 85938.383204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80274.212183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 167573.259393 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72387.659079 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72979.678515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82860.730418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76083.115009 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130872.726307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 135016.780662 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3329,57 +3445,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1503713 # Transaction distribution -system.membus.trans_dist::ReadResp 1503713 # Transaction distribution -system.membus.trans_dist::WriteReq 38586 # Transaction distribution -system.membus.trans_dist::WriteResp 38586 # Transaction distribution -system.membus.trans_dist::Writeback 882638 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 1682947 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 1682947 # Transaction distribution -system.membus.trans_dist::UpgradeReq 373970 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 331267 # Transaction distribution -system.membus.trans_dist::UpgradeResp 103150 # Transaction distribution -system.membus.trans_dist::ReadExReq 170539 # Transaction distribution -system.membus.trans_dist::ReadExResp 155861 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1817706 # Transaction distribution +system.membus.trans_dist::ReadResp 1817706 # Transaction distribution +system.membus.trans_dist::WriteReq 38526 # Transaction distribution +system.membus.trans_dist::WriteResp 38526 # Transaction distribution +system.membus.trans_dist::Writeback 1444194 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 154200 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 154200 # Transaction distribution +system.membus.trans_dist::UpgradeReq 434662 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 279066 # Transaction distribution +system.membus.trans_dist::UpgradeResp 97607 # Transaction distribution +system.membus.trans_dist::ReadExReq 117028 # Transaction distribution +system.membus.trans_dist::ReadExResp 102726 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123062 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26002 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8087433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 8236597 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 229762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 8466359 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6008493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6157429 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6493541 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156169 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52004 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 259532552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 259741319 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7302720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 267044039 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 618323 # Total snoops (count) -system.membus.snoop_fanout::samples 4885385 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 207457224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 207665557 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14110208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 221775765 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 633029 # Total snoops (count) +system.membus.snoop_fanout::samples 4186947 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4885385 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4186947 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4885385 # Request fanout histogram -system.membus.reqLayer0.occupancy 98770920 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4186947 # Request fanout histogram +system.membus.reqLayer0.occupancy 98514469 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21644945 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21244987 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 25191464236 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 16556458898 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 16738053981 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 17312327015 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187451430 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187280188 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3423,49 +3539,49 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 7757807 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7750243 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38586 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38586 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2284318 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1682954 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1576219 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 430271 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 347651 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 777922 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 191 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 316482 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 316482 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11788342 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9897130 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 21685472 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 381410986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320139805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 701550791 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1633796 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12761522 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.009063 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.094770 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 8653355 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 8646086 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38526 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38526 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3063024 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 248029 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 141301 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 493306 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 294608 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 787914 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 273153 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 273153 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10956928 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10351144 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 21308072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 369780529 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 344544100 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 714324629 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1644746 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12968411 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.008917 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.094008 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12645858 99.09% 99.09% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115664 0.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12852771 99.11% 99.11% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115640 0.89% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12761522 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 21862906503 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 12968411 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 19352517195 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 6130500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7381500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 19509958221 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20456793572 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 17925237290 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 20083133002 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 14096 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13518 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4921 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5604 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |