diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual')
5 files changed, 3257 insertions, 3284 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini index 17e0e65c9..11768aa62 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -1423,10 +1423,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -1453,7 +1452,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -1617,12 +1616,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=true -pci_io_base=788529152 system=system [system.realview.aaci_fake] @@ -1715,16 +1711,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -1740,7 +1735,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -1903,13 +1898,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1919,9 +1914,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -1963,7 +1957,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -2044,14 +2038,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2068,7 +2061,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -2083,7 +2076,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -2206,17 +2199,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=12 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=788529152 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -2268,7 +2263,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -2283,7 +2278,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr index 7a8adf6ca..4c70e8d66 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr @@ -11,4 +11,3 @@ warn: allocating bonus target for snoop warn: allocating bonus target for snoop warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: allocating bonus target for snoop diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout index 38e5abd49..cc1e1c387 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 18:32:57 -gem5 executing on e104799-lin, pid 8213 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 13:59:02 +gem5 executing on e104799-lin, pid 13304 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47314506373000 because m5_exit instruction encountered +Exiting @ tick 47393980707000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index d00fb13a2..5e9f9ee14 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.314506 # Number of seconds simulated -sim_ticks 47314506373000 # Number of ticks simulated -final_tick 47314506373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.393981 # Number of seconds simulated +sim_ticks 47393980707000 # Number of ticks simulated +final_tick 47393980707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98624 # Simulator instruction rate (inst/s) -host_op_rate 115961 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5063135105 # Simulator tick rate (ticks/s) -host_mem_usage 768296 # Number of bytes of host memory used -host_seconds 9344.90 # Real time elapsed on the host -sim_insts 921635123 # Number of instructions simulated -sim_ops 1083644532 # Number of ops (including micro ops) simulated +host_inst_rate 118826 # Simulator instruction rate (inst/s) +host_op_rate 139727 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6107626980 # Simulator tick rate (ticks/s) +host_mem_usage 769604 # Number of bytes of host memory used +host_seconds 7759.80 # Real time elapsed on the host +sim_insts 922064003 # Number of instructions simulated +sim_ops 1084251192 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 141824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 130048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4236960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 43669256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 19384064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 193856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 178880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3171232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 16700240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 15629760 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 443968 # Number of bytes read from this memory -system.physmem.bytes_read::total 103880088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4236960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3171232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7408192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 86326016 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 150400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 142336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4326432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 44486728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 20365824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 171008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 152256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3129632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 15575440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14887232 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428800 # Number of bytes read from this memory +system.physmem.bytes_read::total 103816088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4326432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3129632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7456064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 86117376 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 86346600 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2216 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82155 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 682345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 302876 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 49594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 260954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 244215 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6937 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1639148 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1348844 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 86137960 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2350 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 83553 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 695118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 318216 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2672 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2379 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 243379 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 232613 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6700 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1638148 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1345584 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1351418 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 89549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 922957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 409685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 67025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 352962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 330338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2195523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 89549 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 67025 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1824515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1348158 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 91287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 938658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 429713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3608 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 328638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 314117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2190491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 91287 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 157321 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1817053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1824950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1824515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 89549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 923392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 409685 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 67025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 352962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 330338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4020473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1639148 # Number of read requests accepted -system.physmem.writeReqs 1351418 # Number of write requests accepted -system.physmem.readBursts 1639148 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1351418 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104871744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue -system.physmem.bytesWritten 86344960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 103880088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 86346600 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1817487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1817053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 91287 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 939092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 429713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 66034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 328638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 314117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4007978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1638148 # Number of read requests accepted +system.physmem.writeReqs 1348158 # Number of write requests accepted +system.physmem.readBursts 1638148 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1348158 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 104808896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 32576 # Total number of bytes read from write queue +system.physmem.bytesWritten 86137280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 103816088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 86137960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 509 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 532498 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 106578 # Per bank write bursts -system.physmem.perBankRdBursts::1 104344 # Per bank write bursts -system.physmem.perBankRdBursts::2 100892 # Per bank write bursts -system.physmem.perBankRdBursts::3 102125 # Per bank write bursts -system.physmem.perBankRdBursts::4 100013 # Per bank write bursts -system.physmem.perBankRdBursts::5 109287 # Per bank write bursts -system.physmem.perBankRdBursts::6 101103 # Per bank write bursts -system.physmem.perBankRdBursts::7 99682 # Per bank write bursts -system.physmem.perBankRdBursts::8 97394 # Per bank write bursts -system.physmem.perBankRdBursts::9 128253 # Per bank write bursts -system.physmem.perBankRdBursts::10 98226 # Per bank write bursts -system.physmem.perBankRdBursts::11 99141 # Per bank write bursts -system.physmem.perBankRdBursts::12 97088 # Per bank write bursts -system.physmem.perBankRdBursts::13 102696 # Per bank write bursts -system.physmem.perBankRdBursts::14 95500 # Per bank write bursts -system.physmem.perBankRdBursts::15 96299 # Per bank write bursts -system.physmem.perBankWrBursts::0 86551 # Per bank write bursts -system.physmem.perBankWrBursts::1 88756 # Per bank write bursts -system.physmem.perBankWrBursts::2 83871 # Per bank write bursts -system.physmem.perBankWrBursts::3 85066 # Per bank write bursts -system.physmem.perBankWrBursts::4 83226 # Per bank write bursts -system.physmem.perBankWrBursts::5 90269 # Per bank write bursts -system.physmem.perBankWrBursts::6 84251 # Per bank write bursts -system.physmem.perBankWrBursts::7 84163 # Per bank write bursts -system.physmem.perBankWrBursts::8 81439 # Per bank write bursts -system.physmem.perBankWrBursts::9 87752 # Per bank write bursts -system.physmem.perBankWrBursts::10 80936 # Per bank write bursts -system.physmem.perBankWrBursts::11 83767 # Per bank write bursts -system.physmem.perBankWrBursts::12 81736 # Per bank write bursts -system.physmem.perBankWrBursts::13 86099 # Per bank write bursts -system.physmem.perBankWrBursts::14 79882 # Per bank write bursts -system.physmem.perBankWrBursts::15 81376 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 529318 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 98506 # Per bank write bursts +system.physmem.perBankRdBursts::1 102125 # Per bank write bursts +system.physmem.perBankRdBursts::2 96514 # Per bank write bursts +system.physmem.perBankRdBursts::3 101212 # Per bank write bursts +system.physmem.perBankRdBursts::4 98283 # Per bank write bursts +system.physmem.perBankRdBursts::5 109978 # Per bank write bursts +system.physmem.perBankRdBursts::6 106703 # Per bank write bursts +system.physmem.perBankRdBursts::7 105175 # Per bank write bursts +system.physmem.perBankRdBursts::8 93813 # Per bank write bursts +system.physmem.perBankRdBursts::9 120186 # Per bank write bursts +system.physmem.perBankRdBursts::10 99379 # Per bank write bursts +system.physmem.perBankRdBursts::11 109206 # Per bank write bursts +system.physmem.perBankRdBursts::12 97639 # Per bank write bursts +system.physmem.perBankRdBursts::13 103304 # Per bank write bursts +system.physmem.perBankRdBursts::14 94884 # Per bank write bursts +system.physmem.perBankRdBursts::15 100732 # Per bank write bursts +system.physmem.perBankWrBursts::0 82092 # Per bank write bursts +system.physmem.perBankWrBursts::1 86582 # Per bank write bursts +system.physmem.perBankWrBursts::2 80748 # Per bank write bursts +system.physmem.perBankWrBursts::3 83407 # Per bank write bursts +system.physmem.perBankWrBursts::4 81928 # Per bank write bursts +system.physmem.perBankWrBursts::5 88947 # Per bank write bursts +system.physmem.perBankWrBursts::6 86848 # Per bank write bursts +system.physmem.perBankWrBursts::7 87370 # Per bank write bursts +system.physmem.perBankWrBursts::8 79257 # Per bank write bursts +system.physmem.perBankWrBursts::9 83439 # Per bank write bursts +system.physmem.perBankWrBursts::10 82066 # Per bank write bursts +system.physmem.perBankWrBursts::11 89206 # Per bank write bursts +system.physmem.perBankWrBursts::12 82040 # Per bank write bursts +system.physmem.perBankWrBursts::13 87648 # Per bank write bursts +system.physmem.perBankWrBursts::14 80198 # Per bank write bursts +system.physmem.perBankWrBursts::15 84119 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 31 # Number of times write queue was full causing retry -system.physmem.totGap 47314504873500 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times write queue was full causing retry +system.physmem.totGap 47393979099500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1617790 # Read request sizes (log2) +system.physmem.readPktSize::6 1616790 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1348844 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 620628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 413232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 168696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 160410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 100263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 61902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31024 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1345584 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 619728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 417888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 167778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 159876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 99605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 61553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,169 +188,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 21855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 54078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 72022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 78343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 84949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 88390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 91151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 97634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 95478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 99505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 99115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 88325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 81966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 36742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 54132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 72218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 78252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 84742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 88110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 91290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 97437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 95426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 99220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 110773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 98211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 87853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 81636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1061449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 180.146498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.187522 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.320652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 660214 62.20% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 197053 18.56% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 62946 5.93% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34930 3.29% 89.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24785 2.34% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13743 1.29% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13849 1.30% 94.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7639 0.72% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46290 4.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1061449 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 76381 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.453032 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 249.608933 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 76378 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::50 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1054994 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 180.992301 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.466356 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 240.522304 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 655278 62.11% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 195680 18.55% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 62552 5.93% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34743 3.29% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24726 2.34% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13789 1.31% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13873 1.31% 94.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7523 0.71% 95.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46830 4.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1054994 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 76193 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.493169 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 249.861284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 76190 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 76381 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 76381 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.663293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.185244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.515109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 70865 92.78% 92.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3094 4.05% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 460 0.60% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 346 0.45% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 86 0.11% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 303 0.40% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 170 0.22% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 108 0.14% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 111 0.15% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 84 0.11% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 42 0.05% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 72 0.09% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 382 0.50% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 49 0.06% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 51 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 81 0.11% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 17 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 76193 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 76193 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.664287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.191501 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.434084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 70631 92.70% 92.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3142 4.12% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 485 0.64% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 323 0.42% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 79 0.10% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 306 0.40% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 178 0.23% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 116 0.15% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 95 0.12% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 99 0.13% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 41 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 55 0.07% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 407 0.53% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 35 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 33 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 86 0.11% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 20 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 28 0.04% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 76381 # Writes before turning the bus around for reads -system.physmem.totQLat 70826288095 # Total ticks spent queuing -system.physmem.totMemAccLat 101550431845 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8193105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43223.11 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 76193 # Writes before turning the bus around for reads +system.physmem.totQLat 70239099561 # Total ticks spent queuing +system.physmem.totMemAccLat 100944830811 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8188195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 42890.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 61973.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 61640.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.20 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.33 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing -system.physmem.readRowHits 1314681 # Number of row buffer hits during reads -system.physmem.writeRowHits 611629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 45.33 # Row buffer hit rate for writes -system.physmem.avgGap 15821254.20 # Average gap between requests -system.physmem.pageHitRate 64.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4090980600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2232181875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6427387200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4446271440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3090353329440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1181376195975 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27352407006750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31641333353280 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.744914 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45502947755010 # Time in different power states -system.physmem_0.memoryStateTime::REF 1579935240000 # Time in different power states +system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing +system.physmem.readRowHits 1316973 # Number of row buffer hits during reads +system.physmem.writeRowHits 611565 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 45.44 # Row buffer hit rate for writes +system.physmem.avgGap 15870436.28 # Average gap between requests +system.physmem.pageHitRate 64.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4035157560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2201722875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6384222000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4392934560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3095544201360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1182732038730 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27398902223250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31694192500335 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.738819 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45580299815708 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582589060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 231620211240 # Time in different power states +system.physmem_0.memoryStateTime::ACT 231091139792 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3933573840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2146295250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6353809800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4296155760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3090353329440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1178540083170 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27354894825000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31640518072260 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.727683 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45507092069935 # Time in different power states -system.physmem_1.memoryStateTime::REF 1579935240000 # Time in different power states +system.physmem_1.actEnergy 3940597080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2150127375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6389315400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4328465040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3095544201360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1183329754695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27398377902750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31694060363700 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.736031 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45579400276584 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582589060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 227478372065 # Time in different power states +system.physmem_1.memoryStateTime::ACT 231988109666 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -384,15 +378,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 132773230 # Number of BP lookups -system.cpu0.branchPred.condPredicted 87983669 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6601963 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 93351299 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61553732 # Number of BTB hits +system.cpu0.branchPred.lookups 135522453 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89756354 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6696164 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 95487916 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 63232655 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.937735 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18245658 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 197691 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.220583 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18624977 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 201233 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -423,85 +417,85 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 574649 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 574649 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12370 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88781 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 269295 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 305354 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2428.535405 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14847.246962 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 302828 99.17% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1395 0.46% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 849 0.28% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 146 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 590400 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 590400 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12973 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94460 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 278631 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 311769 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2427.181663 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14785.327659 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 309280 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1331 0.43% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 885 0.28% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 124 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.97% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::327680-393215 73 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 305354 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 295785 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20483.935967 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17662.897721 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 19270.228379 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 292925 99.03% 99.03% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 638 0.22% 99.25% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1609 0.54% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 142 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 290 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 80 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 60 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 29 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 295785 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 533721818468 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.601728 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.544409 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 532429522968 99.76% 99.76% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 722596500 0.14% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 256398500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 121663500 0.02% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 95265000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 53651000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 19676500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 22307000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 728500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 533721818468 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 88781 87.77% 87.77% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12370 12.23% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 101151 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 574649 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::393216-458751 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 311769 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 310891 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20766.069137 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17798.694444 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 20375.668326 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 307651 98.96% 98.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 747 0.24% 99.20% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1834 0.59% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 107 0.03% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 307 0.10% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 102 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 75 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 36 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 310891 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 523001837252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.567345 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.551290 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 521647732752 99.74% 99.74% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 761373500 0.15% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 275460500 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 125915000 0.02% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 99351000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 52861000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 16652500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 21714500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 741500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 35000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 523001837252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 94460 87.92% 87.92% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12973 12.08% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107433 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 590400 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 574649 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101151 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 590400 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107433 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101151 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 675800 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107433 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 697833 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 96498807 # DTB read hits -system.cpu0.dtb.read_misses 413728 # DTB read misses -system.cpu0.dtb.write_hits 78559139 # DTB write hits -system.cpu0.dtb.write_misses 160921 # DTB write misses +system.cpu0.dtb.read_hits 98363253 # DTB read hits +system.cpu0.dtb.read_misses 426453 # DTB read misses +system.cpu0.dtb.write_hits 80524387 # DTB write hits +system.cpu0.dtb.write_misses 163947 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38359 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 510 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7352 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 40807 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 204 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7493 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 37571 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 96912535 # DTB read accesses -system.cpu0.dtb.write_accesses 78720060 # DTB write accesses +system.cpu0.dtb.perms_faults 42725 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 98789706 # DTB read accesses +system.cpu0.dtb.write_accesses 80688334 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 175057946 # DTB hits -system.cpu0.dtb.misses 574649 # DTB misses -system.cpu0.dtb.accesses 175632595 # DTB accesses +system.cpu0.dtb.hits 178887640 # DTB hits +system.cpu0.dtb.misses 590400 # DTB misses +system.cpu0.dtb.accesses 179478040 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -531,210 +525,206 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 78486 # Table walker walks requested -system.cpu0.itb.walker.walksLong 78486 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 887 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55688 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9272 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 69214 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1487.228017 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 11268.156243 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 68484 98.95% 98.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 441 0.64% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 31 0.04% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 33 0.05% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 145 0.21% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 56 0.08% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 69214 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 65847 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26575.804517 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 22865.862438 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 26620.164914 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 64258 97.59% 97.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 112 0.17% 97.76% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1232 1.87% 99.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 99 0.15% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 79 0.12% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 85262 # Table walker walks requested +system.cpu0.itb.walker.walksLong 85262 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1098 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61891 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9791 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 75471 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1466.000186 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11351.229924 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 75137 99.56% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 79 0.10% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 235 0.31% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 75471 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72780 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26660.353119 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23025.074927 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 26139.582838 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 71045 97.62% 97.62% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 123 0.17% 97.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1365 1.88% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.13% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 88 0.12% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 30 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 65847 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 404869617088 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.839049 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.367685 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 65190904252 16.10% 16.10% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 339654890336 83.89% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 21211000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 2423500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 188000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 404869617088 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 55688 98.43% 98.43% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 887 1.57% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 56575 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 72780 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 389854695076 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.839132 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.367626 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 62743884640 16.09% 16.09% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 327084697936 83.90% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 23698000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2390500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 24000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 389854695076 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 61891 98.26% 98.26% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1098 1.74% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 62989 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78486 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78486 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85262 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85262 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56575 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56575 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 135061 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 209228100 # ITB inst hits -system.cpu0.itb.inst_misses 78486 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62989 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62989 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 148251 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 213975614 # ITB inst hits +system.cpu0.itb.inst_misses 85262 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 27529 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 29309 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 202656 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 214464 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 209306586 # ITB inst accesses -system.cpu0.itb.hits 209228100 # DTB hits -system.cpu0.itb.misses 78486 # DTB misses -system.cpu0.itb.accesses 209306586 # DTB accesses -system.cpu0.numCycles 789288757 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 214060876 # ITB inst accesses +system.cpu0.itb.hits 213975614 # DTB hits +system.cpu0.itb.misses 85262 # DTB misses +system.cpu0.itb.accesses 214060876 # DTB accesses +system.cpu0.numCycles 807659312 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 88186567 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 587222731 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 132773230 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 79799390 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 653950437 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14236776 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1849931 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 326899 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 5945958 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 775108 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 835772 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 209027134 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1689441 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 26384 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 758989060 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.905560 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.200949 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 88233839 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 599476727 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 135522453 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81857632 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 670713114 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14447630 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2036483 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 334818 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6261942 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 813783 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 863786 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 213760838 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1698349 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28412 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 776481580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.903685 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.199979 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 429796828 56.63% 56.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 127839256 16.84% 73.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 44588296 5.87% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 156764680 20.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 440207018 56.69% 56.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 130689201 16.83% 73.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 45750499 5.89% 79.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 159834862 20.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 758989060 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.168219 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.743990 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 104466806 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 394260374 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 219139619 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 36084867 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5037394 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19164568 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2120604 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 606612799 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 22830363 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5037394 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 138662412 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 63104555 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 247113571 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 220473798 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 84597330 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 589875332 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 5798642 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10641909 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 381250 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 853231 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 50687884 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 10092 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 564041119 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 911558490 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 696481853 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 699850 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 508008632 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 56032481 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 14857922 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 12905611 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 72985645 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 96647129 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 81788442 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8697028 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7422933 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 568689811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 14912069 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 572654206 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2621739 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 52458189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 34404562 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 258659 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 758989060 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.754496 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.046900 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 776481580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.167797 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.742240 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 105533428 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 405339788 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 223093644 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 37388098 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5126622 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19615970 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2136984 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 619581339 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23102207 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5126622 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 140592491 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 65041706 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 253704898 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 224831888 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 87183975 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 602582059 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 5894427 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10859505 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 384608 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 879717 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 52095352 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 10977 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 576174683 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 933371731 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 711261087 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 684793 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 519247735 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 56926942 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15518812 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13493208 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 75428854 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 98376014 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 83834868 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8883598 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7640207 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 580665271 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15522553 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 585221400 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2674583 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 53398017 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 34936380 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 261009 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 776481580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.753684 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.045500 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 446419238 58.82% 58.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 130584028 17.20% 76.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 111330924 14.67% 90.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 63215854 8.33% 99.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7434312 0.98% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4704 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 456332573 58.77% 58.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 134692381 17.35% 76.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 113447710 14.61% 90.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 64406978 8.29% 99.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7597025 0.98% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 4913 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 758989060 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 776481580 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 59334745 45.62% 45.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 61701 0.05% 45.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34211739 26.30% 71.98% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 36440950 28.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 60244006 45.44% 45.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 62130 0.05% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15273 0.01% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 15 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 34917494 26.34% 71.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 37330795 28.16% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 391815865 68.42% 68.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1438003 0.25% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 75602 0.01% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 400469737 68.43% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1445270 0.25% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 74848 0.01% 68.69% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.69% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued @@ -757,949 +747,948 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 42288 0.01% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 99488891 17.37% 86.07% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 79793556 13.93% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 41036 0.01% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 101401840 17.33% 86.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 81788668 13.98% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 572654206 # Type of FU issued -system.cpu0.iq.rate 0.725532 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 130064790 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227126 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2035873022 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 635743875 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 556160378 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1110977 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 443650 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 409772 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 702028683 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 690312 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2617659 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 585221400 # Type of FU issued +system.cpu0.iq.rate 0.724589 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 132569713 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.226529 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2081071755 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 649281804 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 568296572 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1096919 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 437057 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 404655 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 717109128 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 681984 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2687978 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 11976787 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15696 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 128509 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5549515 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12198109 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15815 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 133954 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5685458 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2485031 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4622903 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2533664 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4860713 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5037394 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7963594 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 7170717 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 583715188 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5126622 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8215667 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7173428 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 596307716 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 96647129 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 81788442 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12627210 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54569 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 7047111 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 128509 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1976888 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2838838 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4815726 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 565090405 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 96493854 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 6996299 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 98376014 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 83834868 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13216543 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 57072 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7044703 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 133954 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2031236 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2866413 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4897649 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 577519741 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 98358575 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7118543 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 113308 # number of nop insts executed -system.cpu0.iew.exec_refs 175051410 # number of memory reference insts executed -system.cpu0.iew.exec_branches 106737211 # Number of branches executed -system.cpu0.iew.exec_stores 78557556 # Number of stores executed -system.cpu0.iew.exec_rate 0.715949 # Inst execution rate -system.cpu0.iew.wb_sent 557331942 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 556570150 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 270940614 # num instructions producing a value -system.cpu0.iew.wb_consumers 444738310 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.705154 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609214 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 45776609 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14653410 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4520969 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 750266004 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.707940 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.517135 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 119892 # number of nop insts executed +system.cpu0.iew.exec_refs 178881734 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109041178 # Number of branches executed +system.cpu0.iew.exec_stores 80523159 # Number of stores executed +system.cpu0.iew.exec_rate 0.715054 # Inst execution rate +system.cpu0.iew.wb_sent 569480217 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 568701227 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 276442254 # num instructions producing a value +system.cpu0.iew.wb_consumers 453748356 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.704135 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609241 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 46598328 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15261544 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4598971 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 767596191 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.707129 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.516118 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 517711139 69.00% 69.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 119807975 15.97% 84.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 52242096 6.96% 91.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 17345693 2.31% 94.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12502849 1.67% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8569717 1.14% 97.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5628818 0.75% 97.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3480187 0.46% 98.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 12977530 1.73% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 529386438 68.97% 68.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 123369518 16.07% 85.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 53181556 6.93% 91.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 17664925 2.30% 94.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 12675398 1.65% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8710511 1.13% 97.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5748655 0.75% 97.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3557202 0.46% 98.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13301988 1.73% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 750266004 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 452897446 # Number of instructions committed -system.cpu0.commit.committedOps 531143684 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 767596191 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 462839739 # Number of instructions committed +system.cpu0.commit.committedOps 542789800 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 160909268 # Number of memory references committed -system.cpu0.commit.loads 84670341 # Number of loads committed -system.cpu0.commit.membars 3612111 # Number of memory barriers committed -system.cpu0.commit.branches 101352463 # Number of branches committed -system.cpu0.commit.fp_insts 401266 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 487082373 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13540419 # Number of function calls committed. +system.cpu0.commit.refs 164327314 # Number of memory references committed +system.cpu0.commit.loads 86177904 # Number of loads committed +system.cpu0.commit.membars 3634236 # Number of memory barriers committed +system.cpu0.commit.branches 103555612 # Number of branches committed +system.cpu0.commit.fp_insts 396011 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 497579695 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13818381 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 368934944 69.46% 69.46% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1203387 0.23% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 59505 0.01% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 36580 0.01% 69.71% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84670341 15.94% 85.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 76238927 14.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 377157891 69.49% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1210852 0.22% 69.71% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 58620 0.01% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.72% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 35123 0.01% 69.73% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.73% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.73% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.73% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 86177904 15.88% 85.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 78149410 14.40% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 531143684 # Class of committed instruction -system.cpu0.commit.bw_lim_events 12977530 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1309875410 # The number of ROB reads -system.cpu0.rob.rob_writes 1162529912 # The number of ROB writes -system.cpu0.timesIdled 987855 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 30299697 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93839724027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 452897446 # Number of Instructions Simulated -system.cpu0.committedOps 531143684 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.742754 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.742754 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.573805 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.573805 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 666947650 # number of integer regfile reads -system.cpu0.int_regfile_writes 396615179 # number of integer regfile writes -system.cpu0.fp_regfile_reads 682678 # number of floating regfile reads -system.cpu0.fp_regfile_writes 298828 # number of floating regfile writes -system.cpu0.cc_regfile_reads 124079442 # number of cc regfile reads -system.cpu0.cc_regfile_writes 124706529 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1318525921 # number of misc regfile reads -system.cpu0.misc_regfile_writes 14734262 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 5881965 # number of replacements -system.cpu0.dcache.tags.tagsinuse 478.956800 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149156359 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5882471 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.356072 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 542789800 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13301988 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1339296609 # The number of ROB reads +system.cpu0.rob.rob_writes 1187626415 # The number of ROB writes +system.cpu0.timesIdled 1008617 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 31177732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93980302134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 462839739 # Number of Instructions Simulated +system.cpu0.committedOps 542789800 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.745009 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.745009 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.573063 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.573063 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 681400785 # number of integer regfile reads +system.cpu0.int_regfile_writes 404691660 # number of integer regfile writes +system.cpu0.fp_regfile_reads 669454 # number of floating regfile reads +system.cpu0.fp_regfile_writes 305508 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127155216 # number of cc regfile reads +system.cpu0.cc_regfile_writes 127713312 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1347757085 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15341922 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6037671 # number of replacements +system.cpu0.dcache.tags.tagsinuse 477.387062 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 152039806 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6038183 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.179728 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.956800 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.935463 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.935463 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 506 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 334047120 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 334047120 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 78452229 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78452229 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 65886147 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 65886147 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209885 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 209885 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258671 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 258671 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1757048 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1757048 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1773588 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1773588 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 144338376 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 144338376 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 144548261 # number of overall hits -system.cpu0.dcache.overall_hits::total 144548261 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6459284 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6459284 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7288144 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7288144 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 689122 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 689122 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 817042 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 817042 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 245228 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 245228 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 193470 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 193470 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13747428 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13747428 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 14436550 # number of overall misses -system.cpu0.dcache.overall_misses::total 14436550 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110052955500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 110052955500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 170225463786 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 170225463786 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 91498155223 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 91498155223 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3890581500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3890581500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5535454500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5535454500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 8571500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 8571500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 280278419286 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 280278419286 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 280278419286 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 280278419286 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 84911513 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 84911513 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73174291 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73174291 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899007 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 899007 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1075713 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1075713 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2002276 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2002276 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1967058 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1967058 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 158085804 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 158085804 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 158984811 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 158984811 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076071 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.076071 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099600 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.099600 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766537 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766537 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759535 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759535 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122475 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122475 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098355 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098355 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086962 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086962 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090805 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.090805 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17037.949640 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17037.949640 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23356.490183 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23356.490183 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111987.089064 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111987.089064 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15865.160177 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15865.160177 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28611.435882 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28611.435882 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 477.387062 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.932397 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.932397 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 341097294 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 341097294 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79771007 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79771007 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67422867 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 67422867 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213459 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 213459 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258123 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 258123 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1760749 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1760749 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1785447 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1785447 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 147193874 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 147193874 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147407333 # number of overall hits +system.cpu0.dcache.overall_hits::total 147407333 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6628879 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6628879 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7648651 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7648651 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 727328 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 727328 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823977 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 823977 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 249122 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 249122 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189214 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 189214 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14277530 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14277530 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15004858 # number of overall misses +system.cpu0.dcache.overall_misses::total 15004858 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 114348877500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 114348877500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 176760598457 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 176760598457 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 91829921579 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 91829921579 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3934102000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3934102000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5393439500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5393439500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4601000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4601000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 291109475957 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 291109475957 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 291109475957 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 291109475957 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 86399886 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 86399886 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 75071518 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 75071518 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 940787 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 940787 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082100 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1082100 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2009871 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2009871 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1974661 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1974661 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 161471404 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 161471404 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 162412191 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 162412191 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076723 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.076723 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101885 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.101885 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.773106 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.773106 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.761461 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.761461 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.123949 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.123949 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095821 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095821 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.088421 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.088421 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092388 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092388 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17250.107824 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17250.107824 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23110.035803 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23110.035803 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111447.190369 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111447.190369 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15791.869044 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15791.869044 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28504.442060 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28504.442060 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.698651 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20387.698651 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19414.501338 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19414.501338 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 28857818 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25701299 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 757026 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 713337 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.119983 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 36.029673 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20389.344372 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20389.344372 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19401.015055 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19401.015055 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 28956080 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 26869955 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 763930 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 756063 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.904101 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 35.539307 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5882015 # number of writebacks -system.cpu0.dcache.writebacks::total 5882015 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3286907 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3286907 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5842010 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 5842010 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4476 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4476 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 122858 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 122858 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9128917 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9128917 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9128917 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9128917 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3172377 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3172377 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1446134 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1446134 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 682277 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 682277 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 812566 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 812566 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122370 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122370 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 193461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4618511 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4618511 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5300788 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5300788 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32879 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32981 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65860 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49995905500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49995905500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39710234771 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39710234771 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17655223500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17655223500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 90433652723 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 90433652723 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1780369000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1780369000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5342108500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5342108500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 8456500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 8456500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 89706140271 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 89706140271 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 107361363771 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 107361363771 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6303225000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6303225000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6238855500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6238855500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12542080500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12542080500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037361 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037361 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019763 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019763 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758923 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758923 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.755374 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.755374 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061115 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061115 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098350 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098350 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029215 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029215 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033341 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033341 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15759.761687 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.761687 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27459.581734 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27459.581734 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25876.914362 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25876.914362 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 111293.916707 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 111293.916707 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14549.064313 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14549.064313 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27613.361349 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27613.361349 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6037757 # number of writebacks +system.cpu0.dcache.writebacks::total 6037757 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3397304 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3397304 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6149640 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6149640 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4348 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4348 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 126499 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 126499 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9546944 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9546944 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9546944 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9546944 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3231575 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3231575 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1499011 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1499011 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 720499 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 720499 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 819629 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 819629 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122623 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122623 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189214 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 189214 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4730586 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4730586 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5451085 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5451085 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32157 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31964 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64121 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51760022500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51760022500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40775562681 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 40775562681 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18675421500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18675421500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 90765682079 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 90765682079 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1771728000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1771728000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5204285500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5204285500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4541000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4541000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92535585181 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 92535585181 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111211006681 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 111211006681 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6175664000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6175664000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6047364000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6047364000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12223028000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12223028000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037403 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037403 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019968 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019968 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765847 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765847 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.757443 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.757443 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061010 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061010 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095821 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095821 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029297 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029297 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033563 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033563 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16016.964638 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16016.964638 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27201.643404 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27201.643404 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25920.121333 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25920.121333 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 110739.959273 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 110739.959273 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14448.578162 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14448.578162 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27504.759162 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27504.759162 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19423.173458 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19423.173458 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20253.849762 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20253.849762 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191709.753946 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191709.753946 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189165.140535 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189165.140535 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190435.476769 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190435.476769 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19561.125235 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19561.125235 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20401.627691 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20401.627691 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192047.268091 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192047.268091 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189192.967088 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189192.967088 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190624.413219 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190624.413219 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6005225 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.936915 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 202641946 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6005737 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.741395 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 5991449 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.937020 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 207384617 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5991961 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.610475 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 21603135000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936915 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937020 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 424004104 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 424004104 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 202641946 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 202641946 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 202641946 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 202641946 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 202641946 # number of overall hits -system.cpu0.icache.overall_hits::total 202641946 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6357218 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6357218 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6357218 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6357218 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6357218 # number of overall misses -system.cpu0.icache.overall_misses::total 6357218 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 72002088632 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 72002088632 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 72002088632 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 72002088632 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 72002088632 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 72002088632 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 208999164 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 208999164 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 208999164 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 208999164 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 208999164 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 208999164 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030417 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.030417 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030417 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.030417 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030417 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.030417 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11326.037369 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11326.037369 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11326.037369 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11326.037369 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11326.037369 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11326.037369 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11168048 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1595 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 759109 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.712048 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 113.928571 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 433456796 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 433456796 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 207384617 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 207384617 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 207384617 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 207384617 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 207384617 # number of overall hits +system.cpu0.icache.overall_hits::total 207384617 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6347783 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6347783 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6347783 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6347783 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6347783 # number of overall misses +system.cpu0.icache.overall_misses::total 6347783 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 72771579605 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 72771579605 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 72771579605 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 72771579605 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 72771579605 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 72771579605 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 213732400 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 213732400 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 213732400 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 213732400 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 213732400 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 213732400 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029700 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029700 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029700 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029700 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029700 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029700 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11464.093780 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11464.093780 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11464.093780 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11464.093780 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11464.093780 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11464.093780 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 11432767 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1960 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 763504 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.974076 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 122.500000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 6005225 # number of writebacks -system.cpu0.icache.writebacks::total 6005225 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351442 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 351442 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 351442 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 351442 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 351442 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 351442 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6005776 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6005776 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6005776 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6005776 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6005776 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6005776 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 5991449 # number of writebacks +system.cpu0.icache.writebacks::total 5991449 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355787 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 355787 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 355787 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 355787 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 355787 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 355787 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5991996 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5991996 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5991996 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5991996 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5991996 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5991996 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64732998531 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 64732998531 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64732998531 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 64732998531 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64732998531 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 64732998531 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 65359568752 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 65359568752 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 65359568752 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 65359568752 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 65359568752 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 65359568752 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028736 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028736 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028736 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10778.457027 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10778.457027 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10778.457027 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028035 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028035 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10907.812481 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10907.812481 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10907.812481 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7993443 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8002831 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 8432 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8312308 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8321741 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 8453 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1016241 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2612055 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15872.009303 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 17309640 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2628171 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.586192 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1049931 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2736768 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15876.012159 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 17362528 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2752871 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.307062 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14904.546668 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.900343 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 63.931766 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 838.630526 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.909701 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003961 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003902 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051186 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.968751 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1148 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14896 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 168 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 583 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 378 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14917.842100 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.317341 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.112590 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 828.740128 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.910513 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004292 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003608 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.050582 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.968995 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1213 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14811 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 670 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 342 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1338 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5968 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4418 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3068 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.070068 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 407586755 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 407586755 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 586295 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 178487 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 764782 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3871957 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3871957 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8013001 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8013001 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 532 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 532 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 876856 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 876856 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5449817 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5449817 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2990512 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2990512 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 195363 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 195363 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 586295 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 178487 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5449817 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3867368 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10081967 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 586295 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 178487 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5449817 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3867368 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10081967 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11719 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8497 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 20216 # number of ReadReq misses -system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses -system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 253056 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 253056 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 193456 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 193456 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1270 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5895 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4592 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2939 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.074036 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903992 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 412851946 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 412851946 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 601484 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 195644 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 797128 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 3986432 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 3986432 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 8040621 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 8040621 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 576 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 576 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 912887 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 912887 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5408697 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5408697 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3048347 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 3048347 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 196930 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 196930 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 601484 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 195644 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5408697 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3961234 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 10167059 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 601484 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 195644 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5408697 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3961234 # number of overall hits +system.cpu0.l2cache.overall_hits::total 10167059 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12249 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9259 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 21508 # number of ReadReq misses +system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses +system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses +system.cpu0.l2cache.WritebackClean_misses::writebacks 3 # number of WritebackClean misses +system.cpu0.l2cache.WritebackClean_misses::total 3 # number of WritebackClean misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 258491 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 258491 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 189208 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 189208 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 324941 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 324941 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 555934 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 555934 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 984475 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 984475 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 615167 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 615167 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11719 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8497 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 555934 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1309416 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1885566 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11719 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8497 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 555934 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1309416 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1885566 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 564728500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 467676000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1032404500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3400771000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3400771000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2092190000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2092190000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 8283499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 8283499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 22038897500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 22038897500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22689432998 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22689432998 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43523481971 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43523481971 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 86915383999 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 86915383999 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 564728500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 467676000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22689432998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 65562379471 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 89284216969 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 564728500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 467676000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22689432998 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 65562379471 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 89284216969 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 598014 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 186984 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 784998 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3871959 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3871959 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 8013003 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 8013003 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 253588 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 253588 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 193457 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 193457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 336496 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 336496 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 583279 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 583279 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1024126 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1024126 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 620872 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 620872 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12249 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9259 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 583279 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1360622 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1965409 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12249 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9259 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 583279 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1360622 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1965409 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 599464000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 508507000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1107971000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3541175500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 3541175500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2016705000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2016705000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4451000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4451000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 22474975499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 22474975499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23599019498 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 23599019498 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 45762236974 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 45762236974 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 87223622986 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 87223622986 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 599464000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 508507000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23599019498 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 68237212473 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 92944202971 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 599464000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 508507000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23599019498 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 68237212473 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 92944202971 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 613733 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 204903 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 818636 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3986433 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 3986433 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 8040624 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 8040624 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 259067 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 259067 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189210 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 189210 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1201797 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1201797 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6005751 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 6005751 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3974987 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 3974987 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 810530 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 810530 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 598014 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 186984 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6005751 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5176784 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11967533 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 598014 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 186984 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 6005751 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5176784 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11967533 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019597 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045442 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1249383 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1249383 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5991976 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5991976 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4072473 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4072473 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 817802 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 817802 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 613733 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 204903 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5991976 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5321856 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 12132468 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 613733 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 204903 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5991976 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5321856 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 12132468 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045187 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.026273 # miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997902 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997902 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997777 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997777 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999989 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999989 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.270379 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.270379 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092567 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092567 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.247667 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.247667 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.758969 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.758969 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019597 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045442 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092567 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252940 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.157557 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019597 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045442 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092567 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.252940 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.157557 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48189.137298 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 55040.131811 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 51068.683221 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13438.808011 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13438.808011 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10814.810603 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10814.810603 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 2070874.750000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2070874.750000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67824.305028 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67824.305028 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40813.177460 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40813.177460 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44209.839733 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44209.839733 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 141287.461777 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 141287.461777 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48189.137298 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 55040.131811 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40813.177460 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50069.939172 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 47351.414360 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48189.137298 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 55040.131811 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40813.177460 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50069.939172 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 47351.414360 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 3549 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.269330 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.269330 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.097343 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.097343 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.251475 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.251475 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.759196 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.759196 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045187 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.097343 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.255667 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.161996 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045187 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.097343 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.255667 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.161996 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54920.293768 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 51514.366747 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13699.415067 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13699.415067 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10658.666653 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10658.666653 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1112750 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1112750 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66791.211482 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66791.211482 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40459.230485 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40459.230485 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44684.186295 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44684.186295 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 140485.676574 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 140485.676574 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54920.293768 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40459.230485 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50151.484007 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 47290.005780 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54920.293768 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40459.230485 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50151.484007 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 47290.005780 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 2951 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 236.600000 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 95.193548 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1633377 # number of writebacks -system.cpu0.l2cache.writebacks::total 1633377 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 5 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 190 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 59160 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 59160 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 6628 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 6628 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 15 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::total 15 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 5 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 190 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 65788 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 65985 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 5 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 190 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 65788 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 65985 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11714 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8307 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 20021 # number of ReadReq MSHR misses -system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses -system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses -system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses -system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 825638 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 825638 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 253056 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 253056 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 193456 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 193456 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 1713705 # number of writebacks +system.cpu0.l2cache.writebacks::total 1713705 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 178 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 63480 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 63480 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 6383 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 6383 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 5 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 178 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 69863 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 70046 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 178 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 69863 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 70046 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12245 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9081 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 21326 # number of ReadReq MSHR misses +system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses +system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses +system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 3 # number of WritebackClean MSHR misses +system.cpu0.l2cache.WritebackClean_mshr_misses::total 3 # number of WritebackClean MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 867285 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 867285 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 258491 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 258491 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 189208 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 189208 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 265781 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 265781 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 555932 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 555932 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 977847 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 977847 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 615152 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 615152 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11714 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8307 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 555932 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1243628 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1819581 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11714 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8307 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 555932 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1243628 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 825638 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2645219 # number of overall MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 273016 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 273016 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 583278 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 583278 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1017743 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1017743 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 620867 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 620867 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12245 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9081 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 583278 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1290759 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1895363 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12245 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9081 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 583278 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1290759 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 867285 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2762648 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54172 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32981 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53450 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31964 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87153 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 408146000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 902242500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 60235996440 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 60235996440 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7625664494 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7625664494 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3888505997 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3888505997 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 7593499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 7593499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16722004500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16722004500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19353809498 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19353809498 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 37185118471 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 37185118471 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 83223435999 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 83223435999 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 408146000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19353809498 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 53907122971 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 74163174969 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 408146000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19353809498 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 53907122971 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 60235996440 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 134399171409 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 85414 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 445082000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 970995500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 62672299402 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 62672299402 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7863725997 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7863725997 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3782122004 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3782122004 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4091000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4091000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17017630999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17017630999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20099332998 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20099332998 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39175352474 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39175352474 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 83498176486 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 83498176486 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 445082000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20099332998 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 56192983473 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 77263311971 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 445082000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20099332998 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 56192983473 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 62672299402 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 139935611373 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6040017000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8820099500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5985704467 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5985704467 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5918259500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8698342000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5801825967 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5801825967 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12025721467 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14805803967 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.025505 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11720085467 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14500167967 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026051 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997902 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997902 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997777 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997777 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999989 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999989 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221153 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221153 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092567 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.246000 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.246000 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.758950 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.758950 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240232 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.152043 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240232 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.218521 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.218521 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097343 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249908 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249908 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.759190 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.759190 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242539 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156222 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242539 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.221033 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45064.806953 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72956.909009 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30134.296338 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30134.296338 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20100.208818 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20100.208818 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1898374.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1898374.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62916.478228 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62916.478228 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34813.267626 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38027.542623 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38027.542623 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 135289.222825 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 135289.222825 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43346.662323 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40758.380621 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43346.662323 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50808.334361 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227707 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45531.065366 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72262.635007 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30421.662638 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30421.662638 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19989.228806 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19989.228806 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1022750 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1022750 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62331.991528 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62331.991528 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34459.268133 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38492.382138 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38492.382138 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 134486.414137 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 134486.414137 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43534.837621 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40764.387598 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43534.837621 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50652.711230 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183704.400985 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162816.574983 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181489.477790 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181489.477790 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184042.650123 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162737.923293 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181511.261638 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181511.261638 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182595.224218 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169882.895219 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182780.765537 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169763.363933 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 24664078 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12671171 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2001831 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2001348 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 483 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 921539 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11008242 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32981 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5510686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8013020 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2592060 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1056695 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 478539 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354281 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 520874 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1281558 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1212477 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6005776 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4986753 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 818816 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 810530 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18057865 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19072336 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391759 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1260604 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 38782564 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 768948880 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 715383853 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1495872 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4784112 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1490612717 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7046224 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20167865 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.116092 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.320411 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 24968942 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12837433 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2144 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2067889 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2067431 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 458 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 957998 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11124580 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31965 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31964 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5704814 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8040643 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2700571 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1106688 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 8 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 482477 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344108 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 518232 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1334424 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1260303 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5991996 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5072927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 824948 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 817802 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18016682 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19524167 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428300 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294882 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 39264031 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 767195088 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 734396467 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4909864 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1508140643 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7265658 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 20566582 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.118168 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.322876 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 17827011 88.39% 88.39% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2340371 11.60% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 483 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 18136730 88.19% 88.19% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2429394 11.81% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 458 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20167865 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 24544733928 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 20566582 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 24844807916 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 212322671 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 204855996 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9035902540 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9015512485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8451585698 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8672428624 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 205222100 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 223891503 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 663162345 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 681731807 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 136771271 # Number of BP lookups -system.cpu1.branchPred.condPredicted 91615454 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6699408 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 96252672 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 62838118 # Number of BTB hits +system.cpu1.branchPred.lookups 134041815 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89707660 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6609017 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 94187638 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 61197396 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.284544 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 18248077 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 178326 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 64.973915 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17950728 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 175820 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1729,87 +1718,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 587464 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 587464 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12287 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93954 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 273243 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 314221 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2460.273184 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 14941.067276 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 311748 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1254 0.40% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 917 0.29% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 161 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 52 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 63 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 567287 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 567287 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11327 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89325 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 259417 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 307870 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2446.318251 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 14947.483095 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 305492 99.23% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1236 0.40% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 840 0.27% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 161 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 314221 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 302969 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20764.791117 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17394.458301 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 22544.227052 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 299168 98.75% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 939 0.31% 99.06% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1914 0.63% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 156 0.05% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 510 0.17% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 121 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 110 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 28 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 302969 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 477883045620 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.598615 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.553378 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 476579478620 99.73% 99.73% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 689019500 0.14% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 279828500 0.06% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 139297000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 94668000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 55014500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 17997000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 27375000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 352000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 15500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 477883045620 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 93955 88.43% 88.43% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 12287 11.57% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 106242 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 587464 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 307870 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 284687 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20644.869629 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17424.592515 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 21452.651975 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 281397 98.84% 98.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 951 0.33% 99.18% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1579 0.55% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 108 0.04% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 394 0.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 106 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 102 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 31 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 284687 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 488633591384 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.617867 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.545160 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 487382306384 99.74% 99.74% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 662548500 0.14% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 271218500 0.06% 99.94% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 131442000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 92501000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 52739500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 15718500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 24644000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 457500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 488633591384 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 89326 88.75% 88.75% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11327 11.25% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 100653 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 567287 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 587464 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106242 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 567287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100653 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106242 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 693706 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100653 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 667940 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 101377575 # DTB read hits -system.cpu1.dtb.read_misses 401827 # DTB read misses -system.cpu1.dtb.write_hits 83690670 # DTB write hits -system.cpu1.dtb.write_misses 185637 # DTB write misses +system.cpu1.dtb.read_hits 99577859 # DTB read hits +system.cpu1.dtb.read_misses 392921 # DTB read misses +system.cpu1.dtb.write_hits 81911984 # DTB write hits +system.cpu1.dtb.write_misses 174366 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39959 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 225 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6406 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 37295 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 442 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6095 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 43965 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 101779402 # DTB read accesses -system.cpu1.dtb.write_accesses 83876307 # DTB write accesses +system.cpu1.dtb.perms_faults 38665 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 99970780 # DTB read accesses +system.cpu1.dtb.write_accesses 82086350 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 185068245 # DTB hits -system.cpu1.dtb.misses 587464 # DTB misses -system.cpu1.dtb.accesses 185655709 # DTB accesses +system.cpu1.dtb.hits 181489843 # DTB hits +system.cpu1.dtb.misses 567287 # DTB misses +system.cpu1.dtb.accesses 182057130 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1839,1165 +1831,1167 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 92227 # Table walker walks requested -system.cpu1.itb.walker.walksLong 92227 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 973 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66704 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 11080 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 81147 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1613.670253 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 12323.334174 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 80305 98.96% 98.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 403 0.50% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 31 0.04% 99.50% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 81 0.10% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 234 0.29% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 81147 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 78757 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26873.185876 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22946.544582 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 27397.779974 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 76775 97.48% 97.48% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 153 0.19% 97.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1519 1.93% 99.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 117 0.15% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 110 0.14% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 35 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 36 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 85422 # Table walker walks requested +system.cpu1.itb.walker.walksLong 85422 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 706 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60440 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 10533 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 74889 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1637.737184 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 12543.180008 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 74488 99.46% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 92 0.12% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 279 0.37% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 13 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 74889 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71679 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26447.767128 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22834.132885 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 26054.956905 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 70042 97.72% 97.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 124 0.17% 97.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1290 1.80% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 62 0.09% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 94 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 27 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 78757 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 434901307160 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.857521 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.349757 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 61992873300 14.25% 14.25% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 372883353360 85.74% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 22166000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 2474500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 253500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 186500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 434901307160 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 66704 98.56% 98.56% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 973 1.44% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 67677 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71679 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 419883309648 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.857166 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.350104 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 59999474576 14.29% 14.29% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 359861735072 85.71% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 18604000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 3422000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 61500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 419883309648 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 60440 98.85% 98.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 706 1.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 61146 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 92227 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 92227 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85422 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85422 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 67677 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 67677 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 159904 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 215454990 # ITB inst hits -system.cpu1.itb.inst_misses 92227 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61146 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61146 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 146568 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 210903230 # ITB inst hits +system.cpu1.itb.inst_misses 85422 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 28858 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 26936 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 231246 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 219212 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 215547217 # ITB inst accesses -system.cpu1.itb.hits 215454990 # DTB hits -system.cpu1.itb.misses 92227 # DTB misses -system.cpu1.itb.accesses 215547217 # DTB accesses -system.cpu1.numCycles 759155378 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 210988652 # ITB inst accesses +system.cpu1.itb.hits 210903230 # DTB hits +system.cpu1.itb.misses 85422 # DTB misses +system.cpu1.itb.accesses 210988652 # DTB accesses +system.cpu1.numCycles 739589068 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 87128814 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 606063748 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 136771271 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 81086195 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 630037393 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14425462 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2172177 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 325931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6736887 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 827556 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 851702 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 215200214 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1679756 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 31517 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 735293191 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.969104 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.218230 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 87179307 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 594353675 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 134041815 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 79148124 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 611930141 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14224484 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1980961 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 327085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6413771 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 794469 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 836341 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 210662459 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1674863 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 29397 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 716574317 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.975535 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.220237 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 394185812 53.61% 53.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 132782093 18.06% 71.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 45182528 6.14% 77.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 163142758 22.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 382171132 53.33% 53.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 130053591 18.15% 71.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 44058900 6.15% 77.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 160290694 22.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 735293191 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.180162 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.798340 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 105275670 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 361149345 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 225652352 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 38094367 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5121457 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19322389 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2132865 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 630175710 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 23074598 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5121457 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 140790232 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 54705867 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 237824642 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 227778492 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 69072501 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 613335461 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5878562 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 11068691 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 265258 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 344448 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 33464644 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 12708 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 582683755 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 946463821 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 725287459 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 802163 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 525337621 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 57346134 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 16349116 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 14383675 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76724538 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 101292205 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 87094038 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 9603338 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 8276902 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 590341476 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 16600780 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 596033149 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2703684 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 54441407 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 34942140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 296921 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 735293191 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.810606 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.063717 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 716574317 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.181238 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.803627 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 104297157 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 348522347 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 221906314 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 36809016 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5039483 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18926425 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2113724 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 618028101 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22771231 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5039483 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 138949493 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 52143991 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 230343934 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 223632177 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 66465239 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 601445820 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5788119 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 10817316 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 260401 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 332552 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 31997393 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11898 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 571172784 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 925552885 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 711516112 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 817303 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 514566329 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 56606455 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15686724 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13790746 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 74346046 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 99668213 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 85253354 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 9496006 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 8106709 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 579162522 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15985308 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 584188542 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2667167 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 53686437 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 34500302 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 290258 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 716574317 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.815252 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.066417 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 408888874 55.61% 55.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 138685440 18.86% 74.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 113812160 15.48% 89.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 65908523 8.96% 98.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7993150 1.09% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 5044 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 397414827 55.46% 55.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 134713914 18.80% 74.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 111740906 15.59% 89.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 64830862 9.05% 98.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7868810 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4998 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 735293191 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 716574317 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 59894815 43.89% 43.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 54223 0.04% 43.93% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 19415 0.01% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 13 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.94% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 36698954 26.89% 70.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 39811710 29.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 59065524 44.03% 44.03% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 54166 0.04% 44.07% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 19277 0.01% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 36039894 26.87% 70.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 38965641 29.05% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 40 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 405160238 67.98% 67.98% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1323587 0.22% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 73165 0.01% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 6 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 83635 0.01% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 104404803 17.52% 85.74% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 84987627 14.26% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 396970173 67.95% 67.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1317793 0.23% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 74565 0.01% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 1 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 84907 0.01% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 102569706 17.56% 85.76% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 83171310 14.24% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 596033149 # Type of FU issued -system.cpu1.iq.rate 0.785127 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 136479130 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.228979 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2065187396 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 660997777 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 578833453 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1354907 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 550149 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 503649 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 731674033 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 838206 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2717332 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 584188542 # Type of FU issued +system.cpu1.iq.rate 0.789883 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 134144524 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.229625 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 2020390722 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 648436438 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 567390385 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1372370 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 557189 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 510457 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 717484509 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 848517 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2681981 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12501770 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 165759 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5982611 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12380566 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16529 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 160745 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5876169 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2801463 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4362378 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2772484 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4108210 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5121457 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6701200 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2456436 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 607072203 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 5039483 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6511130 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2319208 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 595271017 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 101292205 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 87094038 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 14166456 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 66987 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2327340 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 165759 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2053658 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2840126 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4893784 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 588333719 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 101371104 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7124424 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 99668213 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 85253354 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13572161 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64444 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2193101 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 160745 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2023154 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2795718 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4818872 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 576621181 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 99570735 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 7012433 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 129947 # number of nop insts executed -system.cpu1.iew.exec_refs 185062017 # number of memory reference insts executed -system.cpu1.iew.exec_branches 110209905 # Number of branches executed -system.cpu1.iew.exec_stores 83690913 # Number of stores executed -system.cpu1.iew.exec_rate 0.774985 # Inst execution rate -system.cpu1.iew.wb_sent 580075402 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 579337102 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 280158358 # num instructions producing a value -system.cpu1.iew.wb_consumers 458852190 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.763134 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610563 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 47675638 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 16303859 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4608134 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 726275789 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.760731 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.562013 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 123187 # number of nop insts executed +system.cpu1.iew.exec_refs 181482515 # number of memory reference insts executed +system.cpu1.iew.exec_branches 107903719 # Number of branches executed +system.cpu1.iew.exec_stores 81911780 # Number of stores executed +system.cpu1.iew.exec_rate 0.779651 # Inst execution rate +system.cpu1.iew.wb_sent 568628901 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 567900842 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 274880956 # num instructions producing a value +system.cpu1.iew.wb_consumers 450165977 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.767860 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610621 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 47031076 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15695050 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4536258 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 707685383 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.765116 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.566861 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 483439526 66.56% 66.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 126884990 17.47% 84.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 53284484 7.34% 91.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17968651 2.47% 93.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12727519 1.75% 95.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8624800 1.19% 96.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6048440 0.83% 97.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3562811 0.49% 98.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 13734568 1.89% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 470367960 66.47% 66.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 123401303 17.44% 83.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 52359305 7.40% 91.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 17652538 2.49% 93.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12497517 1.77% 95.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8502383 1.20% 96.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5935480 0.84% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3482174 0.49% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 13486723 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 726275789 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 468737677 # Number of instructions committed -system.cpu1.commit.committedOps 552500848 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 707685383 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 459224264 # Number of instructions committed +system.cpu1.commit.committedOps 541461392 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 169901862 # Number of memory references committed -system.cpu1.commit.loads 88790435 # Number of loads committed -system.cpu1.commit.membars 3923548 # Number of memory barriers committed -system.cpu1.commit.branches 104577420 # Number of branches committed -system.cpu1.commit.fp_insts 490317 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 507351840 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13608772 # Number of function calls committed. +system.cpu1.commit.refs 166664832 # Number of memory references committed +system.cpu1.commit.loads 87287647 # Number of loads committed +system.cpu1.commit.membars 3905531 # Number of memory barriers committed +system.cpu1.commit.branches 102374979 # Number of branches committed +system.cpu1.commit.fp_insts 497703 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 497469676 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13371734 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 381394130 69.03% 69.03% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1072293 0.19% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 58068 0.01% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 74453 0.01% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 88790435 16.07% 85.32% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 81111427 14.68% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 373594883 69.00% 69.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1066183 0.20% 69.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 59540 0.01% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 75912 0.01% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 87287647 16.12% 85.34% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 79377185 14.66% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 552500848 # Class of committed instruction -system.cpu1.commit.bw_lim_events 13734568 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1308834452 # The number of ROB reads -system.cpu1.rob.rob_writes 1209328543 # The number of ROB writes -system.cpu1.timesIdled 978867 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 23862187 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 93869849108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 468737677 # Number of Instructions Simulated -system.cpu1.committedOps 552500848 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.619574 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.619574 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.617446 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.617446 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 695521161 # number of integer regfile reads -system.cpu1.int_regfile_writes 411377637 # number of integer regfile writes -system.cpu1.fp_regfile_reads 787723 # number of floating regfile reads -system.cpu1.fp_regfile_writes 479172 # number of floating regfile writes -system.cpu1.cc_regfile_reads 125942514 # number of cc regfile reads -system.cpu1.cc_regfile_writes 126793051 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1299771916 # number of misc regfile reads -system.cpu1.misc_regfile_writes 16418490 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5616176 # number of replacements -system.cpu1.dcache.tags.tagsinuse 458.902978 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 158371031 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5616685 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.196531 # Average number of references to valid blocks. +system.cpu1.commit.op_class_0::total 541461392 # Class of committed instruction +system.cpu1.commit.bw_lim_events 13486723 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1278856692 # The number of ROB reads +system.cpu1.rob.rob_writes 1185834230 # The number of ROB writes +system.cpu1.timesIdled 958439 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 23014751 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94048355585 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 459224264 # Number of Instructions Simulated +system.cpu1.committedOps 541461392 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.610518 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.610518 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.620918 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.620918 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 681935687 # number of integer regfile reads +system.cpu1.int_regfile_writes 403917801 # number of integer regfile writes +system.cpu1.fp_regfile_reads 803668 # number of floating regfile reads +system.cpu1.fp_regfile_writes 473340 # number of floating regfile writes +system.cpu1.cc_regfile_reads 122826591 # number of cc regfile reads +system.cpu1.cc_regfile_writes 123738784 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1267794356 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15807378 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5498905 # number of replacements +system.cpu1.dcache.tags.tagsinuse 458.394450 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 155608106 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5499414 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.295398 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8486277940000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.902978 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.896295 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.896295 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.394450 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895302 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.895302 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 416 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 352316395 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 352316395 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 82533449 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 82533449 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 71018677 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 71018677 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 182219 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 182219 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 55748 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 55748 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1865594 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1865594 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1903770 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1903770 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 153552126 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 153552126 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 153734345 # number of overall hits -system.cpu1.dcache.overall_hits::total 153734345 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6611698 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6611698 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7495595 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7495595 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 706613 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 706613 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 438931 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 438931 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288457 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 288457 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 203515 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 203515 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 14107293 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 14107293 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14813906 # number of overall misses -system.cpu1.dcache.overall_misses::total 14813906 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 112950117500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 112950117500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 162063724604 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 162063724604 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18729695563 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 18729695563 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4597585500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4597585500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5657651000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5657651000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7414500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7414500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 275013842104 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 275013842104 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 275013842104 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 275013842104 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 89145147 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 89145147 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 78514272 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 78514272 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 888832 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 888832 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 494679 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 494679 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2154051 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2154051 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2107285 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2107285 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 167659419 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 167659419 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 168548251 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 168548251 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074168 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.074168 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095468 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.095468 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794991 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794991 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.887305 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.887305 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.133914 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.133914 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096577 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096577 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084143 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.084143 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087891 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.087891 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17083.375178 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 17083.375178 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21621.195463 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21621.195463 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42671.161442 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42671.161442 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15938.547166 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15938.547166 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27799.675700 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27799.675700 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 345701865 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 345701865 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 81166944 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 81166944 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 69652711 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 69652711 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 179570 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 179570 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 55554 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 55554 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1867218 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1867218 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1906025 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1906025 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 150819655 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 150819655 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 150999225 # number of overall hits +system.cpu1.dcache.overall_hits::total 150999225 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6513815 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6513815 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7138740 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7138740 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 666746 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 666746 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433208 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 433208 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 280157 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 280157 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195063 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 195063 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13652555 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13652555 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14319301 # number of overall misses +system.cpu1.dcache.overall_misses::total 14319301 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 107790302500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 107790302500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 154935306923 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 154935306923 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17952138757 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 17952138757 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4403404000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 4403404000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5419622500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5419622500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3200000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3200000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 262725609423 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 262725609423 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 262725609423 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 262725609423 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87680759 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87680759 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 76791451 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 76791451 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 846316 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 846316 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 488762 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 488762 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2147375 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2147375 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2101088 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2101088 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 164472210 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 164472210 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 165318526 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 165318526 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074290 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074290 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092963 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.092963 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787822 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787822 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.886337 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.886337 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130465 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130465 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092839 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092839 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083008 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.083008 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086616 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.086616 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16547.952697 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16547.952697 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21703.452839 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21703.452839 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41439.998239 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41439.998239 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15717.629758 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15717.629758 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27783.959541 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27783.959541 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19494.444618 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19494.444618 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18564.573186 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18564.573186 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4974164 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 25867147 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 359446 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 756404 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.838418 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 34.197528 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19243.695369 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19243.695369 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18347.656036 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18347.656036 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4719493 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 24576154 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 351674 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 713575 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.420079 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 34.440884 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5616192 # number of writebacks -system.cpu1.dcache.writebacks::total 5616192 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3382349 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3382349 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6057293 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 6057293 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3337 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3337 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 147189 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 147189 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9439642 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9439642 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9439642 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9439642 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3229349 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3229349 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1438302 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1438302 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706535 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 706535 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 435594 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 435594 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141268 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141268 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 203504 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 203504 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4667651 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4667651 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5374186 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5374186 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5460 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5460 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5292 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10752 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10752 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 50929568500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 50929568500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34490212579 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34490212579 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16980659000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16980659000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 18123603563 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 18123603563 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 2072685000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 2072685000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5454243000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5454243000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 7318500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 7318500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85419781079 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 85419781079 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102400440079 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 102400440079 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 594704500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 594704500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 661334500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 661334500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1256039000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1256039000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036226 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036226 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018319 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018319 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794903 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794903 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.880559 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.880559 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065582 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065582 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096572 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096572 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027840 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027840 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031885 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031885 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15770.846849 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15770.846849 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23979.812709 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23979.812709 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24033.712413 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24033.712413 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41606.641880 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41606.641880 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14672.006399 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14672.006399 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26801.650090 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26801.650090 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5498938 # number of writebacks +system.cpu1.dcache.writebacks::total 5498938 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3304670 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3304670 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5753104 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5753104 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3561 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3561 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 144550 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 144550 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9057774 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9057774 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9057774 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9057774 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3209145 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3209145 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1385636 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1385636 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 666638 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 666638 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 429647 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 429647 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135607 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135607 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195058 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 195058 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4594781 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4594781 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5261419 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5261419 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6299 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6299 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6428 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12727 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12727 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 49159510500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 49159510500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 33253300624 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 33253300624 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15899737000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15899737000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17350623757 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17350623757 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1958308000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1958308000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5224605500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5224605500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3159000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3159000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82412811124 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 82412811124 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 98312548124 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 98312548124 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 727883500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 727883500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859834500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859834500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1587718000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1587718000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018044 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018044 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787694 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787694 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879052 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879052 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063150 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063150 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092837 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092837 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027937 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027937 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031826 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031826 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15318.569432 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15318.569432 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23998.583051 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23998.583051 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23850.631077 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23850.631077 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40383.439794 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40383.439794 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14441.053928 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14441.053928 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26784.881933 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26784.881933 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18300.378730 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18300.378730 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19054.130259 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19054.130259 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108920.238095 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 108920.238095 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124968.726379 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124968.726379 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116819.103423 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116819.103423 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17936.178269 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17936.178269 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18685.557665 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18685.557665 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 115555.405620 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 115555.405620 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133763.923460 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 133763.923460 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124751.944685 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124751.944685 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5955939 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.596349 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 208888584 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5956451 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 35.069303 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 5972259 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.613786 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 204337040 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5972771 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.211431 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8525956583000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.596349 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979680 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979680 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.613786 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979714 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979714 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 436342012 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 436342012 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 208888584 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 208888584 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 208888584 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 208888584 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 208888584 # number of overall hits -system.cpu1.icache.overall_hits::total 208888584 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6304191 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6304191 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6304191 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6304191 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6304191 # number of overall misses -system.cpu1.icache.overall_misses::total 6304191 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 70452471315 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 70452471315 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 70452471315 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 70452471315 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 70452471315 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 70452471315 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 215192775 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 215192775 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 215192775 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 215192775 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 215192775 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 215192775 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029296 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029296 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029296 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029296 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029296 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029296 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11175.497588 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 11175.497588 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11175.497588 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 11175.497588 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11175.497588 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 11175.497588 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 10802796 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 573 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 747541 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.451108 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 114.600000 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 427283163 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 427283163 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 204337040 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 204337040 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 204337040 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 204337040 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 204337040 # number of overall hits +system.cpu1.icache.overall_hits::total 204337040 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6318152 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6318152 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6318152 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6318152 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6318152 # number of overall misses +system.cpu1.icache.overall_misses::total 6318152 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 69955140831 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 69955140831 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 69955140831 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 69955140831 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 69955140831 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 69955140831 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 210655192 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 210655192 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 210655192 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 210655192 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 210655192 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 210655192 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029993 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029993 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029993 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029993 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029993 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029993 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11072.088932 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 11072.088932 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11072.088932 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 11072.088932 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11072.088932 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 11072.088932 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 10670268 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1157 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 748022 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.264645 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 144.625000 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 5955939 # number of writebacks -system.cpu1.icache.writebacks::total 5955939 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 347729 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 347729 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 347729 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 347729 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 347729 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 347729 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5956462 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5956462 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5956462 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5956462 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5956462 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5956462 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5972259 # number of writebacks +system.cpu1.icache.writebacks::total 5972259 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 345373 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 345373 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 345373 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 345373 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 345373 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 345373 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5972779 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5972779 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5972779 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5972779 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5972779 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5972779 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63484136905 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 63484136905 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63484136905 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 63484136905 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63484136905 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 63484136905 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63045966777 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 63045966777 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63045966777 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 63045966777 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63045966777 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 63045966777 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8835998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8835998 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8835998 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 8835998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027680 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027680 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027680 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10658.027686 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10658.027686 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10658.027686 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028353 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028353 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028353 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10555.549900 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10555.549900 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10555.549900 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 131880.567164 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 131880.567164 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7807580 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7812689 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 4721 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7501600 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7506319 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 4330 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 919623 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2337918 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13374.571842 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17269379 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2353639 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.337310 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10121843878000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12566.070038 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 56.667232 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.366082 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000003 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 686.468486 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.766972 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003459 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003990 # Average percentage of cache occupancy +system.cpu1.l2cache.prefetcher.pfSpanPage 900873 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2224556 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13365.286062 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 17240330 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2240308 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 7.695518 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10278781174500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 12562.638726 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.088648 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 68.405438 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000005 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 667.153246 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.766763 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004095 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004175 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041899 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.816319 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14434 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 80 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 187 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 549 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 387 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 65 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 840 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4705 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3842 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.880981 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 397810098 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 397810098 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 597256 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 208532 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 805788 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3539726 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3539726 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 8031138 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 8031138 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 945 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 945 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 889943 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 889943 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5374664 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5374664 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3032294 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3032294 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 189660 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 189660 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 597256 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 208532 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5374664 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3922237 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 10102689 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 597256 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 208532 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5374664 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3922237 # number of overall hits -system.cpu1.l2cache.overall_hits::total 10102689 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12883 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10252 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 23135 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 246019 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 246019 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 203494 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 203494 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 311077 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 311077 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 581787 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 581787 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1040673 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1040673 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 244105 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 244105 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12883 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10252 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 581787 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1351750 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1956672 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12883 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10252 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 581787 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1351750 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1956672 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 705237000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 609311000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1314548000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3694717000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 3694717000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1939092500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1939092500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 7171998 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 7171998 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 16701418499 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 16701418499 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22000590000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22000590000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 43617133977 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 43617133977 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 15757180999 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 15757180999 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 705237000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 609311000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22000590000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 60318552476 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 83633690476 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 705237000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 609311000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22000590000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 60318552476 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 83633690476 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 610139 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 218784 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 828923 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3539731 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3539731 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 8031138 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 8031138 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 246964 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 246964 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 203498 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 203498 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1201020 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1201020 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5956451 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5956451 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4072967 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 4072967 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433765 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 433765 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 610139 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 218784 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5956451 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5273987 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 12059361 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 610139 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 218784 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5956451 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5273987 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 12059361 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046859 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.027910 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040720 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.815752 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1289 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14365 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 78 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 616 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 417 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 949 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4690 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3797 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078674 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.876770 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 393723429 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 393723429 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 587134 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 192926 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 780060 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3457963 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3457963 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 8011825 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 8011825 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 813 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 813 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 855353 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 855353 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5413940 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 5413940 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3003863 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3003863 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191485 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 191485 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 587134 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 192926 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5413940 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3859216 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 10053216 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 587134 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 192926 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5413940 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3859216 # number of overall hits +system.cpu1.l2cache.overall_hits::total 10053216 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12541 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9429 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 21970 # number of ReadReq misses +system.cpu1.l2cache.WritebackDirty_misses::writebacks 4 # number of WritebackDirty misses +system.cpu1.l2cache.WritebackDirty_misses::total 4 # number of WritebackDirty misses +system.cpu1.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses +system.cpu1.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 239265 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 239265 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195055 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 195055 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 299638 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 299638 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 558835 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 558835 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1003530 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1003530 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 236473 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 236473 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12541 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9429 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 558835 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1303168 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1883973 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12541 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9429 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 558835 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1303168 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1883973 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 648758500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 531765000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1180523500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3573774499 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 3573774499 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1875778500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1875778500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3096999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3096999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 16089567500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 16089567500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 21287303500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 21287303500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 40947637491 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 40947637491 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 14994721499 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 14994721499 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 648758500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 531765000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21287303500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 57037204991 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 79505031991 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 648758500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 531765000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 21287303500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 57037204991 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 79505031991 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 599675 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 202355 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 802030 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3457967 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 3457967 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 8011827 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 8011827 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 240078 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 240078 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195057 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 195057 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1154991 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1154991 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5972775 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5972775 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4007393 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4007393 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 427958 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 427958 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 599675 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 202355 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5972775 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5162384 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 11937189 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 599675 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 202355 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5972775 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5162384 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 11937189 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046596 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.027393 # miss rate for ReadReq accesses system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996174 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996174 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999980 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999980 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses +system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996614 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996614 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999990 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999990 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.259011 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.259011 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097673 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097673 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255507 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255507 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.562759 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.562759 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046859 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097673 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256305 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.162253 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046859 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097673 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256305 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.162253 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 59433.378853 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 56820.747785 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15018.014869 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15018.014869 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9528.991027 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9528.991027 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1195333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1195333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53689.017507 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53689.017507 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37815.540739 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37815.540739 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 41912.429723 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 41912.429723 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 64550.832629 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 64550.832629 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 59433.378853 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37815.540739 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44622.565176 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 42742.825816 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 59433.378853 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37815.540739 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44622.565176 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 42742.825816 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 758 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.259429 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.259429 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.093564 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.093564 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.250420 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.250420 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.552561 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.552561 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046596 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.093564 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.252435 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.157824 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046596 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.093564 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.252435 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.157824 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 56396.754693 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 53733.431953 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14936.470019 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14936.470019 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9616.664531 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9616.664531 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3096999 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3096999 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53696.685667 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53696.685667 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38092.287527 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38092.287527 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40803.600780 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40803.600780 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 63409.867084 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 63409.867084 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 56396.754693 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38092.287527 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43768.113544 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 42200.727925 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 56396.754693 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38092.287527 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43768.113544 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 42200.727925 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 1276 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 126.333333 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 159.500000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1264789 # number of writebacks -system.cpu1.l2cache.writebacks::total 1264789 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 4 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 169 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 44408 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 44408 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 5726 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 5726 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 6 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 4 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 169 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 50134 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 50307 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 4 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 169 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 50134 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 50307 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12879 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10083 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 22962 # number of ReadReq MSHR misses -system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 5 # number of WritebackDirty MSHR misses -system.cpu1.l2cache.WritebackDirty_mshr_misses::total 5 # number of WritebackDirty MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 820594 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 820594 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 246019 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 246019 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 203494 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 203494 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 266669 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 266669 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 581787 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 581787 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1034947 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1034947 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 244099 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 244099 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12879 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10083 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 581787 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1301616 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1906365 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12879 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10083 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 581787 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1301616 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 820594 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2726959 # number of overall MSHR misses +system.cpu1.l2cache.writebacks::writebacks 1185134 # number of writebacks +system.cpu1.l2cache.writebacks::total 1185134 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 196 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 42850 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 42850 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 5641 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 5641 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 196 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 48491 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 48690 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 196 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 48491 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 48690 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12538 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9233 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 21771 # number of ReadReq MSHR misses +system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 4 # number of WritebackDirty MSHR misses +system.cpu1.l2cache.WritebackDirty_mshr_misses::total 4 # number of WritebackDirty MSHR misses +system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses +system.cpu1.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 776550 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 776550 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 239265 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 239265 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195055 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195055 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 256788 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 256788 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 558835 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 558835 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 997889 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 997889 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 236470 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 236470 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12538 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9233 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 558835 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1254677 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1835283 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12538 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9233 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 558835 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1254677 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 776550 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2611833 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5460 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5527 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5292 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6299 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6366 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6428 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10752 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10819 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 537691500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1165579500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 49091164625 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 49091164625 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7718588995 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7718588995 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3925065997 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3925065997 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6595998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6595998 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12865032499 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12865032499 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18509868000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18509868000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 37054911477 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 37054911477 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 14292006999 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 14292006999 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 537691500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18509868000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 49919943976 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 69595391476 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 537691500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18509868000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 49919943976 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 49091164625 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 118686556101 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 12727 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 12794 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 464925500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1038396500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46806898722 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46806898722 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7460497999 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7460497999 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3758753499 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3758753499 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2850999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2850999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12334341500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12334341500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17934293500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17934293500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 34643944491 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 34643944491 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 13575517499 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 13575517499 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 464925500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17934293500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 46978285991 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 65950975991 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 464925500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17934293500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 46978285991 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46806898722 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 112757874713 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8332500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 550904000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 559236500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 621567000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 621567000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 677372000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 685704500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811538500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811538500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8332500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1172471000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1180803500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027701 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1488910500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1497243000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027145 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996174 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996174 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999980 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999980 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996614 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996614 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999990 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222035 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222035 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097673 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.254101 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254101 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562745 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562745 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246799 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158082 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246799 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222329 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222329 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093564 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.249012 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249012 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.552554 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.552554 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243042 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153745 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243042 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226128 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 50761.235955 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59823.938056 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31373.954837 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31373.954837 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19288.362296 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19288.362296 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1099333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1099333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48243.449741 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48243.449741 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31815.540739 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 35803.680263 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35803.680263 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 58550.043216 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 58550.043216 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 38352.282068 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 36506.855443 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 38352.282068 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43523.410547 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218798 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 47696.316200 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60275.447456 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31180.899835 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31180.899835 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19270.223778 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19270.223778 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2850999 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2850999 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48033.169385 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48033.169385 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32092.287527 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34717.232569 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34717.232569 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 57409.047655 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 57409.047655 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37442.533808 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35935.044345 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37442.533808 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43171.931250 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100898.168498 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101182.648815 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117454.081633 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117454.081633 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107536.434355 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 107713.556393 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126250.544493 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 126250.544493 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109046.781994 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 109141.648951 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116988.331893 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 117026.965765 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 24065952 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12401926 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1256 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2060689 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2060329 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 360 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 934376 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 11053796 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5292 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5292 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4812576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 8031153 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2767424 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1034593 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 454030 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 361772 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 513435 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1276992 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1207288 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956462 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5025648 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 440267 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 433765 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17868522 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18112795 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 459206 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1298566 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 37739089 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762364336 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703129592 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1750272 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4881112 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1472125312 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6734851 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19529823 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.125012 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.330788 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 23835470 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12272459 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1390 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 2000895 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2000561 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 900425 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10970003 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6428 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6428 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4651207 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 8011843 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2673516 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 976496 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 442024 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 347278 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 498740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1227372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1161574 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5972779 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4961310 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 435892 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 427958 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17917345 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17734263 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 424426 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1271663 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 37347697 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 764444720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 688461274 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1618840 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4797400 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1459322234 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6483444 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 19136823 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.123774 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.329377 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 17088727 87.50% 87.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2440736 12.50% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 360 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 16768514 87.62% 87.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2367975 12.37% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19529823 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23888032965 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176197847 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 19136823 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23662576976 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176028266 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8940771887 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8965097194 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8370756543 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8193842587 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 240887058 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 222514103 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 689185473 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 672743976 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40298 # Transaction distribution -system.iobus.trans_dist::ReadResp 40298 # Transaction distribution -system.iobus.trans_dist::WriteReq 136623 # Transaction distribution -system.iobus.trans_dist::WriteResp 136623 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47620 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40336 # Transaction distribution +system.iobus.trans_dist::ReadResp 40336 # Transaction distribution +system.iobus.trans_dist::WriteReq 136625 # Transaction distribution +system.iobus.trans_dist::WriteResp 136625 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47628 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) @@ -3007,18 +3001,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122554 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122562 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231280 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353842 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353922 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47648 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3028,24 +3020,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155661 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155669 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339136 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339136 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496595 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36904500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36916001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) @@ -3058,79 +3049,73 @@ system.iobus.reqLayer16.occupancy 14000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24719501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24643501 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 169000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36442501 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 36445000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 565518728 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 115000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565389979 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 44500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92662000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92668000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147904000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147976000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115596 # number of replacements -system.iocache.tags.tagsinuse 11.294963 # Cycle average of tags in use -system.iocache.tags.total_refs 4 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9125681000000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.424342 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.870620 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.464021 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.241914 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705935 # Average percentage of cache occupancy +system.iocache.tags.replacements 115636 # number of replacements +system.iocache.tags.tagsinuse 11.302848 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115652 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9125688591000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.411882 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.890966 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463243 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.243185 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706428 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040789 # Number of tag accesses -system.iocache.tags.data_accesses 1040789 # Number of data accesses +system.iocache.tags.tag_accesses 1041117 # Number of tag accesses +system.iocache.tags.data_accesses 1041117 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8949 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses -system.iocache.demand_misses::total 8916 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8912 # number of demand (read+write) misses +system.iocache.demand_misses::total 8952 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8876 # number of overall misses -system.iocache.overall_misses::total 8916 # number of overall misses +system.iocache.overall_misses::realview.ide 8912 # number of overall misses +system.iocache.overall_misses::total 8952 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1711011512 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1716211512 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1705648493 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1710848493 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13978863467 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13978863467 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13974401235 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13974401235 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1711011512 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1716580512 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1705648493 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1711217493 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1711011512 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1716580512 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1705648493 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1711217493 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8949 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8912 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8952 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8912 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8952 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3145,54 +3130,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 192768.309148 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 192551.499159 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 191387.847060 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 191177.616829 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130976.533496 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130976.533496 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130934.724112 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130934.724112 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 192768.309148 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 192528.096904 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 191387.847060 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 191154.769102 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 192768.309148 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 192528.096904 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36708 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 191387.847060 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 191154.769102 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 35975 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3726 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3674 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.851852 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.791780 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106693 # number of writebacks -system.iocache.writebacks::total 106693 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8876 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8913 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8949 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8876 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8916 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8912 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8952 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8876 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8916 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8912 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8952 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1267211512 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1270561512 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1260048493 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1263398493 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8642463467 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8642463467 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638001235 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8638001235 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1267211512 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1270780512 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1260048493 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1263617493 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1267211512 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1270780512 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1260048493 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1263617493 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3207,625 +3192,619 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142768.309148 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 142551.499159 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141387.847060 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 141177.616829 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80976.533496 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80976.533496 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80934.724112 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80934.724112 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 142768.309148 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 142528.096904 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 141387.847060 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 141154.769102 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 142768.309148 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 142528.096904 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 141387.847060 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 141154.769102 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1583129 # number of replacements -system.l2c.tags.tagsinuse 63158.639853 # Cycle average of tags in use -system.l2c.tags.total_refs 6207421 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1642739 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.778702 # Average number of references to valid blocks. +system.l2c.tags.replacements 1576044 # number of replacements +system.l2c.tags.tagsinuse 63242.380291 # Cycle average of tags in use +system.l2c.tags.total_refs 6232719 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1635533 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.810818 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 20395.624897 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.797068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 37.096794 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3244.022805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4223.269206 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3404.413573 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 297.158145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 465.494648 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3968.740099 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9359.576527 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17727.446091 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.311213 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000546 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.049500 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064442 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.051947 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004534 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.060558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.142816 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.270499 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.963724 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10142 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49262 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1206 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 394 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8542 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 205 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 375 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5795 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 39993 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.154755 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.751678 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79196544 # Number of tag accesses -system.l2c.tags.data_accesses 79196544 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2898173 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2898173 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 160488 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 150342 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 310830 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37186 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 44723 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 81909 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 154261 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 179531 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 333792 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5731 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3658 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 494823 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 574885 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276090 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6999 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5287 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 532007 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 626878 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 326161 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2852519 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5731 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3658 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 494823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 729146 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 276090 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6999 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 532007 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 806409 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 326161 # number of demand (read+write) hits -system.l2c.demand_hits::total 3186311 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5731 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3658 # number of overall hits -system.l2c.overall_hits::cpu0.inst 494823 # number of overall hits -system.l2c.overall_hits::cpu0.data 729146 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 276090 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6999 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5287 # number of overall hits -system.l2c.overall_hits::cpu1.inst 532007 # number of overall hits -system.l2c.overall_hits::cpu1.data 806409 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 326161 # number of overall hits -system.l2c.overall_hits::total 3186311 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 60003 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 64185 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 124188 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13364 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11770 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25134 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 540709 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 127504 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 668213 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2216 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2032 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 61109 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 146627 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 303108 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3029 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2795 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 49780 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 138724 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 244242 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 953662 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2216 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2032 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 61109 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 687336 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 303108 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3029 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2795 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 49780 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 266228 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 244242 # number of demand (read+write) misses -system.l2c.demand_misses::total 1621875 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2216 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2032 # number of overall misses -system.l2c.overall_misses::cpu0.inst 61109 # number of overall misses -system.l2c.overall_misses::cpu0.data 687336 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 303108 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3029 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2795 # number of overall misses -system.l2c.overall_misses::cpu1.inst 49780 # number of overall misses -system.l2c.overall_misses::cpu1.data 266228 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 244242 # number of overall misses -system.l2c.overall_misses::total 1621875 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 974602500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1153364500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2127967000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 208392500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 213995000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 422387500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 89500490493 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 18793488998 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 108293979491 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 316188000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 293419000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8381886002 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 21271080498 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 433939500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 397141000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6825711500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 19972888998 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 156103388614 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 316188000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 293419000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 8381886002 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 110771570991 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 433939500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 397141000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 6825711500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 38766377996 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 264397368105 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 316188000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 293419000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 8381886002 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 110771570991 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 433939500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 397141000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 6825711500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 38766377996 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of overall miss cycles -system.l2c.overall_miss_latency::total 264397368105 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2898173 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2898173 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 220491 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 214527 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 435018 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 50550 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 56493 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 107043 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 694970 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 307035 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1002005 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7947 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5690 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 555932 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 721512 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 579198 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 10028 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8082 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 581787 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 765602 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 570403 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3806181 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 7947 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5690 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 555932 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1416482 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 579198 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 10028 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 8082 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 581787 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1072637 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 570403 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4808186 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 7947 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5690 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 555932 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1416482 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 579198 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 10028 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 8082 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 581787 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1072637 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 570403 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4808186 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.272134 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.299193 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.285478 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.264372 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.208344 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.234803 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.778032 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.415275 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.666876 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.357118 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.109922 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.203222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.345830 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085564 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181196 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.250556 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.357118 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.109922 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.485242 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.345830 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.085564 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.248200 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.337315 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.357118 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.109922 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.485242 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.345830 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.085564 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.248200 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.337315 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16242.562872 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17969.377580 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 17135.045254 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15593.572284 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18181.393373 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 16805.422933 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165524.321757 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147395.289544 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 162065.059331 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142684.115523 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 144399.114173 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137162.872932 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 145069.328964 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143261.637504 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142089.803220 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137117.547208 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143975.728771 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 163688.380804 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142684.115523 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 144399.114173 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 137162.872932 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 161160.729237 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 143261.637504 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142089.803220 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 137117.547208 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 145613.451613 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 163019.571857 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142684.115523 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 144399.114173 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 137162.872932 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 161160.729237 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143261.637504 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142089.803220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 137117.547208 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 145613.451613 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 163019.571857 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 10461 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 20333.059620 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 44.017365 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 59.342117 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3579.623644 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5086.228075 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3815.151087 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 296.252046 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 450.100507 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3644.907232 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 8614.023056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17319.675542 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.310258 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000672 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000905 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.054621 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.077610 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.058215 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004520 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006868 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.055617 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.131440 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.264277 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.965002 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9601 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49687 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1158 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 504 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 7939 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 193 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5617 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 40824 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.146500 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.758163 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 79314813 # Number of tag accesses +system.l2c.tags.data_accesses 79314813 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2898844 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2898844 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 4 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 4 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 171467 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 140817 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 312284 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 39034 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 42272 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 81306 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 165571 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 166162 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 331733 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6582 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4549 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 520761 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 620991 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 302233 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6543 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4534 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 509705 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 595476 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292636 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2864010 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6582 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 520761 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 786562 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 302233 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6543 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4534 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 509705 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 761638 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 292636 # number of demand (read+write) hits +system.l2c.demand_hits::total 3195743 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6582 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4549 # number of overall hits +system.l2c.overall_hits::cpu0.inst 520761 # number of overall hits +system.l2c.overall_hits::cpu0.data 786562 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 302233 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6543 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4534 # number of overall hits +system.l2c.overall_hits::cpu1.inst 509705 # number of overall hits +system.l2c.overall_hits::cpu1.data 761638 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 292636 # number of overall hits +system.l2c.overall_hits::total 3195743 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 62046 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 61831 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 123877 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 12641 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 11279 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 23920 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 543765 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 121378 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 665143 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2350 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2224 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 62516 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 155884 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 318351 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2672 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2379 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 49130 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 126625 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 232724 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 954855 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2350 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2224 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 62516 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 699649 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 318351 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2672 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2379 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 49130 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 248003 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 232724 # number of demand (read+write) misses +system.l2c.demand_misses::total 1619998 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2350 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2224 # number of overall misses +system.l2c.overall_misses::cpu0.inst 62516 # number of overall misses +system.l2c.overall_misses::cpu0.data 699649 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 318351 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2672 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2379 # number of overall misses +system.l2c.overall_misses::cpu1.inst 49130 # number of overall misses +system.l2c.overall_misses::cpu1.data 248003 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 232724 # number of overall misses +system.l2c.overall_misses::total 1619998 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 1024631500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1063145500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 2087777000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 193873000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 194795500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 388668500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 89836611997 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 17865168996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 107701780993 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 337305500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 317505000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8570748002 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 22562577998 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 382906000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 336227500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6715379500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 18141536999 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 155883444402 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 337305500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 317505000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 8570748002 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 112399189995 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 382906000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 336227500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6715379500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 36006705995 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 263585225395 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 337305500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 317505000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 8570748002 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 112399189995 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 382906000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 336227500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6715379500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 36006705995 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of overall miss cycles +system.l2c.overall_miss_latency::total 263585225395 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 2898844 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2898844 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 233513 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 202648 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 436161 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 51675 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 53551 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 105226 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 709336 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 287540 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 996876 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8932 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6773 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 583277 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 776875 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 620584 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9215 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6913 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 558835 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 722101 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 525360 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3818865 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6773 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 583277 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1486211 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 620584 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9215 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6913 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 558835 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1009641 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525360 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4815741 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6773 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 583277 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1486211 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 620584 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9215 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6913 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 558835 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1009641 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525360 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4815741 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.265707 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.305115 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.284017 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.244625 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.210622 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.227320 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.766583 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.422126 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.667227 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.328363 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107181 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200655 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.344134 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087915 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.175356 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.250036 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.328363 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.107181 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.470760 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.344134 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.087915 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.245635 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.336396 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.328363 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.107181 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.470760 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.344134 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.087915 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.245635 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.336396 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16514.062147 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17194.376607 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16853.629003 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15336.840440 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17270.635695 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 16248.683110 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165212.200118 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147186.219875 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 161922.745925 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 142763.039568 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137096.871233 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 144739.537079 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141331.441782 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 136685.925097 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143269.788738 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 163253.524778 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 142763.039568 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 137096.871233 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 160650.826336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141331.441782 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 136685.925097 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 145186.574336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 162707.130129 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 142763.039568 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 137096.871233 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 160650.826336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141331.441782 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 136685.925097 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 145186.574336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 162707.130129 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17532 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 107 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 141 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 97.766355 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 124.340426 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1242151 # number of writebacks -system.l2c.writebacks::total 1242151 # number of writebacks +system.l2c.writebacks::writebacks 1238890 # number of writebacks +system.l2c.writebacks::total 1238890 # number of writebacks system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 210 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 653 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 13 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 219 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 244 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 263 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 1384 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 210 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 654 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 13 # number of demand (read+write) MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 32 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 528 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 219 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 34 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 244 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 263 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1385 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 210 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 654 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 13 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 32 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 529 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 219 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 34 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 244 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 263 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1385 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 60824 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 60824 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 60003 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 64185 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 124188 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13364 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11770 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 25134 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 540708 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 127504 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 668212 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2216 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2032 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 60899 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 145974 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 303095 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3029 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2795 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 49536 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 138461 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 244241 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 952278 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2216 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2032 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 60899 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 686682 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 303095 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 3029 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2795 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 49536 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 265965 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 244241 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1620490 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2216 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2032 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 60899 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 686682 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 303095 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 3029 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2795 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 49536 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 265965 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 244241 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1620490 # number of overall MSHR misses +system.l2c.overall_mshr_hits::cpu1.data 32 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 529 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 60450 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 60450 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 62046 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 61831 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 123877 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12641 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11279 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 23920 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 543764 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 121378 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 665142 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2350 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2224 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 62297 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 155851 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2672 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2379 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 48886 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 126593 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 954327 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2350 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2224 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 62297 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 699615 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2672 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2379 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 48886 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 247971 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1619469 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2350 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2224 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 62297 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 699615 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2672 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2379 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 48886 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 247971 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1619469 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5458 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 59697 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38273 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6297 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 59814 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38392 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10750 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 97970 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4411059004 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4718897004 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 9129956008 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1022873502 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 899918499 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1922792001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 84093329493 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17518448998 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 101611778491 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 294028000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 273099000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7748135502 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19727243498 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 51959564758 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 403649500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 369191000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6300483000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 18553666498 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40776701375 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 146405762131 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 294028000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 273099000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 7748135502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 103820572991 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 51959564758 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 403649500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 369191000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 6300483000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 36072115496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 40776701375 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 248017540622 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 294028000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 273099000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 7748135502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 103820572991 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 51959564758 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 403649500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 369191000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 6300483000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 36072115496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40776701375 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 248017540622 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 12725 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 98206 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4564244502 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4544780000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 9109024502 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 967924994 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 862182998 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1830107992 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 84398895997 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16651388996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 101050284993 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 295265000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7922359002 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 21000185498 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 312437500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6197673000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 16871940499 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 146278359902 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 295265000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 7922359002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 105399081495 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 312437500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 6197673000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 33523329495 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 247328644895 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 295265000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 7922359002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 105399081495 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 312437500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 6197673000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 33523329495 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 247328644895 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5447961500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5339273500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7124500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 452516500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8304410500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5424521033 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 531333000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5955854033 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 563876500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8307082500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5257909033 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 701977500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5959886533 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10872482533 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10597182533 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7124500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 983849500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 14260264533 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1265854000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 14266969033 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.272134 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.299193 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.285478 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.264372 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.208344 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.234803 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.778031 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.415275 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.666875 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.202317 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.180852 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250193 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.484780 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.247954 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.337027 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.484780 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.247954 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.337027 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73513.974368 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73520.246226 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73517.215898 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76539.471865 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76458.666015 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76501.631296 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155524.478079 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137395.289544 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 152065.180648 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 135142.172565 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133999.223594 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153742.669820 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 151191.633086 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135627.302450 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 153050.954108 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 151191.633086 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135627.302450 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 153050.954108 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.265707 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.305115 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.284017 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.244625 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.210622 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.227320 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.766582 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.422126 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.667226 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200613 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.175312 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.249898 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.470737 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245603 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.336287 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.470737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245603 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.336287 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73562.268349 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73503.258883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73532.814824 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76570.286686 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76441.439667 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76509.531438 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155212.364182 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137186.219875 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 151922.875105 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134745.272716 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133277.041377 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153279.075099 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150652.975558 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135190.524275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 152722.061920 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150652.975558 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135190.524275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 152722.061920 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165697.299188 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166037.674534 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 82908.849395 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139109.343853 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164474.122464 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100403.061224 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155615.029734 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89546.847705 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138881.908918 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164494.713834 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109206.207218 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155237.719655 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165084.763635 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165268.516290 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91520.883721 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 145557.461805 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99477.721022 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145275.940706 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 59697 # Transaction distribution -system.membus.trans_dist::ReadResp 1020888 # Transaction distribution -system.membus.trans_dist::WriteReq 38273 # Transaction distribution -system.membus.trans_dist::WriteResp 38273 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1348844 # Transaction distribution -system.membus.trans_dist::CleanEvict 267564 # Transaction distribution -system.membus.trans_dist::UpgradeReq 448101 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 314840 # Transaction distribution -system.membus.trans_dist::UpgradeResp 158230 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 678893 # Transaction distribution -system.membus.trans_dist::ReadExResp 659308 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 961191 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106727 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106727 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122554 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 59814 # Transaction distribution +system.membus.trans_dist::ReadResp 1023090 # Transaction distribution +system.membus.trans_dist::WriteReq 38392 # Transaction distribution +system.membus.trans_dist::WriteResp 38392 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1345584 # Transaction distribution +system.membus.trans_dist::CleanEvict 266165 # Transaction distribution +system.membus.trans_dist::UpgradeReq 443726 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 302861 # Transaction distribution +system.membus.trans_dist::UpgradeResp 156448 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 676664 # Transaction distribution +system.membus.trans_dist::ReadExResp 656494 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 963276 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122562 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5713992 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5862068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342759 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342759 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6204827 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155661 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5690514 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5839062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342298 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342298 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6181360 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155669 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182954368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 183161477 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7272320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190433797 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 627031 # Total snoops (count) -system.membus.snoop_fanout::samples 4226315 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182696832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 182904877 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190162093 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 613313 # Total snoops (count) +system.membus.snoop_fanout::samples 4205672 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4226315 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4205672 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4226315 # Request fanout histogram -system.membus.reqLayer0.occupancy 98488499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4205672 # Request fanout histogram +system.membus.reqLayer0.occupancy 98421997 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21525971 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21914471 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9456985184 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9436458556 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8888143010 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8880795227 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228798971 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228859415 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3879,57 +3858,57 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12205155 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6621083 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1960564 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 171525 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 155955 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 15570 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 59699 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4664873 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38273 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38273 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4247047 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1614803 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 750027 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 396749 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1146775 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 211 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1140836 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1140836 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4612412 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106727 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8853195 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7749082 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16602277 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269317869 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 224565592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 493883461 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3357154 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8803755 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.347401 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.479844 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12199905 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6623903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1949036 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 168152 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 152817 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 15335 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 59816 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4662380 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38392 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38392 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4244441 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1619343 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 747362 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 384167 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1131529 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1137603 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1137603 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4609811 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9241165 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7356268 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16597433 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283441843 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 210970938 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 494412781 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3322045 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8775737 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.344900 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.478998 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5760896 65.44% 65.44% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3027289 34.39% 99.82% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 15570 0.18% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5764320 65.68% 65.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2996082 34.14% 99.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 15335 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8803755 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9517655622 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8775737 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9513972562 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2614297 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2693663 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4898920623 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5075177047 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4389147401 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4195991011 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12586 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 12889 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5763 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5680 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal index bbb96f95b..8e5190276 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal @@ -105,62 +105,62 @@ [ 2.144312] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.144339] pci_bus 0000:00: fixups for bus
[ 2.144347] pci_bus 0000:00: bus scan returning with max=00
-[ 2.144359] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.144358] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.144376] pci 0000:00:00.0: fixup irq: got 33
[ 2.144384] pci 0000:00:00.0: assigning IRQ 33
[ 2.144394] pci 0000:00:01.0: fixup irq: got 34
[ 2.144402] pci 0000:00:01.0: assigning IRQ 34
[ 2.144413] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.144426] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.144439] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.144438] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.144451] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.144463] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.144474] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.144462] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.144473] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.144485] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.144496] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.144948] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.145138] ata_piix 0000:00:01.0: version 2.13
+[ 2.145137] ata_piix 0000:00:01.0: version 2.13
[ 2.145148] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.145170] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.145355] scsi0 : ata_piix
-[ 2.145414] scsi1 : ata_piix
-[ 2.145435] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.145447] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.145523] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.145535] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.145548] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.145560] e1000 0000:00:00.0: enabling bus mastering
+[ 2.145169] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.145354] scsi0 : ata_piix
+[ 2.145413] scsi1 : ata_piix
+[ 2.145434] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.145446] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.145522] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.145534] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.145547] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.145559] e1000 0000:00:00.0: enabling bus mastering
[ 2.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.290714] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290739] ata1.00: configured for UDMA/33
-[ 2.290783] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.290882] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.290916] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.290925] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.290941] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.290995] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.291062] sda: sda1
-[ 2.291150] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.290784] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.290883] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.290917] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.290926] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.290943] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.290996] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291064] sda: sda1
+[ 2.291152] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.410949] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.410962] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.410980] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.410990] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.411008] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.411020] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.411069] usbcore: registered new interface driver usb-storage
-[ 2.411117] mousedev: PS/2 mouse device common for all mice
-[ 2.411224] usbcore: registered new interface driver usbhid
-[ 2.411234] usbhid: USB HID core driver
-[ 2.411259] TCP: cubic registered
+[ 2.411070] usbcore: registered new interface driver usb-storage
+[ 2.411118] mousedev: PS/2 mouse device common for all mice
+[ 2.411225] usbcore: registered new interface driver usbhid
+[ 2.411235] usbhid: USB HID core driver
+[ 2.411260] TCP: cubic registered
[ 2.411267] NET: Registered protocol family 17
- -[ 2.411614] devtmpfs: mounted
-[ 2.411651] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+ +[ 2.411619] devtmpfs: mounted
+[ 2.411656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.447825] udevd[609]: starting version 182
+[ 2.447817] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.512686] random: dd urandom read with 18 bits of entropy available
+[ 2.532679] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.620897] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.640899] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
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