diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt | 2843 |
1 files changed, 1425 insertions, 1418 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 2bd86426a..400af0c45 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.558698 # Number of seconds simulated -sim_ticks 51558697863000 # Number of ticks simulated -final_tick 51558697863000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.558690 # Number of seconds simulated +sim_ticks 51558690384000 # Number of ticks simulated +final_tick 51558690384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167711 # Simulator instruction rate (inst/s) -host_op_rate 197118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7760882097 # Simulator tick rate (ticks/s) -host_mem_usage 692228 # Number of bytes of host memory used -host_seconds 6643.41 # Real time elapsed on the host -sim_insts 1114173091 # Number of instructions simulated -sim_ops 1309536110 # Number of ops (including micro ops) simulated +host_inst_rate 207581 # Simulator instruction rate (inst/s) +host_op_rate 243983 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9602431196 # Simulator tick rate (ticks/s) +host_mem_usage 695472 # Number of bytes of host memory used +host_seconds 5369.34 # Real time elapsed on the host +sim_insts 1114574366 # Number of instructions simulated +sim_ops 1310024478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 691712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 570944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6573600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 114559048 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428096 # Number of bytes read from this memory -system.physmem.bytes_read::total 122823400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6573600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6573600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 143392768 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 681408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 573376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6481504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112175560 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 429184 # Number of bytes read from this memory +system.physmem.bytes_read::total 120341032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6481504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6481504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 141267776 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 143413348 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 118665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1789998 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6689 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1935081 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2240512 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 141288356 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10647 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 117226 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1752756 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6706 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1896294 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2207309 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2243085 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 13416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 11074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 127497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2221915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2382205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 127497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 127497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2781156 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 2209882 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 13216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 11121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 125711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2175687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2334059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 125711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 125711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2739941 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2781555 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2781156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 13416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 11074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 127497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2222314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5163760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1935081 # Number of read requests accepted -system.physmem.writeReqs 2243085 # Number of write requests accepted -system.physmem.readBursts 1935081 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2243085 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 123796992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48192 # Total number of bytes read from write queue -system.physmem.bytesWritten 143410368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 122823400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 143413348 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 753 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2282 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 2740340 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2739941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 13216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 11121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 125711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2176086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5074399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1896294 # Number of read requests accepted +system.physmem.writeReqs 2209882 # Number of write requests accepted +system.physmem.readBursts 1896294 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2209882 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 121325696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue +system.physmem.bytesWritten 141284736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 120341032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 141288356 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114857 # Per bank write bursts -system.physmem.perBankRdBursts::1 123887 # Per bank write bursts -system.physmem.perBankRdBursts::2 121380 # Per bank write bursts -system.physmem.perBankRdBursts::3 115864 # Per bank write bursts -system.physmem.perBankRdBursts::4 115150 # Per bank write bursts -system.physmem.perBankRdBursts::5 124779 # Per bank write bursts -system.physmem.perBankRdBursts::6 116343 # Per bank write bursts -system.physmem.perBankRdBursts::7 120532 # Per bank write bursts -system.physmem.perBankRdBursts::8 117169 # Per bank write bursts -system.physmem.perBankRdBursts::9 147715 # Per bank write bursts -system.physmem.perBankRdBursts::10 116324 # Per bank write bursts -system.physmem.perBankRdBursts::11 125031 # Per bank write bursts -system.physmem.perBankRdBursts::12 116553 # Per bank write bursts -system.physmem.perBankRdBursts::13 122187 # Per bank write bursts -system.physmem.perBankRdBursts::14 118707 # Per bank write bursts -system.physmem.perBankRdBursts::15 117850 # Per bank write bursts -system.physmem.perBankWrBursts::0 135590 # Per bank write bursts -system.physmem.perBankWrBursts::1 141676 # Per bank write bursts -system.physmem.perBankWrBursts::2 140587 # Per bank write bursts -system.physmem.perBankWrBursts::3 138605 # Per bank write bursts -system.physmem.perBankWrBursts::4 137623 # Per bank write bursts -system.physmem.perBankWrBursts::5 144276 # Per bank write bursts -system.physmem.perBankWrBursts::6 136529 # Per bank write bursts -system.physmem.perBankWrBursts::7 140386 # Per bank write bursts -system.physmem.perBankWrBursts::8 138327 # Per bank write bursts -system.physmem.perBankWrBursts::9 145050 # Per bank write bursts -system.physmem.perBankWrBursts::10 137213 # Per bank write bursts -system.physmem.perBankWrBursts::11 144076 # Per bank write bursts -system.physmem.perBankWrBursts::12 138694 # Per bank write bursts -system.physmem.perBankWrBursts::13 142077 # Per bank write bursts -system.physmem.perBankWrBursts::14 140963 # Per bank write bursts -system.physmem.perBankWrBursts::15 139115 # Per bank write bursts +system.physmem.perBankRdBursts::0 112674 # Per bank write bursts +system.physmem.perBankRdBursts::1 120331 # Per bank write bursts +system.physmem.perBankRdBursts::2 120633 # Per bank write bursts +system.physmem.perBankRdBursts::3 114638 # Per bank write bursts +system.physmem.perBankRdBursts::4 113111 # Per bank write bursts +system.physmem.perBankRdBursts::5 123581 # Per bank write bursts +system.physmem.perBankRdBursts::6 115477 # Per bank write bursts +system.physmem.perBankRdBursts::7 120263 # Per bank write bursts +system.physmem.perBankRdBursts::8 112291 # Per bank write bursts +system.physmem.perBankRdBursts::9 145720 # Per bank write bursts +system.physmem.perBankRdBursts::10 114582 # Per bank write bursts +system.physmem.perBankRdBursts::11 120005 # Per bank write bursts +system.physmem.perBankRdBursts::12 112695 # Per bank write bursts +system.physmem.perBankRdBursts::13 118645 # Per bank write bursts +system.physmem.perBankRdBursts::14 113317 # Per bank write bursts +system.physmem.perBankRdBursts::15 117751 # Per bank write bursts +system.physmem.perBankWrBursts::0 133340 # Per bank write bursts +system.physmem.perBankWrBursts::1 139177 # Per bank write bursts +system.physmem.perBankWrBursts::2 138321 # Per bank write bursts +system.physmem.perBankWrBursts::3 137224 # Per bank write bursts +system.physmem.perBankWrBursts::4 136590 # Per bank write bursts +system.physmem.perBankWrBursts::5 143143 # Per bank write bursts +system.physmem.perBankWrBursts::6 136203 # Per bank write bursts +system.physmem.perBankWrBursts::7 139934 # Per bank write bursts +system.physmem.perBankWrBursts::8 134977 # Per bank write bursts +system.physmem.perBankWrBursts::9 143618 # Per bank write bursts +system.physmem.perBankWrBursts::10 135619 # Per bank write bursts +system.physmem.perBankWrBursts::11 140132 # Per bank write bursts +system.physmem.perBankWrBursts::12 134815 # Per bank write bursts +system.physmem.perBankWrBursts::13 138770 # Per bank write bursts +system.physmem.perBankWrBursts::14 136807 # Per bank write bursts +system.physmem.perBankWrBursts::15 138904 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 498 # Number of times write queue was full causing retry -system.physmem.totGap 51558696478500 # Total gap between requests +system.physmem.numWrRetry 518 # Number of times write queue was full causing retry +system.physmem.totGap 51558689064500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1913796 # Read request sizes (log2) +system.physmem.readPktSize::6 1875009 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2240512 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1142122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 697940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2207309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1116053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 690517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,88 +160,88 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 36011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 84715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 118224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 127097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 131612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 139104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 141132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 137785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 140939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 143104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 134560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 133279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 134737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 146876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 129080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 132587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 83457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 116558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 125148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 129368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 131713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 136998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 138946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 135798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 138971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 141020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 132458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 131167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 132874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 144896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 126854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 129875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1973 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1141 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 951139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.933676 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.585937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.458614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 376624 39.60% 39.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 238014 25.02% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 91172 9.59% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 53576 5.63% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 39458 4.15% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27371 2.88% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21519 2.26% 89.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17750 1.87% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 85655 9.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 951139 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 118362 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.342416 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 51.876252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 118357 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 1272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1209 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 930002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 282.376133 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.748609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.895017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 369309 39.71% 39.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 231862 24.93% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88277 9.49% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51814 5.57% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37452 4.03% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26213 2.82% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21092 2.27% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17823 1.92% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 86160 9.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 930002 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 116289 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.301748 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 52.348914 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 116283 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 118362 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 118362 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.931642 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.417353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.979781 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 114164 96.45% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 1862 1.57% 98.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1234 1.04% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 621 0.52% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 196 0.17% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 102 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 116289 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 116288 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.983653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.436820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.158845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 112077 96.38% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 1857 1.60% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1248 1.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 622 0.53% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 199 0.17% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 102 0.09% 99.84% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads @@ -259,68 +259,68 @@ system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Wr system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 118362 # Writes before turning the bus around for reads -system.physmem.totQLat 71570448504 # Total ticks spent queuing -system.physmem.totMemAccLat 107839098504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9671640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37000.16 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 116288 # Writes before turning the bus around for reads +system.physmem.totQLat 70130172482 # Total ticks spent queuing +system.physmem.totMemAccLat 105674809982 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9478570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36994.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55750.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55744.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.74 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.69 # Average write queue length when enqueuing -system.physmem.readRowHits 1560611 # Number of row buffer hits during reads -system.physmem.writeRowHits 1663363 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.23 # Row buffer hit rate for writes -system.physmem.avgGap 12340030.64 # Average gap between requests -system.physmem.pageHitRate 77.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3363189900 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1787570235 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6802934880 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5821719840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 51899586960.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 51612190140 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3200334720 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 101759183310 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 76295730720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12252381205680 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12554961718635 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.508122 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51437094541003 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5396479999 # Time in different power states -system.physmem_0.memoryStateTime::REF 22052840000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51015251458000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 198686963242 # Time in different power states -system.physmem_0.memoryStateTime::ACT 94153955748 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 223156166011 # Time in different power states -system.physmem_1.actEnergy 3427956840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1822002270 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7008167040 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5875188300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 53218604400.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 52383682290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3161186880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 106497624090 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 77662512480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12248740584255 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12559836053265 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.602662 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51435493097538 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5216830750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22612324000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 50999709861500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 202245988185 # Time in different power states -system.physmem_1.memoryStateTime::ACT 95365744212 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 233547114353 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.06 # Average write queue length when enqueuing +system.physmem.readRowHits 1529656 # Number of row buffer hits during reads +system.physmem.writeRowHits 1643629 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.45 # Row buffer hit rate for writes +system.physmem.avgGap 12556375.83 # Average gap between requests +system.physmem.pageHitRate 77.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3321699360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1765517490 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6716655120 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5762509380 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 51680160480.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 50972480280 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3129835680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 101675150490 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 76210464000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12252798333465 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12554072367525 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.490909 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51438669732358 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5228340749 # Time in different power states +system.physmem_0.memoryStateTime::REF 21959504000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51017233392500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 198464631937 # Time in different power states +system.physmem_0.memoryStateTime::ACT 92832806893 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 222971707921 # Time in different power states +system.physmem_1.actEnergy 3318507780 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1763828715 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6818742840 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5761011240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51892211280.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 51236173110 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3081583200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 102800614920 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 76208995200 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12252080918985 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12555002532930 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.508949 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51438215485769 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5081473992 # Time in different power states +system.physmem_1.memoryStateTime::REF 22049198000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51014315527500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 198460418659 # Time in different power states +system.physmem_1.memoryStateTime::ACT 93344226239 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 225439539610 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -337,30 +337,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 292003156 # Number of BP lookups -system.cpu.branchPred.condPredicted 199825428 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13707860 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 209782047 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131422635 # Number of BTB hits +system.cpu.branchPred.lookups 292068322 # Number of BP lookups +system.cpu.branchPred.condPredicted 199851600 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13713135 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 209724607 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131462172 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.647227 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37743675 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 403344 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 8164760 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6089475 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2075285 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 798713 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.683237 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37751449 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 403092 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 8173057 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6085508 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2087549 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 802881 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,90 +390,91 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 1433016 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1433016 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 32195 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277777 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 671696 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 761320 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2826.976830 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 21785.764506 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 754204 99.07% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4652 0.61% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 981 0.13% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 445 0.06% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 347 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 34 0.00% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 244 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 36 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 13 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 353 0.05% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 1435892 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1435892 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31985 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277981 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 675717 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 760175 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2830.191074 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 21829.241774 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 752984 99.05% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4669 0.61% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1022 0.13% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 473 0.06% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 342 0.04% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.00% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 237 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 34 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 14 0.00% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 355 0.05% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::917504-983039 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 761320 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 803371 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 26077.733077 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21137.704877 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20668.738137 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-131071 799705 99.54% 99.54% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-262143 2825 0.35% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-393215 589 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-524287 118 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-655359 123 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-786431 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::786432-917503 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::1.17965e+06-1.31072e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 803371 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1075651264316 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.736998 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.521821 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1071482592816 99.61% 99.61% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2636080000 0.25% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 763976000 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 297116500 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 205516000 0.02% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 123566500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 47691000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 91565500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3134000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1075651264316 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 277778 89.61% 89.61% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 32195 10.39% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 309973 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1433016 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::786432-851967 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 760175 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 806276 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26170.477603 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21293.851875 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20136.943306 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 787717 97.70% 97.70% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 14855 1.84% 99.54% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1801 0.22% 99.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 1099 0.14% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 441 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 139 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 81 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 59 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 68 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 806276 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1071348818020 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.742300 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.520529 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1067163432520 99.61% 99.61% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2639718000 0.25% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 767294500 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 303032500 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 205205000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 125461000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 48256000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 92861500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3532500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1071348818020 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 277982 89.68% 89.68% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 31985 10.32% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 309967 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1435892 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1433016 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309973 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1435892 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309967 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309973 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1742989 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309967 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1745859 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 218874380 # DTB read hits -system.cpu.dtb.read_misses 1009020 # DTB read misses -system.cpu.dtb.write_hits 193682033 # DTB write hits -system.cpu.dtb.write_misses 423996 # DTB write misses +system.cpu.dtb.read_hits 219013119 # DTB read hits +system.cpu.dtb.read_misses 1011306 # DTB read misses +system.cpu.dtb.write_hits 193770026 # DTB write hits +system.cpu.dtb.write_misses 424586 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 89021 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 108 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 17262 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 88767 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 111 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 16184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 85593 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 219883400 # DTB read accesses -system.cpu.dtb.write_accesses 194106029 # DTB write accesses +system.cpu.dtb.perms_faults 85758 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 220024425 # DTB read accesses +system.cpu.dtb.write_accesses 194194612 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 412556413 # DTB hits -system.cpu.dtb.misses 1433016 # DTB misses -system.cpu.dtb.accesses 413989429 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 412783145 # DTB hits +system.cpu.dtb.misses 1435892 # DTB misses +system.cpu.dtb.accesses 414219037 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -503,947 +504,953 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 178466 # Table walker walks requested -system.cpu.itb.walker.walksLong 178466 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1508 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 129505 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 20095 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 158371 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1754.443680 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 17709.281636 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-65535 157140 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-131071 1047 0.66% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-196607 42 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-327679 14 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-393215 7 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::524288-589823 40 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::589824-655359 48 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 158371 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 151108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29265.005824 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23190.077140 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 30431.733671 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 145001 95.96% 95.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5046 3.34% 99.30% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 391 0.26% 99.56% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 366 0.24% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 100 0.07% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 51 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 85 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 178617 # Table walker walks requested +system.cpu.itb.walker.walksLong 178617 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1509 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 129197 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 20173 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 158444 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1791.778168 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 17776.926489 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-65535 157195 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-131071 1061 0.67% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-196607 49 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-262143 23 0.01% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-393215 12 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-458751 2 0.00% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::524288-589823 45 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::589824-655359 46 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 158444 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 150879 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29477.399108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23380.752932 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 29925.423831 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 144789 95.96% 95.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5035 3.34% 99.30% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 407 0.27% 99.57% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 355 0.24% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 85 0.06% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 65 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 23 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 82 0.05% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 151108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 912439402568 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.949255 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.219812 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 46367810152 5.08% 5.08% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 866006867916 94.91% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 63907500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 568000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 249000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 912439402568 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 129505 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1508 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 131013 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 150879 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 908136653272 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.948518 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.221299 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 46816690152 5.16% 5.16% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 861256760620 94.84% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 62690500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 511000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 908136653272 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 129197 98.85% 98.85% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1509 1.15% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 130706 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178466 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 178466 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178617 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 178617 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 131013 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 131013 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 309479 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 465485773 # ITB inst hits -system.cpu.itb.inst_misses 178466 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130706 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 130706 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 309323 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 465622680 # ITB inst hits +system.cpu.itb.inst_misses 178617 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 63716 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 62647 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 62354 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 443320 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 442443 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 465664239 # ITB inst accesses -system.cpu.itb.hits 465485773 # DTB hits -system.cpu.itb.misses 178466 # DTB misses -system.cpu.itb.accesses 465664239 # DTB accesses -system.cpu.numPwrStateTransitions 34324 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 17162 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 2940404395.507225 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 58760863847.973442 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7839 45.68% 45.68% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.12% 99.80% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 465801297 # ITB inst accesses +system.cpu.itb.hits 465622680 # DTB hits +system.cpu.itb.misses 178617 # DTB misses +system.cpu.itb.accesses 465801297 # DTB accesses +system.cpu.numPwrStateTransitions 34330 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 17165 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2940001446.310807 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 58531807829.842911 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7841 45.68% 45.68% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.11% 99.79% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988780801904 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 17162 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1095477627305 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50463220235695 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2190964579 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 17165 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1093565558075 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50465124825925 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2187140442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 794033282 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1302230220 # Number of instructions fetch has processed -system.cpu.fetch.Branches 292003156 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 175255785 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1304336456 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29502488 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4651258 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26755 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11711903 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1225327 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 1089 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 465024484 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6899822 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 52313 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2130737314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.716190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.134027 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 793785781 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1302631708 # Number of instructions fetch has processed +system.cpu.fetch.Branches 292068322 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 175299129 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1300965183 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29519562 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4657753 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 25879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11707627 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1236073 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 927 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 465162073 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6904477 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 52597 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2127139004 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.717629 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.134701 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1403414987 65.87% 65.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 283475853 13.30% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 89003023 4.18% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 354843451 16.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1399565872 65.80% 65.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 283601888 13.33% 79.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 89018844 4.18% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 354952400 16.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2130737314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133276 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.594364 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 615599644 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 888388322 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542818505 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73189293 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10741550 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41458105 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4067803 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1416661162 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33069720 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10741550 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 678370602 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 94749069 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569457122 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 557397759 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 220021212 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1392357267 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 8139910 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7467928 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 990269 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1135391 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 140197147 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22858 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1342242693 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2216016664 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1651872272 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1433815 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1263306379 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78936311 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44081382 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39609601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160762582 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 223936207 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 198122558 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12861166 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11120462 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1339067750 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44403277 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1369076757 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4228585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 73934913 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42101353 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 368543 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2130737314 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.642537 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.913709 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2127139004 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133539 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.595587 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 615428593 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 884736584 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 543030027 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 73193860 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10749940 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41477613 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4067608 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1417243244 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 33090232 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10749940 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 678230325 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 91937865 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 569242294 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 557610269 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219368311 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1392930802 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 8136567 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7440637 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 990068 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1113298 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 139552598 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22837 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1342716381 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2216807318 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1652527627 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1431919 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1263732146 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78984232 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44095214 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39617186 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160769192 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 224047664 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 198221089 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12872997 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11132343 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1339626168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44413765 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1369656198 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4234304 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 74015451 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42135581 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 368828 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2127139004 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.643896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.914248 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1278640571 60.01% 60.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 452467629 21.24% 81.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 292658965 13.74% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96618652 4.53% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10322243 0.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29254 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1274738634 59.93% 59.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 452592629 21.28% 81.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 292740987 13.76% 94.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96714663 4.55% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10322849 0.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29242 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2130737314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2127139004 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 74049078 33.84% 33.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90108 0.04% 33.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26756 0.01% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 482 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 59033401 26.97% 60.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 85651168 39.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 74109343 33.81% 33.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90161 0.04% 33.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26765 0.01% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 458 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 59034015 26.93% 60.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 85210307 38.88% 99.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 64791 0.03% 99.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 640346 0.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 55 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 945875031 69.09% 69.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2941932 0.21% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129428 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 946221695 69.08% 69.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2942835 0.21% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 130438 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 112221 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 112188 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 223931934 16.36% 85.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 196085738 14.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 223953856 16.35% 85.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 195515958 14.27% 99.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 118365 0.01% 99.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 660412 0.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1369076757 # Type of FU issued -system.cpu.iq.rate 0.624874 # Inst issue rate -system.cpu.iq.fu_busy_cnt 218850993 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.159853 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5089559021 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1456673430 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1346855595 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2411384 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 915419 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 886368 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1586411072 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1516623 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5720273 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1369656198 # Type of FU issued +system.cpu.iq.rate 0.626231 # Inst issue rate +system.cpu.iq.fu_busy_cnt 219176186 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.160023 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5087371498 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1457327579 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1347394357 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2490391 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 913879 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 884967 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1587235373 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1596980 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5732534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17413416 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22608 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 184689 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8002869 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17426729 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22539 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 187787 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8018407 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3613750 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2051788 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3639533 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2053743 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10741550 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13180703 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5272349 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1383757283 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10749940 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12646274 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5267578 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1384326807 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 223936207 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 198122558 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39070088 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 183909 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4898355 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 184689 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4057329 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6115164 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10172493 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1355379185 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 218880930 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12294353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 224047664 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 198221089 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39077844 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 183202 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4894696 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 187787 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4060868 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6118781 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10179649 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1355949241 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 219017773 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12300796 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 286256 # number of nop insts executed -system.cpu.iew.exec_refs 412572980 # number of memory reference insts executed -system.cpu.iew.exec_branches 257403074 # Number of branches executed -system.cpu.iew.exec_stores 193692050 # Number of stores executed -system.cpu.iew.exec_rate 0.618622 # Inst execution rate -system.cpu.iew.wb_sent 1348783541 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1347741963 # cumulative count of insts written-back -system.cpu.iew.wb_producers 576070929 # num instructions producing a value -system.cpu.iew.wb_consumers 948341211 # num instructions consuming a value -system.cpu.iew.wb_rate 0.615136 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.607451 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 63015193 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 44034734 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9698166 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2116507295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.618725 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.263721 # Number of insts commited each cycle +system.cpu.iew.exec_nop 286874 # number of nop insts executed +system.cpu.iew.exec_refs 412797364 # number of memory reference insts executed +system.cpu.iew.exec_branches 257488143 # Number of branches executed +system.cpu.iew.exec_stores 193779591 # Number of stores executed +system.cpu.iew.exec_rate 0.619964 # Inst execution rate +system.cpu.iew.wb_sent 1349320641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1348279324 # cumulative count of insts written-back +system.cpu.iew.wb_producers 576318139 # num instructions producing a value +system.cpu.iew.wb_consumers 948680474 # num instructions consuming a value +system.cpu.iew.wb_rate 0.616458 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.607494 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 63090267 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 44044937 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9703294 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2112894773 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.620014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.265043 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1435626131 67.83% 67.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 397528537 18.78% 86.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150810671 7.13% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44606790 2.11% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36101901 1.71% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18021060 0.85% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 11293216 0.53% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5858251 0.28% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16660738 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1431908907 67.77% 67.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 397571073 18.82% 86.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150815124 7.14% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44594147 2.11% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36107553 1.71% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18031210 0.85% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 11307158 0.54% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5865302 0.28% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16694299 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2116507295 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1114173091 # Number of instructions committed -system.cpu.commit.committedOps 1309536110 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2112894773 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1114574366 # Number of instructions committed +system.cpu.commit.committedOps 1310024478 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 396642479 # Number of memory references committed -system.cpu.commit.loads 206522790 # Number of loads committed -system.cpu.commit.membars 9192719 # Number of memory barriers committed -system.cpu.commit.branches 249090207 # Number of branches committed -system.cpu.commit.fp_insts 874521 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1196753296 # Number of committed integer instructions. -system.cpu.commit.function_calls 31104441 # Number of function calls committed. +system.cpu.commit.refs 396823616 # Number of memory references committed +system.cpu.commit.loads 206620934 # Number of loads committed +system.cpu.commit.membars 9197183 # Number of memory barriers committed +system.cpu.commit.branches 249169048 # Number of branches committed +system.cpu.commit.fp_insts 873305 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1197213012 # Number of committed integer instructions. +system.cpu.commit.function_calls 31117535 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 910131481 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2552727 0.19% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 103687 0.01% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 910437285 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2553089 0.19% 69.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 104752 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 8 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 21 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.70% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105694 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 105694 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 206522790 15.77% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 190119689 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 206508219 15.76% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 189547828 14.47% 99.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 112715 0.01% 99.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 654854 0.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1309536110 # Class of committed instruction -system.cpu.commit.bw_lim_events 16660738 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3462896243 # The number of ROB reads -system.cpu.rob.rob_writes 2759222856 # The number of ROB writes -system.cpu.timesIdled 9103079 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 60227265 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100926431181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1114173091 # Number of Instructions Simulated -system.cpu.committedOps 1309536110 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.966449 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.966449 # CPI: Total CPI of All Threads -system.cpu.ipc 0.508531 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.508531 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1609897597 # number of integer regfile reads -system.cpu.int_regfile_writes 948614350 # number of integer regfile writes -system.cpu.fp_regfile_reads 1422281 # number of floating regfile reads -system.cpu.fp_regfile_writes 763660 # number of floating regfile writes -system.cpu.cc_regfile_reads 314738541 # number of cc regfile reads -system.cpu.cc_regfile_writes 315610902 # number of cc regfile writes -system.cpu.misc_regfile_reads 3478507383 # number of misc regfile reads -system.cpu.misc_regfile_writes 44953668 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 13773933 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982218 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 363424605 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13774445 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.383974 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 1310024478 # Class of committed instruction +system.cpu.commit.bw_lim_events 16694299 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3459813368 # The number of ROB reads +system.cpu.rob.rob_writes 2760364536 # The number of ROB writes +system.cpu.timesIdled 9090851 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60001438 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100930240360 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1114574366 # Number of Instructions Simulated +system.cpu.committedOps 1310024478 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.962310 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.962310 # CPI: Total CPI of All Threads +system.cpu.ipc 0.509603 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.509603 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1610546046 # number of integer regfile reads +system.cpu.int_regfile_writes 949011498 # number of integer regfile writes +system.cpu.fp_regfile_reads 1420249 # number of floating regfile reads +system.cpu.fp_regfile_writes 762248 # number of floating regfile writes +system.cpu.cc_regfile_reads 314797086 # number of cc regfile reads +system.cpu.cc_regfile_writes 315669715 # number of cc regfile writes +system.cpu.misc_regfile_reads 3475493523 # number of misc regfile reads +system.cpu.misc_regfile_writes 44962873 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 13773422 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.982216 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 363599894 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13773934 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.397679 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.982218 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.982216 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1609792532 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1609792532 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 188105539 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 188105539 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164299305 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164299305 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 464298 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 464298 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335039 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335039 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4843113 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4843113 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5333928 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5333928 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 352739883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 352739883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 353204181 # number of overall hits -system.cpu.dcache.overall_hits::total 353204181 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12867394 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12867394 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18868212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18868212 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2064415 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2064415 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1270711 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1270711 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 552556 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 552556 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1610515756 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1610515756 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 188193818 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 188193818 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164381838 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164381838 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 464944 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 464944 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 334105 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 334105 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4846159 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4846159 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5335614 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5335614 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 352909761 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 352909761 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 353374705 # number of overall hits +system.cpu.dcache.overall_hits::total 353374705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12874356 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12874356 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18866989 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18866989 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 226129752000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 226129752000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113756894884 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1113756894884 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30103485720 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 30103485720 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9429427500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 9429427500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 286500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 286500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1369990132604 # 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mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035366 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813697 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813697 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787065 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787065 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052994 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052994 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813523 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813523 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787530 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787530 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052610 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052610 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029746 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029746 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034851 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034851 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16903.456875 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16903.456875 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53003.208852 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53003.208852 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17049.364674 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17049.364674 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22581.531314 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22581.531314 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14896.774103 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14896.774103 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34812.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34812.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27277.293966 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27277.293966 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25722.074735 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25722.074735 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184782.307373 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184782.307373 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92376.073893 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92376.073893 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16962264 # number of replacements -system.cpu.icache.tags.tagsinuse 511.953467 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 447249112 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16962776 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.366505 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029735 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029735 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034839 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034839 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.155043 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.155043 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52757.649961 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52757.649961 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16887.385024 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16887.385024 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22527.617909 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22527.617909 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14864.208487 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14864.208487 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34687.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34687.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27001.105779 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27001.105779 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25463.106633 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25463.106633 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184781.476315 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184781.476315 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.658432 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.658432 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16948036 # number of replacements +system.cpu.icache.tags.tagsinuse 511.953468 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 447400638 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16948548 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.397579 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.953467 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.953468 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 481966186 # Number of tag accesses -system.cpu.icache.tags.data_accesses 481966186 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13418.359463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13418.359463 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 22063 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 482089545 # Number of tag accesses +system.cpu.icache.tags.data_accesses 482089545 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 447400638 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 447400638 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 447400638 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 447400638 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 447400638 # 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miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.038139 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038139 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13401.571429 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13401.571429 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13401.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13401.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13401.571429 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 22866 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1484 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1431 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.867251 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.979036 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16962264 # number of writebacks -system.cpu.icache.writebacks::total 16962264 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791074 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 791074 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 791074 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 791074 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 791074 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 791074 # 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number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 791363 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 791363 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16948772 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16948772 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16948772 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16948772 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16948772 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16948772 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.865899 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48531.996533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.143952 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005881 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101789 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.740539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 284 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61860 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 284 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1015 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5647 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55838 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959610 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 508088213 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 508088213 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1306072 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 309439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1615511 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012171 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804371500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290859000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.092878 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.092878 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093189 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093189 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437237 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437237 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.047479 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.047479 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.471162 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.471162 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061372 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061372 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115042.931725 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19076.732059 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19076.732059 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45625 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45625 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94799.663632 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94799.663632 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100703.051484 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100703.051484 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101451.929412 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101451.929412 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20684.448732 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20684.448732 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435286 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435286 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005662 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044125 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044125 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.468366 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.468366 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060127 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028138 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005662 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.140210 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060127 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 114665.332041 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19081.004205 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19081.004205 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94652.555491 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94652.555491 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100026.972418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100026.972418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102583.789605 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102583.789605 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20693.059030 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20693.059030 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127582.276698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99314.655654 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100026.972418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96535.444801 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96904.810849 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.469429 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.842324 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.439748 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.824137 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.675421 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.038077 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 62444778 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31707340 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2080 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2080 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.660583 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.026802 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 62411777 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31689071 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2067 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2067 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 2265526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28668320 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 2264077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28650207 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 12556358 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16962264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3627230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43361 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 12517715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16948036 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3623971 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43388 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43369 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3071629 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3071629 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16963000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1296315 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263830 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50930633 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41545171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 782892 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3048631 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 96307327 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171543584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467959922 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2514816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10453048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3652471370 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 3035082 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 141349672 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 35524572 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026277 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.159958 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3072817 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3072817 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16948772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9438927 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1295442 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1264567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50887949 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41543699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 787064 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3057144 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 96275856 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169722400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467531890 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2547184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10533752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3650335226 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2976479 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 139099568 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 35465406 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026221 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.159793 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 34591090 97.37% 97.37% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 933482 2.63% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 34535454 97.38% 97.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 929952 2.62% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35524572 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 59309730487 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35465406 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 59274617984 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1500879 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1490379 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25476019939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25454807175 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19475244130 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19473878402 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 468898263 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 469039231 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1742663628 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1741050209 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40311 # Transaction distribution -system.iobus.trans_dist::ReadResp 40311 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40296 # Transaction distribution +system.iobus.trans_dist::ReadResp 40296 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1618,11 +1625,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1637,12 +1644,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41893500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41892500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1664,75 +1671,75 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25183500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25201500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36499000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36497000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569168088 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569294464 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147710000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115471 # number of replacements -system.iocache.tags.tagsinuse 10.450359 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115456 # number of replacements +system.iocache.tags.tagsinuse 10.450363 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.527977 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.922382 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220499 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432649 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.528284 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.922079 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432630 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653148 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039767 # Number of tag accesses -system.iocache.tags.data_accesses 1039767 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039632 # Number of tag accesses +system.iocache.tags.data_accesses 1039632 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115490 # number of demand (read+write) misses -system.iocache.demand_misses::total 115530 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115475 # number of demand (read+write) misses +system.iocache.demand_misses::total 115515 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115490 # number of overall misses -system.iocache.overall_misses::total 115530 # number of overall misses +system.iocache.overall_misses::realview.ide 115475 # number of overall misses +system.iocache.overall_misses::total 115515 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1926111562 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1931197062 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1862993006 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1868078506 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13315765026 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13315765026 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13281113958 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13281113958 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15241876588 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15247313088 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15144106964 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15149543464 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15241876588 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15247313088 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15144106964 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15149543464 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115490 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115530 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115475 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115515 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115490 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115530 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115475 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115515 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1747,52 +1754,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218231.538862 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217894.286585 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 211439.451368 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 211130.030063 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124838.418079 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 124838.418079 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124513.556195 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 124513.556195 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131977.088964 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131147.846288 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131977.088964 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 47583 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 131146.195835 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131147.846288 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 44063 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.760266 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.567884 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115490 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115530 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115475 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115515 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115490 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115530 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115475 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115515 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1484811562 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1488047062 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1422443006 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1425678506 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7975666597 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7975666597 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7941073224 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7941073224 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9460478159 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9463914659 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9363516230 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9366952730 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9460478159 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9463914659 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9363516230 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9366952730 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1807,94 +1814,94 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168231.538862 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167894.286585 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 161439.451368 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 161130.030063 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74773.743690 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74773.743690 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74449.422711 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74449.422711 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 5147706 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2561464 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81086.955878 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81088.626845 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 5064341 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2518493 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2998 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54986 # Transaction distribution -system.membus.trans_dist::ReadResp 629139 # Transaction distribution +system.membus.trans_dist::ReadResp 595799 # Transaction distribution system.membus.trans_dist::WriteReq 33703 # Transaction distribution system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::WritebackDirty 2240512 # Transaction distribution -system.membus.trans_dist::CleanEvict 283345 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution +system.membus.trans_dist::WritebackDirty 2207309 # Transaction distribution +system.membus.trans_dist::CleanEvict 275154 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4609 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1342476 # Transaction distribution -system.membus.trans_dist::ReadExResp 1342476 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 574153 # Transaction distribution -system.membus.trans_dist::InvalidateReq 702122 # Transaction distribution +system.membus.trans_dist::ReadExReq 1336997 # Transaction distribution +system.membus.trans_dist::ReadExResp 1336997 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 540813 # Transaction distribution +system.membus.trans_dist::InvalidateReq 698937 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6871030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7000692 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237690 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237690 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7238382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6748871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6878533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237677 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237677 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7116210 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258984332 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 259154386 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7252416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 266406802 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2841 # Total snoops (count) -system.membus.snoopTraffic 181312 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2712040 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013104 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.113719 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254375884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254545938 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7253504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 261799442 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2809 # Total snoops (count) +system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2670049 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012702 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.111987 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2676502 98.69% 98.69% # Request fanout histogram -system.membus.snoop_fanout::1 35538 1.31% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2636133 98.73% 98.73% # Request fanout histogram +system.membus.snoop_fanout::1 33916 1.27% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2712040 # Request fanout histogram -system.membus.reqLayer0.occupancy 104012000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2670049 # Request fanout histogram +system.membus.reqLayer0.occupancy 104027000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5608000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5600000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14521699612 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14297533259 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10216122095 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10011316944 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44869281 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44794763 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1937,30 +1944,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558690384000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17162 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 17165 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |