diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt | 2815 |
1 files changed, 1415 insertions, 1400 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 591f883e9..df2086525 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.562170 # Number of seconds simulated -sim_ticks 51562169701000 # Number of ticks simulated -final_tick 51562169701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.291801 # Number of seconds simulated +sim_ticks 51291801227000 # Number of ticks simulated +final_tick 51291801227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82472 # Simulator instruction rate (inst/s) -host_op_rate 96938 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3850541751 # Simulator tick rate (ticks/s) -host_mem_usage 726532 # Number of bytes of host memory used -host_seconds 13390.89 # Real time elapsed on the host -sim_insts 1104366834 # Number of instructions simulated -sim_ops 1298086167 # Number of ops (including micro ops) simulated +host_inst_rate 104106 # Simulator instruction rate (inst/s) +host_op_rate 122333 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6261768882 # Simulator tick rate (ticks/s) +host_mem_usage 729608 # Number of bytes of host memory used +host_seconds 8191.26 # Real time elapsed on the host +sim_insts 852762944 # Number of instructions simulated +sim_ops 1002063356 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 657984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 557504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6634080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 148649160 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417792 # Number of bytes read from this memory -system.physmem.bytes_read::total 156916520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6634080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6634080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 139624832 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 238464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 234560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5768352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 75242504 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 407680 # Number of bytes read from this memory +system.physmem.bytes_read::total 81891560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5768352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5768352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69965824 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 139645412 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10281 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 119610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2322656 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6528 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2467786 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2181638 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69986404 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3726 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 106083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1175677 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6370 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1295521 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1093216 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2184211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 10812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 128662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2882911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3043249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 128662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 128662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2707893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2708292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2707893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 10812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 128662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2883310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5751541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2467786 # Number of read requests accepted -system.physmem.writeReqs 2184211 # Number of write requests accepted -system.physmem.readBursts 2467786 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2184211 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 157889856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48448 # Total number of bytes read from write queue -system.physmem.bytesWritten 139644224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 156916520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 139645412 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 757 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 155211 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 149005 # Per bank write bursts -system.physmem.perBankRdBursts::1 156339 # Per bank write bursts -system.physmem.perBankRdBursts::2 155955 # Per bank write bursts -system.physmem.perBankRdBursts::3 150628 # Per bank write bursts -system.physmem.perBankRdBursts::4 148084 # Per bank write bursts -system.physmem.perBankRdBursts::5 159303 # Per bank write bursts -system.physmem.perBankRdBursts::6 149188 # Per bank write bursts -system.physmem.perBankRdBursts::7 152515 # Per bank write bursts -system.physmem.perBankRdBursts::8 150862 # Per bank write bursts -system.physmem.perBankRdBursts::9 179370 # Per bank write bursts -system.physmem.perBankRdBursts::10 150320 # Per bank write bursts -system.physmem.perBankRdBursts::11 155893 # Per bank write bursts -system.physmem.perBankRdBursts::12 152080 # Per bank write bursts -system.physmem.perBankRdBursts::13 155961 # Per bank write bursts -system.physmem.perBankRdBursts::14 150556 # Per bank write bursts -system.physmem.perBankRdBursts::15 150970 # Per bank write bursts -system.physmem.perBankWrBursts::0 132106 # Per bank write bursts -system.physmem.perBankWrBursts::1 138501 # Per bank write bursts -system.physmem.perBankWrBursts::2 137398 # Per bank write bursts -system.physmem.perBankWrBursts::3 135602 # Per bank write bursts -system.physmem.perBankWrBursts::4 133392 # Per bank write bursts -system.physmem.perBankWrBursts::5 140433 # Per bank write bursts -system.physmem.perBankWrBursts::6 132940 # Per bank write bursts -system.physmem.perBankWrBursts::7 137025 # Per bank write bursts -system.physmem.perBankWrBursts::8 135656 # Per bank write bursts -system.physmem.perBankWrBursts::9 141181 # Per bank write bursts -system.physmem.perBankWrBursts::10 134433 # Per bank write bursts -system.physmem.perBankWrBursts::11 138339 # Per bank write bursts -system.physmem.perBankWrBursts::12 136301 # Per bank write bursts -system.physmem.perBankWrBursts::13 138853 # Per bank write bursts -system.physmem.perBankWrBursts::14 135122 # Per bank write bursts -system.physmem.perBankWrBursts::15 134659 # Per bank write bursts +system.physmem.num_writes::total 1095789 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1466950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1364074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1364475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1364074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1467351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2961057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1295521 # Number of read requests accepted +system.physmem.writeReqs 1095789 # Number of write requests accepted +system.physmem.readBursts 1295521 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1095789 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 82863680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue +system.physmem.bytesWritten 69985152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81891560 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 69986404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 141837 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 78118 # Per bank write bursts +system.physmem.perBankRdBursts::1 81473 # Per bank write bursts +system.physmem.perBankRdBursts::2 82762 # Per bank write bursts +system.physmem.perBankRdBursts::3 80112 # Per bank write bursts +system.physmem.perBankRdBursts::4 77452 # Per bank write bursts +system.physmem.perBankRdBursts::5 84131 # Per bank write bursts +system.physmem.perBankRdBursts::6 77443 # Per bank write bursts +system.physmem.perBankRdBursts::7 77113 # Per bank write bursts +system.physmem.perBankRdBursts::8 74240 # Per bank write bursts +system.physmem.perBankRdBursts::9 104872 # Per bank write bursts +system.physmem.perBankRdBursts::10 79788 # Per bank write bursts +system.physmem.perBankRdBursts::11 80502 # Per bank write bursts +system.physmem.perBankRdBursts::12 82162 # Per bank write bursts +system.physmem.perBankRdBursts::13 82091 # Per bank write bursts +system.physmem.perBankRdBursts::14 76266 # Per bank write bursts +system.physmem.perBankRdBursts::15 76220 # Per bank write bursts +system.physmem.perBankWrBursts::0 65460 # Per bank write bursts +system.physmem.perBankWrBursts::1 68510 # Per bank write bursts +system.physmem.perBankWrBursts::2 70351 # Per bank write bursts +system.physmem.perBankWrBursts::3 69772 # Per bank write bursts +system.physmem.perBankWrBursts::4 67735 # Per bank write bursts +system.physmem.perBankWrBursts::5 71090 # Per bank write bursts +system.physmem.perBankWrBursts::6 66311 # Per bank write bursts +system.physmem.perBankWrBursts::7 67773 # Per bank write bursts +system.physmem.perBankWrBursts::8 64800 # Per bank write bursts +system.physmem.perBankWrBursts::9 72411 # Per bank write bursts +system.physmem.perBankWrBursts::10 67462 # Per bank write bursts +system.physmem.perBankWrBursts::11 69064 # Per bank write bursts +system.physmem.perBankWrBursts::12 70238 # Per bank write bursts +system.physmem.perBankWrBursts::13 69848 # Per bank write bursts +system.physmem.perBankWrBursts::14 66451 # Per bank write bursts +system.physmem.perBankWrBursts::15 66242 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 21 # Number of times write queue was full causing retry -system.physmem.totGap 51562168447500 # Total gap between requests +system.physmem.numWrRetry 28 # Number of times write queue was full causing retry +system.physmem.totGap 51291799925500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2446501 # Read request sizes (log2) +system.physmem.readPktSize::6 1274236 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2181638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1276105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 831313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 193469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 160610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1093216 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 662611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 153233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 129247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 143 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,161 +159,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 23029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 68337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 107857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 119474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 131451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 131860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 135328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 136231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 139007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 140497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 136343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 166652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 162914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 137438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 145049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 131294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 938073 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.175418 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.850858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.830774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 348981 37.20% 37.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 217922 23.23% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89990 9.59% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51985 5.54% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 41514 4.43% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 28050 2.99% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24686 2.63% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20558 2.19% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 114387 12.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 938073 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 129462 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 19.055908 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 183.344638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 129459 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 12367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 46525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 65687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 66815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 69682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 68432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 68922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 68990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 86951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 67526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 71071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 505036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.648619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.485841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.471265 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 200174 39.64% 39.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 119366 23.64% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 47641 9.43% 72.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24555 4.86% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19234 3.81% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12076 2.39% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11328 2.24% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8283 1.64% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62379 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 505036 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62413 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.744284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 264.086390 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 62410 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 129462 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 129462 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.853911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.595936 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.789289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 125866 97.22% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1229 0.95% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 433 0.33% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 197 0.15% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 330 0.25% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 524 0.40% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 121 0.09% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 39 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.01% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 43 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 23 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 425 0.33% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 42 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 37 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 19 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 35 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 129462 # Writes before turning the bus around for reads -system.physmem.totQLat 61876185756 # Total ticks spent queuing -system.physmem.totMemAccLat 108132979506 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 12335145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25081.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 62413 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.520677 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.965036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.067360 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 59523 95.37% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 900 1.44% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 59 0.09% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 320 0.51% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 34 0.05% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 343 0.55% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 222 0.36% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.03% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 51 0.08% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 131 0.21% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.05% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 40 0.06% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 504 0.81% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 37 0.06% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 23 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 123 0.20% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 24 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62413 # Writes before turning the bus around for reads +system.physmem.totQLat 33295532684 # Total ticks spent queuing +system.physmem.totMemAccLat 57572001434 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6473725000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25715.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43831.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.06 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44465.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.36 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing -system.physmem.readRowHits 2056722 # Number of row buffer hits during reads -system.physmem.writeRowHits 1654173 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.81 # Row buffer hit rate for writes -system.physmem.avgGap 11083878.27 # Average gap between requests -system.physmem.pageHitRate 79.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3550765680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1937421750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 9523885800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 7046332560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1313489115900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29785116936750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34488454558920 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.871313 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49548907375208 # Time in different power states -system.physmem_0.memoryStateTime::REF 1721774080000 # Time in different power states +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing +system.physmem.readRowHits 1061078 # Number of row buffer hits during reads +system.physmem.writeRowHits 822147 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.18 # Row buffer hit rate for writes +system.physmem.avgGap 21449247.45 # Average gap between requests +system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1917609120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1046314500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4981072200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3544572960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1242137154015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29685484530000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34289242115835 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.513169 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49384250074028 # Time in different power states +system.physmem_0.memoryStateTime::REF 1712745840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 291487862292 # Time in different power states +system.physmem_0.memoryStateTime::ACT 194804679972 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3541066200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1932129375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 9718893600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 7092645120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3367790100480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1316895447015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29782128927000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34489099208790 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.883816 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49543906734220 # Time in different power states -system.physmem_1.memoryStateTime::REF 1721774080000 # Time in different power states +system.physmem_1.actEnergy 1900463040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1036959000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5117892000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3541423680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1242496599435 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29685169227000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34289393427195 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.516119 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49383714226365 # Time in different power states +system.physmem_1.memoryStateTime::REF 1712745840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 296486485780 # Time in different power states +system.physmem_1.memoryStateTime::ACT 195340926635 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -325,27 +327,27 @@ system.realview.nvmem.num_reads::cpu.data 5 # N system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 288825634 # Number of BP lookups -system.cpu.branchPred.condPredicted 198097109 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13566789 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 207338959 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136913226 # Number of BTB hits +system.cpu.branchPred.lookups 225483777 # Number of BP lookups +system.cpu.branchPred.condPredicted 150731207 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12226483 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159238670 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104065621 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.033526 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37451224 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 402112 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.351978 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30986634 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344493 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -376,84 +378,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 1430156 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1430156 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30793 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273791 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 677378 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 752778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2375.228819 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 15567.513073 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 746726 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4359 0.58% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 685 0.09% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 394 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 311 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 120 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 171 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 752778 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 802636 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25959.455469 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21570.790504 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 17698.477360 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 783977 97.68% 97.68% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 16023 2.00% 99.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1555 0.19% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 316 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 129 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 37 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 22 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 802636 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1044763922448 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.739319 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.520240 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1040800473448 99.62% 99.62% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2579873000 0.25% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 637994000 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 271834500 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 201274500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 132884500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 46819000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 89469000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3255500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 45000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1044763922448 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 273792 89.89% 89.89% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 30793 10.11% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 304585 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1430156 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 951545 # Table walker walks requested +system.cpu.dtb.walker.walksLong 951545 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16343 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155686 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 435595 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 515950 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2268.523113 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 15037.920153 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 512394 99.31% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1973 0.38% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 1076 0.21% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 204 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 151 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 58 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 515950 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 484012 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23030.337058 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17887.395943 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 21586.118666 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 472338 97.59% 97.59% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7777 1.61% 99.19% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2811 0.58% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 207 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 566 0.12% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 146 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 21 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 484012 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 787280100836 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.726034 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.521586 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 785046223336 99.72% 99.72% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1194986000 0.15% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 471189500 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 205721500 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 152825500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 122394500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 28887000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 55269000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2572500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 32000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 787280100836 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 155687 90.50% 90.50% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16343 9.50% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 172030 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951545 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1430156 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304585 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172030 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304585 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1734741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172030 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1123575 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 217117628 # DTB read hits -system.cpu.dtb.read_misses 1002788 # DTB read misses -system.cpu.dtb.write_hits 192115888 # DTB write hits -system.cpu.dtb.write_misses 427368 # DTB write misses -system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 170217039 # DTB read hits +system.cpu.dtb.read_misses 674912 # DTB read misses +system.cpu.dtb.write_hits 148367148 # DTB write hits +system.cpu.dtb.write_misses 276633 # DTB write misses +system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 87986 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15675 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 39773 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72532 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10694 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 85972 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 218120416 # DTB read accesses -system.cpu.dtb.write_accesses 192543256 # DTB write accesses +system.cpu.dtb.perms_faults 70020 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 170891951 # DTB read accesses +system.cpu.dtb.write_accesses 148643781 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 409233516 # DTB hits -system.cpu.dtb.misses 1430156 # DTB misses -system.cpu.dtb.accesses 410663672 # DTB accesses +system.cpu.dtb.hits 318584187 # DTB hits +system.cpu.dtb.misses 951545 # DTB misses +system.cpu.dtb.accesses 319535732 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,877 +488,881 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 177415 # Table walker walks requested -system.cpu.itb.walker.walksLong 177415 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1441 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 130680 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 19804 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 157611 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1499.045117 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 10189.386950 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 155888 98.91% 98.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 579 0.37% 99.27% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 739 0.47% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 292 0.19% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 35 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 38 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 157611 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 151925 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29463.087050 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24547.770920 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 22228.579404 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 146250 96.26% 96.26% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 4800 3.16% 99.42% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 534 0.35% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 196 0.13% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 80 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 44 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 15 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 151925 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 920206753364 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.948994 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.220270 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 46987798652 5.11% 5.11% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 873167595712 94.89% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 50573500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 783500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walks 161585 # Table walker walks requested +system.cpu.itb.walker.walksLong 161585 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1428 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121821 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17557 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144028 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1321.829783 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9926.807145 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142959 99.26% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 572 0.40% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 68 0.05% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 87 0.06% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 28 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144028 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140806 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29194.196270 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24049.387193 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24612.430029 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137481 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 705 0.50% 98.14% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 2241 1.59% 99.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 147 0.10% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 149 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 40 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 28 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 140806 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 671312841344 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944614 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.229094 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37236199060 5.55% 5.55% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 634022806284 94.45% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 53008500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 825500 0.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 920206753364 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 130680 98.91% 98.91% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1441 1.09% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 132121 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 671312841344 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121821 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1428 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123249 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177415 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 177415 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161585 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161585 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 132121 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 132121 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 309536 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 461294711 # ITB inst hits -system.cpu.itb.inst_misses 177415 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123249 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123249 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 284834 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 358536824 # ITB inst hits +system.cpu.itb.inst_misses 161585 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63203 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 62159 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 39773 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53279 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 458083 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 371261 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 461472126 # ITB inst accesses -system.cpu.itb.hits 461294711 # DTB hits -system.cpu.itb.misses 177415 # DTB misses -system.cpu.itb.accesses 461472126 # DTB accesses -system.cpu.numCycles 2141240199 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 358698409 # ITB inst accesses +system.cpu.itb.hits 358536824 # DTB hits +system.cpu.itb.misses 161585 # DTB misses +system.cpu.itb.accesses 358698409 # DTB accesses +system.cpu.numCycles 1657263364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 785638694 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1289733601 # Number of instructions fetch has processed -system.cpu.fetch.Branches 288825634 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174364450 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1267374465 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29210356 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4418623 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 12152128 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1217886 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 633 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 460817774 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6728045 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 53516 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2085435848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.725171 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.139838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 646687588 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1006138467 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225483777 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135052255 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 923834525 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26119142 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3836248 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9382773 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1057490 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1024 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 358148752 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6114742 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1597889466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.737838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.145066 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1366680941 65.53% 65.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 278589155 13.36% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 86788366 4.16% 83.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 353377386 16.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1037892560 64.95% 64.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215037687 13.46% 78.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70931005 4.44% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274028214 17.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2085435848 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.134887 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.602330 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 612239538 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 852574124 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 529946172 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80118083 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10557931 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41219534 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4107385 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1403247413 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32566835 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10557931 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 674962554 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 85247440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 550746700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 547461697 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 216459526 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1379612307 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 7971383 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7360618 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 963827 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1074082 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 133209723 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22971 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1329803577 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2195861380 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1637517470 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1437183 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1251935276 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 77868298 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43546894 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39087703 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 166786807 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 221659276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 196613901 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12565776 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11015266 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1326936815 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 43849103 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1356961205 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4098709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 72699747 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41430931 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 372473 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2085435848 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.650685 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.914510 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1597889466 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136058 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.607108 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 525509961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577968560 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 434692108 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50467392 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9251445 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33765808 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3868232 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1090395947 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29075856 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9251445 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 570461027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 71248505 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 374528556 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 440187114 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 132212819 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1070563825 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6799460 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5139795 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 352432 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 543797 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 80592393 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20524 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1018210604 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1650018567 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1266293182 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1471142 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 952425146 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65785455 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27183969 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23507268 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103615043 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174251996 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 151954482 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9963478 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9058683 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1035258502 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27485968 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1050977707 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3302134 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60681110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33832223 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315804 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1597889466 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.657729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.917270 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1239320860 59.43% 59.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 449936886 21.58% 81.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 291017288 13.95% 94.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 95682212 4.59% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9449903 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 28699 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 947140839 59.27% 59.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 336074269 21.03% 80.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 235675867 14.75% 95.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72461429 4.53% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6517893 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2085435848 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1597889466 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73477453 34.17% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90486 0.04% 34.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26768 0.01% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 385 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57876005 26.91% 61.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83594438 38.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58047509 35.02% 35.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99216 0.06% 35.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26736 0.02% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 621 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44536420 26.87% 61.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63031836 38.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 937288786 69.07% 69.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2936989 0.22% 69.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129444 0.01% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 114407 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 221949724 16.36% 85.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194541406 14.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 723805798 68.87% 68.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2543227 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122751 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120969 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174113455 16.57% 85.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150271445 14.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1356961205 # Type of FU issued -system.cpu.iq.rate 0.633727 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215065535 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.158491 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5016097714 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1442740685 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1335189379 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2424787 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 927446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 888349 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1570502436 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1524273 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5709357 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1050977707 # Type of FU issued +system.cpu.iq.rate 0.634165 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165742338 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157703 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3866409671 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1122621449 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1032956403 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2479680 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 948183 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 910717 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1215162069 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1557965 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4345381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 16902439 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24350 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 184211 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8196884 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13856832 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14557 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 145376 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6348158 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3577769 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1870440 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2556112 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1569383 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10557931 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12374030 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7706525 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1371058602 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9251445 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7205871 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9780746 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1062967049 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 221659276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 196613901 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 38550114 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178028 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7343410 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 184211 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4239042 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5703306 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 9942348 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1343677933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 217120223 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11882036 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174251996 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 151954482 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23081360 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59250 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9646548 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 145376 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3669738 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5114532 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8784270 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1039771083 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170205641 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10266382 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 272684 # number of nop insts executed -system.cpu.iew.exec_refs 409245203 # number of memory reference insts executed -system.cpu.iew.exec_branches 255119365 # Number of branches executed -system.cpu.iew.exec_stores 192124980 # Number of stores executed -system.cpu.iew.exec_rate 0.627523 # Inst execution rate -system.cpu.iew.wb_sent 1337102879 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1336077728 # cumulative count of insts written-back -system.cpu.iew.wb_producers 573421420 # num instructions producing a value -system.cpu.iew.wb_consumers 940568778 # num instructions consuming a value +system.cpu.iew.exec_nop 222579 # number of nop insts executed +system.cpu.iew.exec_refs 318568485 # number of memory reference insts executed +system.cpu.iew.exec_branches 197267293 # Number of branches executed +system.cpu.iew.exec_stores 148362844 # Number of stores executed +system.cpu.iew.exec_rate 0.627402 # Inst execution rate +system.cpu.iew.wb_sent 1034679114 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1033867120 # cumulative count of insts written-back +system.cpu.iew.wb_producers 440084197 # num instructions producing a value +system.cpu.iew.wb_consumers 711913770 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.623974 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.609654 # average fanout of values written-back +system.cpu.iew.wb_rate 0.623840 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618171 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 62140410 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 43476630 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9519542 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2071346493 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.626687 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.267080 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51558670 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27170164 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8418357 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1585876661 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.631867 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.268709 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1395640231 67.38% 67.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 393909449 19.02% 86.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150461425 7.26% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44316735 2.14% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 35977476 1.74% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18232281 0.88% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10892931 0.53% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5452952 0.26% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16463013 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1071299476 67.55% 67.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 289640402 18.26% 85.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120963875 7.63% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36621114 2.31% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28592038 1.80% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14082122 0.89% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8687118 0.55% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4193736 0.26% 99.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11796780 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2071346493 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1104366834 # Number of instructions committed -system.cpu.commit.committedOps 1298086167 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1585876661 # Number of insts commited each cycle +system.cpu.commit.committedInsts 852762944 # Number of instructions committed +system.cpu.commit.committedOps 1002063356 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 393173853 # Number of memory references committed -system.cpu.commit.loads 204756836 # Number of loads committed -system.cpu.commit.membars 9104821 # Number of memory barriers committed -system.cpu.commit.branches 246834909 # Number of branches committed -system.cpu.commit.fp_insts 874964 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1186447841 # Number of committed integer instructions. -system.cpu.commit.function_calls 30876862 # Number of function calls committed. +system.cpu.commit.refs 306001487 # Number of memory references committed +system.cpu.commit.loads 160395163 # Number of loads committed +system.cpu.commit.membars 6971183 # Number of memory barriers committed +system.cpu.commit.branches 190333133 # Number of branches committed +system.cpu.commit.fp_insts 897329 # Number of committed floating point instructions. +system.cpu.commit.int_insts 920660333 # Number of committed integer instructions. +system.cpu.commit.function_calls 25420821 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 902159630 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2542825 0.20% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 103949 0.01% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105868 0.01% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 204756836 15.77% 85.49% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 188417017 14.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 693695163 69.23% 69.23% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2156692 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98172 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111800 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 160395163 16.01% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145606324 14.53% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1298086167 # Class of committed instruction -system.cpu.commit.bw_lim_events 16463013 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3405665880 # The number of ROB reads -system.cpu.rob.rob_writes 2734432791 # The number of ROB writes -system.cpu.timesIdled 9009507 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 55804351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100983102115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1104366834 # Number of Instructions Simulated -system.cpu.committedOps 1298086167 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.938885 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.938885 # CPI: Total CPI of All Threads -system.cpu.ipc 0.515760 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.515760 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1596434625 # number of integer regfile reads -system.cpu.int_regfile_writes 940526203 # number of integer regfile writes -system.cpu.fp_regfile_reads 1424965 # number of floating regfile reads -system.cpu.fp_regfile_writes 765828 # number of floating regfile writes -system.cpu.cc_regfile_reads 311708448 # number of cc regfile reads -system.cpu.cc_regfile_writes 312593649 # number of cc regfile writes -system.cpu.misc_regfile_reads 3410532874 # number of misc regfile reads -system.cpu.misc_regfile_writes 44362921 # number of misc regfile writes -system.cpu.dcache.tags.replacements 13614186 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983787 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 360288791 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13614698 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.463223 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1642601500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983787 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 1002063356 # Class of committed instruction +system.cpu.commit.bw_lim_events 11796780 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2620126782 # The number of ROB reads +system.cpu.rob.rob_writes 2119163855 # The number of ROB writes +system.cpu.timesIdled 8145872 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59373898 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100926342082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 852762944 # Number of Instructions Simulated +system.cpu.committedOps 1002063356 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.943405 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.943405 # CPI: Total CPI of All Threads +system.cpu.ipc 0.514561 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.514561 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1230978083 # number of integer regfile reads +system.cpu.int_regfile_writes 734956592 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462594 # number of floating regfile reads +system.cpu.fp_regfile_writes 785720 # number of floating regfile writes +system.cpu.cc_regfile_reads 226481409 # number of cc regfile reads +system.cpu.cc_regfile_writes 227147205 # number of cc regfile writes +system.cpu.misc_regfile_reads 2590605655 # number of misc regfile reads +system.cpu.misc_regfile_writes 27218545 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9745793 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972785 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 284478201 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9746305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.188313 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 2742937500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.972785 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1595334423 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1595334423 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 186468319 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 186468319 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 162903680 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 162903680 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 463393 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 463393 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4787397 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4787397 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5271269 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5271269 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 349371999 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 349371999 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 349835392 # number of overall hits -system.cpu.dcache.overall_hits::total 349835392 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12723000 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12723000 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18625078 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18625078 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2035956 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2035956 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1270469 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1270469 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 547335 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 547335 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 31348078 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 31348078 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 33384034 # number of overall misses -system.cpu.dcache.overall_misses::total 33384034 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 203343916000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 203343916000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 979374659621 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 979374659621 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 74427778402 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 74427778402 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8800618500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 8800618500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 251000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1182718575621 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1182718575621 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1182718575621 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1182718575621 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 199191319 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 199191319 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 181528758 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 181528758 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2499349 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2499349 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5334732 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5334732 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5271276 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5271276 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 380720077 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 380720077 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 383219426 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 383219426 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063873 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.063873 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102601 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.102601 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.814595 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.814595 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791819 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791819 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102598 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102598 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1242843351 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1242843351 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147746281 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147746281 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128943597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128943597 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 378897 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 378897 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 324717 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 324717 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3321055 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3321055 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3719262 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3719262 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 276689878 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 276689878 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 277068775 # number of overall hits +system.cpu.dcache.overall_hits::total 277068775 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9599758 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9599758 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11373760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11373760 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1183380 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1183380 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1233189 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1233189 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 450358 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 450358 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20973518 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20973518 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22156898 # number of overall misses +system.cpu.dcache.overall_misses::total 22156898 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 170465804000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 170465804000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 459745522921 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 459745522921 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 90424230789 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 90424230789 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6989283500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6989283500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276500 # 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number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165573828380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165573828380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 189614190380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 189614190380 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829312500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829312500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5836671467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5836671467 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11665983967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11665983967 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753126 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753126 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787163 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787163 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060989 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060989 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031648 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031648 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15592.205017 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15592.205017 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46933.898739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46933.898739 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15953.398196 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.398196 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 57686.049849 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 57686.049849 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14358.598185 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14358.598185 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34857.142857 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25156.879429 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25156.879429 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23616.995737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23616.995737 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173011.293482 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.293482 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 169369.001780 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169369.001780 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171189.850389 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171189.850389 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024044 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024044 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027851 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027851 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16685.436929 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16685.436929 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39517.127269 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39517.127269 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20432.216463 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20432.216463 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72409.561396 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72409.561396 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14196.612410 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14196.612410 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54300 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54300 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23134.060911 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23134.060911 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22752.603440 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22752.603440 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173089.628244 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173089.628244 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173215.558731 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173215.558731 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173152.610310 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 173152.610310 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 16756542 # number of replacements -system.cpu.icache.tags.tagsinuse 511.945135 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 443237235 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16757054 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.450785 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 17214303500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.945135 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999893 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15058288 # number of replacements +system.cpu.icache.tags.tagsinuse 511.916796 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 342301291 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15058800 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.730981 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 24732660500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.916796 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999837 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999837 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 477553750 # Number of tag accesses -system.cpu.icache.tags.data_accesses 477553750 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 443237235 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 443237235 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 443237235 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 443237235 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 443237235 # number of overall hits -system.cpu.icache.overall_hits::total 443237235 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17559241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17559241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17559241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17559241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17559241 # number of overall misses -system.cpu.icache.overall_misses::total 17559241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 232141013891 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 232141013891 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 232141013891 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 232141013891 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 232141013891 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 232141013891 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 460796476 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 460796476 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 460796476 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 460796476 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 460796476 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 460796476 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038106 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.038106 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.038106 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.038106 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.038106 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.038106 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13220.446937 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13220.446937 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13220.446937 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13220.446937 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13220.446937 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 15959 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 373186476 # Number of tag accesses +system.cpu.icache.tags.data_accesses 373186476 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 342301291 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 342301291 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 342301291 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 342301291 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 342301291 # number of overall hits +system.cpu.icache.overall_hits::total 342301291 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15826164 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15826164 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15826164 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15826164 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15826164 # number of overall misses +system.cpu.icache.overall_misses::total 15826164 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 213799135380 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 213799135380 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 213799135380 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 213799135380 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 213799135380 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 213799135380 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 358127455 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 358127455 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 358127455 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 358127455 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 358127455 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 358127455 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044191 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044191 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044191 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044191 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044191 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044191 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.220262 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13509.220262 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.220262 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13509.220262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.220262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13509.220262 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 22973 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1225 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1424 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.027755 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.132725 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 801966 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 801966 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 801966 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 801966 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 801966 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 801966 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16757275 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16757275 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16757275 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16757275 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16757275 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16757275 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 767143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 767143 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 767143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 767143 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 767143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 767143 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15059021 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15059021 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15059021 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15059021 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15059021 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15059021 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208567956898 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 208567956898 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208567956898 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 208567956898 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208567956898 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 208567956898 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1594412000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1594412000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1594412000 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12446.412492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12446.412492 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74872.599202 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74872.599202 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74872.599202 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191438172888 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191438172888 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191438172888 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191438172888 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191438172888 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191438172888 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684494000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684494000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684494000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 2684494000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042049 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042049 # 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average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129275.526257 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145142.032882 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145142.032882 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160589.390700 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142372.364615 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161581.908832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161581.908832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161085.782349 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149672.377043 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2244083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28317103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 12480720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 20347986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 60667 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 60674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3036433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3036433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16757275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9323830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1369962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263298 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50310988 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41099763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 807461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3043712 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 95261924 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1072793136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1449869810 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2707560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10589056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2535959562 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 3104722 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 65657900 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.072586 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259455 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 50352882 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25547569 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadReq 1630756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23229377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8639097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 17453404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1981151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1981151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15059021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6547690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1332988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226324 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45216170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29460715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1932656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 77338263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964104688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1028452958 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2398344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6286416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2001242406 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1898399 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 52724879 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.013444 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.115165 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 60892075 92.74% 92.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 4765825 7.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 52016056 98.66% 98.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 708823 1.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 65657900 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 41856500497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 52724879 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 33221521499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1449383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25164199957 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22617176752 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19241199390 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13467693225 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 469526277 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 429237366 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1720822991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1147199772 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 40298 # Transaction distribution system.iobus.trans_dist::ReadResp 40298 # Transaction distribution @@ -1622,7 +1637,7 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 568892559 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565777121 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) @@ -1633,16 +1648,16 @@ system.iobus.respLayer3.utilization 0.0 # La system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.449705 # Cycle average of tags in use +system.iocache.tags.tagsinuse 10.417924 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13095311633000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.528028 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.921676 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220502 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432605 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653107 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13103107119000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.546641 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.871282 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221665 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429455 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651120 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1661,19 +1676,19 @@ system.iocache.demand_misses::total 8853 # nu system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8813 # number of overall misses system.iocache.overall_misses::total 8853 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1615020135 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1620089135 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ethernet 5101000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1670573105 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1675674105 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12610143424 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12610143424 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1615020135 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1620440135 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1615020135 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1620440135 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13828326016 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13828326016 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5452000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1670573105 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1676025105 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5452000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1670573105 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1676025105 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) @@ -1700,24 +1715,24 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183254.298763 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183060.919209 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137864.864865 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189557.824237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189341.706780 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118223.050176 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118223.050176 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183038.533266 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183254.298763 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183038.533266 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31319 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129643.797495 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129643.797495 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 136300 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 189557.824237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 189317.192477 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 136300 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 189557.824237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 189317.192477 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34546 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3397 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.276955 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.169561 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1736,19 +1751,19 @@ system.iocache.demand_mshr_misses::total 8853 # nu system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174370135 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1177589135 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3251000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229923105 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1233174105 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7276943424 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7276943424 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1174370135 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1177790135 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1174370135 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1177790135 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8495126016 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8495126016 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3452000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1229923105 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1233375105 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3452000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1229923105 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1233375105 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1762,73 +1777,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133254.298763 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133060.919209 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87864.864865 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139557.824237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139341.706780 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68223.050176 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68223.050176 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133254.298763 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133038.533266 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79643.797495 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79643.797495 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86300 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 139557.824237 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139317.192477 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86300 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 139557.824237 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139317.192477 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54987 # Transaction distribution -system.membus.trans_dist::ReadResp 601962 # Transaction distribution -system.membus.trans_dist::WriteReq 33703 # Transaction distribution -system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::Writeback 2181638 # Transaction distribution -system.membus.trans_dist::CleanEvict 277040 # Transaction distribution -system.membus.trans_dist::UpgradeReq 48552 # Transaction distribution +system.membus.trans_dist::ReadReq 54973 # Transaction distribution +system.membus.trans_dist::ReadResp 419838 # Transaction distribution +system.membus.trans_dist::WriteReq 33696 # Transaction distribution +system.membus.trans_dist::WriteResp 33696 # Transaction distribution +system.membus.trans_dist::Writeback 1093216 # Transaction distribution +system.membus.trans_dist::CleanEvict 195829 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35178 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 48555 # Transaction distribution -system.membus.trans_dist::ReadExReq 1902507 # Transaction distribution -system.membus.trans_dist::ReadExResp 1902507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 546975 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35181 # Transaction distribution +system.membus.trans_dist::ReadExReq 912510 # Transaction distribution +system.membus.trans_dist::ReadExResp 912510 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 364865 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7371150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7500814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341657 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341657 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7842471 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3830691 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3960313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341363 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341363 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4301676 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 289319820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 289489890 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7242112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 296732002 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2989 # Total snoops (count) -system.membus.snoop_fanout::samples 5154600 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144645964 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144815950 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7232000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 152047950 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3147 # Total snoops (count) +system.membus.snoop_fanout::samples 2799608 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5154600 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2799608 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 5154600 # Request fanout histogram -system.membus.reqLayer0.occupancy 104456000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2799608 # Request fanout histogram +system.membus.reqLayer0.occupancy 104476500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5495500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5464500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14230820482 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7417701934 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 13100845399 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6905958013 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228852771 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228360981 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1839,11 +1854,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1883,6 +1898,6 @@ system.realview.realview_io.osc_smb.clock 20000 # C system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 20008 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 19016 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |