diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 7f31e0119..3c37d97cb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.327140 # Nu sim_ticks 51327139864000 # Number of ticks simulated final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184861 # Simulator instruction rate (inst/s) -host_op_rate 217215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11186950873 # Simulator tick rate (ticks/s) -host_mem_usage 729056 # Number of bytes of host memory used -host_seconds 4588.13 # Real time elapsed on the host +host_inst_rate 138298 # Simulator instruction rate (inst/s) +host_op_rate 162502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8369157499 # Simulator tick rate (ticks/s) +host_mem_usage 688884 # Number of bytes of host memory used +host_seconds 6132.89 # Real time elapsed on the host sim_insts 848164321 # Number of instructions simulated sim_ops 996610207 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -465,7 +465,7 @@ system.cpu.dtb.flush_tlb 10 # Nu system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 72038 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -574,7 +574,7 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52849 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |