diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt | 70 |
1 files changed, 29 insertions, 41 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index a24da51f0..dd0bedb40 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1780456 # Simulator instruction rate (inst/s) -host_op_rate 2092420 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92650032032 # Simulator tick rate (ticks/s) -host_mem_usage 679092 # Number of bytes of host memory used -host_seconds 551.66 # Real time elapsed on the host +host_inst_rate 1195823 # Simulator instruction rate (inst/s) +host_op_rate 1405350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62227318824 # Simulator tick rate (ticks/s) +host_mem_usage 678332 # Number of bytes of host memory used +host_seconds 821.36 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -300,10 +300,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330184303 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330184303 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330608768 # number of overall hits -system.cpu.dcache.overall_hits::total 330608768 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits +system.cpu.dcache.overall_hits::total 330945053 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses @@ -316,10 +316,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8571515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8571515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10157717 # number of overall misses -system.cpu.dcache.overall_misses::total 10157717 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses +system.cpu.dcache.overall_misses::total 11404487 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses) @@ -332,10 +332,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 338755818 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 338755818 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 340766485 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 340766485 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses @@ -348,21 +348,18 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025303 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029808 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks system.cpu.dcache.writebacks::total 8917390 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 14265253 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. @@ -409,11 +406,8 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks system.cpu.icache.writebacks::total 14265253 # number of writebacks -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1725806 # number of replacements system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. @@ -555,11 +549,8 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks system.cpu.l2cache.writebacks::total 1507080 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -670,11 +661,11 @@ system.iocache.WriteReq_misses::total 3 # nu system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses -system.iocache.demand_misses::total 8853 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses +system.iocache.demand_misses::total 115517 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8813 # number of overall misses -system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.overall_misses::realview.ide 115477 # number of overall misses +system.iocache.overall_misses::total 115517 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) @@ -683,11 +674,11 @@ system.iocache.WriteReq_accesses::total 3 # nu system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -707,11 +698,8 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76679 # Transaction distribution system.membus.trans_dist::ReadResp 524946 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution |