diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual')
5 files changed, 1613 insertions, 1254 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini index 7268469a8..4ef1d1b22 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -122,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -168,8 +190,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -192,9 +219,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -208,9 +240,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -246,8 +287,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -305,9 +351,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -321,9 +372,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -334,13 +390,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -358,6 +418,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -368,6 +429,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -384,8 +449,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -393,9 +463,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -423,6 +499,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=1 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -441,6 +518,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -462,13 +543,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -487,8 +572,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -511,9 +601,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -527,9 +622,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -540,13 +640,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -565,8 +669,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -624,9 +733,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -640,9 +754,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -653,13 +772,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -677,6 +800,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -687,6 +811,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -703,8 +831,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -712,9 +845,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -759,9 +898,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -775,13 +919,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -800,8 +948,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -812,13 +965,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -837,20 +994,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -862,11 +1030,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -877,16 +1050,28 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=2147483648:2415919103 port=system.membus.master[5] @@ -901,10 +1086,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -985,14 +1175,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1001,13 +1196,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1017,6 +1217,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1087,10 +1288,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1170,17 +1376,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1206,12 +1417,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1219,14 +1436,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1312,14 +1534,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1328,13 +1555,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1343,13 +1575,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1357,11 +1594,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1375,11 +1617,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1393,19 +1640,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1451,14 +1704,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1467,11 +1735,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1481,21 +1754,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1505,12 +1788,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1519,10 +1807,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1532,12 +1825,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1547,26 +1845,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1575,10 +1883,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1586,10 +1899,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1597,21 +1915,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1625,11 +1953,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1640,11 +1973,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1652,10 +1990,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -1671,9 +2014,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr index a78b01f0e..ec34e9426 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simerr @@ -2,9 +2,12 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout index 722fe47ae..520d50f95 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 13:36:23 -gem5 executing on e104799-lin, pid 11118 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:49:27 +gem5 executing on e108600-lin, pid 23294 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47216814145000 because m5_exit instruction encountered +Exiting @ tick 47296281748500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 613ee48d7..99716a632 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.216815 # Number of seconds simulated -sim_ticks 47216814802000 # Number of ticks simulated -final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.296282 # Number of seconds simulated +sim_ticks 47296281748500 # Number of ticks simulated +final_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 917426 # Simulator instruction rate (inst/s) -host_op_rate 1079212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44335256452 # Simulator tick rate (ticks/s) -host_mem_usage 692848 # Number of bytes of host memory used -host_seconds 1064.99 # Real time elapsed on the host -sim_insts 977053655 # Number of instructions simulated -sim_ops 1149354696 # Number of ops (including micro ops) simulated +host_inst_rate 717114 # Simulator instruction rate (inst/s) +host_op_rate 843581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34713303168 # Simulator tick rate (ticks/s) +host_mem_usage 688104 # Number of bytes of host memory used +host_seconds 1362.48 # Real time elapsed on the host +sim_insts 977055082 # Number of instructions simulated +sim_ops 1149364510 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 34948936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 222656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2668232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38725552 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417728 # Number of bytes read from this memory -system.physmem.bytes_read::total 81375732 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3895860 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2668232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6564092 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101375872 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 151424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 124352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3875572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35081800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 222336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 221312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2647048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38747248 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 401984 # Number of bytes read from this memory +system.physmem.bytes_read::total 81473076 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3875572 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2647048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6522620 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 101454976 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 101396456 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2349 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 101280 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 546090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41798 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 605103 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1312039 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1583998 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 101475560 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2366 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 100963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 548166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3474 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 605442 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6281 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1313560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1585234 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1586572 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 740180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 820164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1723448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 139020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2147029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1587808 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 81942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 741745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 819245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1722611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 81942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55967 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 137910 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2145094 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2147465 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2147029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 740616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.physmem.bw_write::total 2145529 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2145094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 81942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 742181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 819245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3868140 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -100,9 +100,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -110,7 +110,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -140,47 +140,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 124420 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 124420 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 124420 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 125159 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 125159 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 125159 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 125159 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 125159 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95857 89.92% 89.92% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10751 10.08% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106608 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 96412 89.79% 89.79% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10963 10.21% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107375 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125159 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124420 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106608 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125159 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107375 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106608 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 231028 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107375 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 232534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91801710 # DTB read hits -system.cpu0.dtb.read_misses 88193 # DTB read misses -system.cpu0.dtb.write_hits 84999619 # DTB write hits -system.cpu0.dtb.write_misses 36227 # DTB write misses +system.cpu0.dtb.read_hits 92471463 # DTB read hits +system.cpu0.dtb.read_misses 88826 # DTB read misses +system.cpu0.dtb.write_hits 85455153 # DTB write hits +system.cpu0.dtb.write_misses 36333 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36431 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5198 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4810 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10393 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91889903 # DTB read accesses -system.cpu0.dtb.write_accesses 85035846 # DTB write accesses +system.cpu0.dtb.perms_faults 10399 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 92560289 # DTB read accesses +system.cpu0.dtb.write_accesses 85491486 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176801329 # DTB hits -system.cpu0.dtb.misses 124420 # DTB misses -system.cpu0.dtb.accesses 176925749 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 177926616 # DTB hits +system.cpu0.dtb.misses 125159 # DTB misses +system.cpu0.dtb.accesses 178051775 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -210,463 +210,464 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 60852 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60852 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60852 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 61082 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61082 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 61082 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61082 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61082 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54793 98.83% 98.83% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 650 1.17% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 55443 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 54995 98.82% 98.82% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 656 1.18% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 55651 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60852 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60852 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61082 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61082 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55443 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55443 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 116295 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 493637993 # ITB inst hits -system.cpu0.itb.inst_misses 60852 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55651 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55651 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 116733 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 496679820 # ITB inst hits +system.cpu0.itb.inst_misses 61082 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25053 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25177 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 493698845 # ITB inst accesses -system.cpu0.itb.hits 493637993 # DTB hits -system.cpu0.itb.misses 60852 # DTB misses -system.cpu0.itb.accesses 493698845 # DTB accesses -system.cpu0.numPwrStateTransitions 26456 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13226 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3548051502.510434 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 89670925641.729767 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3168 23.95% 23.95% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10031 75.84% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 496740902 # ITB inst accesses +system.cpu0.itb.hits 496679820 # DTB hits +system.cpu0.itb.misses 61082 # DTB misses +system.cpu0.itb.accesses 496740902 # DTB accesses +system.cpu0.numPwrStateTransitions 26445 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13222 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3555001605.490697 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 88683028869.484894 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3170 23.98% 23.98% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10025 75.82% 99.80% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7470356053852 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13226 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 290285629797 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46926529172203 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94433642835 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7351153278004 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13222 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 292050520702 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47004231227798 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94592576721 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13230 # number of quiesce instructions executed -system.cpu0.committedInsts 493402150 # Number of instructions committed -system.cpu0.committedOps 580232432 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 531778274 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 521057 # Number of float alu accesses -system.cpu0.num_func_calls 28738017 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75812609 # number of instructions that are conditional controls -system.cpu0.num_int_insts 531778274 # number of integer instructions -system.cpu0.num_fp_insts 521057 # number of float instructions -system.cpu0.num_int_register_reads 778807297 # number of times the integer registers were read -system.cpu0.num_int_register_writes 421918818 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 841474 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 439940 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132610797 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132275173 # number of times the CC registers were written -system.cpu0.num_mem_refs 176902115 # number of memory refs -system.cpu0.num_load_insts 91875039 # Number of load instructions -system.cpu0.num_store_insts 85027076 # Number of store instructions -system.cpu0.num_idle_cycles 93853071494.060760 # Number of idle cycles -system.cpu0.num_busy_cycles 580571340.939238 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006148 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993852 # Percentage of idle cycles -system.cpu0.Branches 110403926 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13223 # number of quiesce instructions executed +system.cpu0.committedInsts 496443686 # Number of instructions committed +system.cpu0.committedOps 583761680 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 535025290 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 524584 # Number of float alu accesses +system.cpu0.num_func_calls 28899937 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76311856 # number of instructions that are conditional controls +system.cpu0.num_int_insts 535025290 # number of integer instructions +system.cpu0.num_fp_insts 524584 # number of float instructions +system.cpu0.num_int_register_reads 783282318 # number of times the integer registers were read +system.cpu0.num_int_register_writes 424505870 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 845921 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 445948 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133408683 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 133073326 # number of times the CC registers were written +system.cpu0.num_mem_refs 178027643 # number of memory refs +system.cpu0.num_load_insts 92545018 # Number of load instructions +system.cpu0.num_store_insts 85482625 # Number of store instructions +system.cpu0.num_idle_cycles 94008475597.936935 # Number of idle cycles +system.cpu0.num_busy_cycles 584101123.063064 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006175 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993825 # Percentage of idle cycles +system.cpu0.Branches 111093071 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 402310075 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1222689 0.21% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 59704 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 72217 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::MemRead 91875039 15.83% 85.35% # Class of executed instruction -system.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 404699186 69.29% 69.29% # Class of executed instruction +system.cpu0.op_class::IntMult 1236587 0.21% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 60193 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 72938 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::MemRead 92545018 15.84% 85.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 85482625 14.64% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 580566843 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6218107 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6218619 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.419706 # Average number of references to valid blocks. +system.cpu0.op_class::total 584096590 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6248912 # number of replacements +system.cpu0.dcache.tags.tagsinuse 501.980044 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 171607959 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6249424 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.459804 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.352532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983110 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983110 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.980044 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980430 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.980430 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80242803 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214677 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 214677 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 260385 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 260385 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076595 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2076595 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2038168 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2038168 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165891148 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 165891148 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 166105825 # number of overall hits -system.cpu0.dcache.overall_hits::total 166105825 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3280646 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3280646 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1472125 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1472125 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768471 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 768471 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 819890 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 819890 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 117360 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 117360 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154684 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 154684 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5572661 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5572661 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6341132 # number of overall misses -system.cpu0.dcache.overall_misses::total 6341132 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88668606 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88668606 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81714928 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81714928 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 983148 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 983148 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1080275 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1080275 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193955 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2193955 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2192852 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2192852 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 171463809 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 171463809 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 172446957 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 172446957 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036999 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036999 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018015 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018015 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781643 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781643 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758964 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.758964 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070540 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032501 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032501 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036771 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036771 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 362271537 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 362271537 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 86024172 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86024172 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80672636 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80672636 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 216269 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 216269 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261023 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 261023 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2087977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051999 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2051999 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 166957831 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 166957831 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167174100 # number of overall hits +system.cpu0.dcache.overall_hits::total 167174100 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3298422 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3298422 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1479208 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1479208 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 769563 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 769563 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 824176 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 824176 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119749 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119749 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154638 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 154638 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5601806 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5601806 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6371369 # number of overall misses +system.cpu0.dcache.overall_misses::total 6371369 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89322594 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89322594 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82151844 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82151844 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 985832 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 985832 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1085199 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1085199 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207726 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2207726 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2206637 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2206637 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 172559637 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 172559637 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 173545469 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 173545469 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036927 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036927 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018006 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018006 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.780623 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780623 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759470 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759470 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054241 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054241 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070079 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070079 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032463 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032463 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036713 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036713 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks -system.cpu0.dcache.writebacks::total 6218107 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5488502 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5489014 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.942097 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor +system.cpu0.dcache.writebacks::writebacks 6248912 # number of writebacks +system.cpu0.dcache.writebacks::total 6248912 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5509619 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989024 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 491225335 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5510131 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 89.149484 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989024 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 488204417 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 488204417 # number of overall hits -system.cpu0.icache.overall_hits::total 488204417 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5489019 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5489019 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5489019 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5489019 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5489019 # number of overall misses -system.cpu0.icache.overall_misses::total 5489019 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 493693436 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 493693436 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 493693436 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 493693436 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 493693436 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 493693436 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011118 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011118 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011118 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011118 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011118 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011118 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 998981078 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 998981078 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 491225335 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 491225335 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 491225335 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 491225335 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 491225335 # number of overall hits +system.cpu0.icache.overall_hits::total 491225335 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5510136 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5510136 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5510136 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5510136 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5510136 # number of overall misses +system.cpu0.icache.overall_misses::total 5510136 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 496735471 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 496735471 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 496735471 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 496735471 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 496735471 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 496735471 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011093 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011093 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011093 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011093 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011093 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011093 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks -system.cpu0.icache.writebacks::total 5488502 # number of writebacks -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 5509619 # number of writebacks +system.cpu0.icache.writebacks::total 5509619 # number of writebacks +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2643580 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2659582 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.807038 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2653803 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16139.372932 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15525451 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2669765 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.815287 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16070.787170 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 39.567916 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 37.515300 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.980883 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002415 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002290 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985588 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 16063.015838 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 35.657747 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 40.699347 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.980409 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002176 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002484 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985069 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15949 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15909 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1503 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4323 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5407 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4485 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1444 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4368 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5335 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4524 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4423360 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4423360 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7281875 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7281875 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 738 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 738 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 633298 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 633298 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4991790 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4991790 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937635 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2937635 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218374 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 218374 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 293436 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155846 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4991790 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3570933 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 9012005 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 293436 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155846 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4991790 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3570933 # number of overall hits -system.cpu0.l2cache.overall_hits::total 9012005 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11306 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8709 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 20015 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136695 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 136695 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154684 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 154684 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 701772 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 701772 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1228842 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1228842 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601138 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 601138 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11306 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8709 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1930614 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2447858 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11306 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8709 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1930614 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2447858 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 304742 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164555 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 469297 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4423360 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4423360 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7281875 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7281875 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137433 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 137433 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154684 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 154684 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1335070 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1335070 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5489019 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5489019 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4166477 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4166477 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819512 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 819512 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 304742 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164555 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5489019 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5501547 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11459863 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 304742 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164555 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5489019 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5501547 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11459863 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052925 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.042649 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994630 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994630 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971008 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 395826781 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 395826781 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 296735 # 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number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2954772 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 221315 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 221315 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 296735 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157755 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5010934 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3593858 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 9059282 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 296735 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157755 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5010934 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3593858 # number of overall hits +system.cpu0.l2cache.overall_hits::total 9059282 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11441 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8530 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 19971 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138499 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 138499 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154638 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 154638 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 701212 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 701212 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 499202 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 499202 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1232962 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1232962 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 602526 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 602526 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11441 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8530 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 499202 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1934174 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2453347 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11441 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8530 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 499202 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1934174 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2453347 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 308176 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 166285 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 474461 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4439476 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4439476 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7317657 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7317657 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139245 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 139245 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154638 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 154638 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1340298 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1340298 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510136 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5510136 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187734 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4187734 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 823841 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 823841 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 308176 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166285 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5510136 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5528032 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11512629 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 308176 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166285 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5510136 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5528032 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11512629 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051297 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.042092 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994643 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994643 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525644 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525644 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090586 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090586 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294936 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294936 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733532 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733532 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052925 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090586 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350922 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.213603 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037100 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052925 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090586 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350922 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.213603 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.523176 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.523176 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090597 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090597 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294422 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294422 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731362 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731362 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051297 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090597 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.349885 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.213101 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051297 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090597 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.349885 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.213101 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 1554149 # number of writebacks -system.cpu0.l2cache.writebacks::total 1554149 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 24067586 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12257514 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33238 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4423360 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7283249 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 137433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154684 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 292117 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1335070 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1335070 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5489019 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4166477 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 819512 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 819512 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16552790 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19577101 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 363556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 723958 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37217405 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 702733844 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 750256336 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1454224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2895832 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1457340236 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6073545 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 30354370 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.066939 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.249960 # Request fanout histogram +system.cpu0.l2cache.writebacks::writebacks 1559963 # number of writebacks +system.cpu0.l2cache.writebacks::total 1559963 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 24176858 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12314856 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1775409 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1775098 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 311 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 622617 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10320487 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33234 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33234 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4439476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7319055 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 139245 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154638 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 293883 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1340298 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1340298 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187734 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 823841 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 823841 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616141 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19673024 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364916 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 727936 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37382017 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705436820 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753922812 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1459664 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2911744 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1463731040 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6082125 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 101619328 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 30471409 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.066979 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.250027 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28322817 93.31% 93.31% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2031217 6.69% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 336 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28430762 93.30% 93.30% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2040336 6.70% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 311 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.snoop_fanout::total 30471409 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -696,47 +697,47 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 144355 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 144355 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 144355 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 111959 88.88% 88.88% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14012 11.12% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 125971 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144355 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 144363 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144363 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144363 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144363 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144363 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 111796 88.76% 88.76% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 14154 11.24% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 125950 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144363 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144355 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125971 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144363 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125950 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125971 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 270326 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125950 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 270313 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91325952 # DTB read hits -system.cpu1.dtb.read_misses 111931 # DTB read misses -system.cpu1.dtb.write_hits 82141676 # DTB write hits -system.cpu1.dtb.write_misses 32424 # DTB write misses +system.cpu1.dtb.read_hits 90656208 # DTB read hits +system.cpu1.dtb.read_misses 111973 # DTB read misses +system.cpu1.dtb.write_hits 81688076 # DTB write hits +system.cpu1.dtb.write_misses 32390 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44794 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44622 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4450 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4399 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11485 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91437883 # DTB read accesses -system.cpu1.dtb.write_accesses 82174100 # DTB write accesses +system.cpu1.dtb.perms_faults 11479 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90768181 # DTB read accesses +system.cpu1.dtb.write_accesses 81720466 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 173467628 # DTB hits -system.cpu1.dtb.misses 144355 # DTB misses -system.cpu1.dtb.accesses 173611983 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 172344284 # DTB hits +system.cpu1.dtb.misses 144363 # DTB misses +system.cpu1.dtb.accesses 172488647 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -766,460 +767,462 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 61638 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61638 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61638 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54650 99.05% 99.05% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 526 0.95% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55176 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 61351 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61351 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61351 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61351 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61351 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54387 99.05% 99.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 524 0.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 54911 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61638 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61638 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61351 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61351 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55176 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55176 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 116814 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 483902380 # ITB inst hits -system.cpu1.itb.inst_misses 61638 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54911 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54911 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 116262 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 480862179 # ITB inst hits +system.cpu1.itb.inst_misses 61351 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31448 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31395 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 483964018 # ITB inst accesses -system.cpu1.itb.hits 483902380 # DTB hits -system.cpu1.itb.misses 61638 # DTB misses -system.cpu1.itb.accesses 483964018 # DTB accesses -system.cpu1.numPwrStateTransitions 12326 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 6163 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 7615138435.844394 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 188025849317.388916 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4489 72.84% 72.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1652 26.81% 99.64% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.10% 99.74% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 480923530 # ITB inst accesses +system.cpu1.itb.hits 480862179 # DTB hits +system.cpu1.itb.misses 61351 # DTB misses +system.cpu1.itb.accesses 480923530 # DTB accesses +system.cpu1.numPwrStateTransitions 12248 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 6124 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 7676898273.449706 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 188572680414.552032 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4459 72.81% 72.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1644 26.85% 99.66% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.74% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813542449500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 6163 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 284716621891 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46932098180109 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94433635768 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 11813542452500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 6124 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 282956721894 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47013325026606 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94592569622 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu1.committedInsts 483651505 # Number of instructions committed -system.cpu1.committedOps 569122264 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 522328734 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 379089 # Number of float alu accesses -system.cpu1.num_func_calls 28525698 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 74077236 # number of instructions that are conditional controls -system.cpu1.num_int_insts 522328734 # number of integer instructions -system.cpu1.num_fp_insts 379089 # number of float instructions -system.cpu1.num_int_register_reads 771436981 # number of times the integer registers were read -system.cpu1.num_int_register_writes 415765246 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 615128 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 311192 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 127876698 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 127597836 # number of times the CC registers were written -system.cpu1.num_mem_refs 173588529 # number of memory refs -system.cpu1.num_load_insts 91424864 # Number of load instructions -system.cpu1.num_store_insts 82163665 # Number of store instructions -system.cpu1.num_idle_cycles 93864202487.047195 # Number of idle cycles -system.cpu1.num_busy_cycles 569433280.952807 # Number of busy cycles -system.cpu1.not_idle_fraction 0.006030 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.993970 # Percentage of idle cycles -system.cpu1.Branches 107756231 # Number of branches fetched +system.cpu1.kern.inst.quiesce 6124 # number of quiesce instructions executed +system.cpu1.committedInsts 480611396 # Number of instructions committed +system.cpu1.committedOps 565602830 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 519092247 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 374666 # Number of float alu accesses +system.cpu1.num_func_calls 28363152 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 73579507 # number of instructions that are conditional controls +system.cpu1.num_int_insts 519092247 # number of integer instructions +system.cpu1.num_fp_insts 374666 # number of float instructions +system.cpu1.num_int_register_reads 766987939 # number of times the integer registers were read +system.cpu1.num_int_register_writes 413187755 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 609913 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 303136 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 127077975 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 126798720 # number of times the CC registers were written +system.cpu1.num_mem_refs 172465256 # number of memory refs +system.cpu1.num_load_insts 90755131 # Number of load instructions +system.cpu1.num_store_insts 81710125 # Number of store instructions +system.cpu1.num_idle_cycles 94026656141.566330 # Number of idle cycles +system.cpu1.num_busy_cycles 565913480.433670 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005983 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994017 # Percentage of idle cycles +system.cpu1.Branches 107067845 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 394594292 69.30% 69.30% # Class of executed instruction -system.cpu1.op_class::IntMult 1146816 0.20% 69.50% # Class of executed instruction -system.cpu1.op_class::IntDiv 61459 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 37349 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::IntAlu 392212619 69.31% 69.31% # Class of executed instruction +system.cpu1.op_class::IntMult 1132978 0.20% 69.51% # Class of executed instruction +system.cpu1.op_class::IntDiv 61173 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 36628 0.01% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 91424864 16.06% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 90755131 16.04% 85.56% # Class of executed instruction +system.cpu1.op_class::MemWrite 81710125 14.44% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 569428445 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 6003966 # number of replacements -system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 6004478 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.891759 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.687505 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.827515 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.827515 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 77963660 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187526 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 187526 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 65427 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 65427 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2067288 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2067288 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2056969 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2056969 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 162861135 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 162861135 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 163048661 # number of overall hits -system.cpu1.dcache.overall_hits::total 163048661 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3388721 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3388721 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1469364 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1469364 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 795051 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 795051 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 438458 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 438458 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 148516 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 148516 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157576 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 157576 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5296543 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5296543 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6091594 # number of overall misses -system.cpu1.dcache.overall_misses::total 6091594 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 88220769 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 88220769 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 79433024 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 79433024 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 982577 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 982577 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 503885 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 503885 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2215804 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2215804 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2214545 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2214545 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 168157678 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 168157678 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 169140255 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 169140255 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038412 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038412 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018498 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018498 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809149 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870155 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870155 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067026 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067026 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071155 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071155 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031497 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031497 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036015 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.036015 # miss rate for overall accesses +system.cpu1.op_class::total 565908654 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5970882 # number of replacements +system.cpu1.dcache.tags.tagsinuse 423.354804 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 166384450 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5971393 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.863591 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.354804 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.826865 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.826865 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 350957209 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 350957209 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 84198599 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 84198599 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 77532107 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 77532107 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187263 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187263 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64879 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 64879 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055501 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2055501 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044925 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2044925 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 161795585 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 161795585 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 161982848 # number of overall hits +system.cpu1.dcache.overall_hits::total 161982848 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3367289 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3367289 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1465578 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1465578 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 793623 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 793623 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433878 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 433878 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147104 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 147104 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156474 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 156474 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5266745 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5266745 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6060368 # number of overall misses +system.cpu1.dcache.overall_misses::total 6060368 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87565888 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87565888 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 78997685 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 78997685 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980886 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 980886 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498757 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 498757 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2202605 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2202605 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2201399 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2201399 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 167062330 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 167062330 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 168043216 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 168043216 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038454 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038454 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018552 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018552 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809088 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809088 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869919 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.869919 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066786 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066786 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071079 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071079 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031526 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031526 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036064 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.036064 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks -system.cpu1.dcache.writebacks::total 6003966 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4799154 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4799666 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.831507 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy +system.cpu1.dcache.writebacks::writebacks 5970882 # number of writebacks +system.cpu1.dcache.writebacks::total 5970882 # number of writebacks +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4768482 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.452247 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 476148096 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4768994 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.842461 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.452247 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969633 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969633 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 479157890 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 479157890 # number of overall hits -system.cpu1.icache.overall_hits::total 479157890 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4799666 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4799666 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4799666 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4799666 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4799666 # number of overall misses -system.cpu1.icache.overall_misses::total 4799666 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 483957556 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 483957556 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 483957556 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 483957556 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 483957556 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 483957556 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009918 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009918 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009918 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009918 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009918 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009918 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 966603174 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 966603174 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 476148096 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 476148096 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 476148096 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 476148096 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 476148096 # number of overall hits +system.cpu1.icache.overall_hits::total 476148096 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4768994 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4768994 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4768994 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4768994 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4768994 # number of overall misses +system.cpu1.icache.overall_misses::total 4768994 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 480917090 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 480917090 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 480917090 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 480917090 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 480917090 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 480917090 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks -system.cpu1.icache.writebacks::total 4799154 # number of writebacks -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.writebacks::writebacks 4768482 # number of writebacks +system.cpu1.icache.writebacks::total 4768482 # number of writebacks +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2283161 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2299207 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.258624 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10262240501000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 13228.741418 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.265537 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.948066 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.807418 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003129 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004025 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.814572 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15957 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2262891 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13357.261726 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 14305129 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2278874 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.277279 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9829187815500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 13247.067066 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.785938 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.408722 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.808537 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003161 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003565 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.815263 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15892 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1511 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4384 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3784 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 4070389 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 4070389 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6732353 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6732353 # number of WritebackClean hits +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1574 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6119 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4359 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3688 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.969971 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 363588050 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 363588050 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 348760 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155429 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 504189 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 4050331 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 4050331 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6688666 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 6688666 # number of WritebackClean hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 1054 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 615614 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 615614 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4333068 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4333068 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3106952 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3106952 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 166128 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 166128 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 347777 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155733 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4333068 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3722566 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8559144 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 347777 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155733 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4333068 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3722566 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8559144 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12333 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9620 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 21953 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143903 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 143903 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157576 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 157576 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 709038 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 466598 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 466598 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1225336 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1225336 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272085 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 272085 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12333 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9620 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 466598 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1934374 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2422925 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12333 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9620 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 466598 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1934374 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2422925 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360110 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165353 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 525463 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4070389 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 4070389 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6732353 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6732353 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144957 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 144957 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157576 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 157576 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1324652 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1324652 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4799666 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 4799666 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4332288 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 4332288 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 438213 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 438213 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360110 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165353 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4799666 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5656940 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10982069 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360110 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165353 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4799666 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5656940 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10982069 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058179 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.041778 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992729 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992729 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 613437 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 613437 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4306709 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4306709 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3087044 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3087044 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 164780 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 164780 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 348760 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155429 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4306709 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3700481 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8511379 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 348760 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155429 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4306709 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3700481 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8511379 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12218 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9629 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 21847 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143649 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 143649 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156474 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 156474 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 707649 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 707649 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 462285 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 462285 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1220972 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1220972 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268887 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 268887 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12218 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9629 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 462285 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1928621 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2412753 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12218 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9629 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 462285 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1928621 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2412753 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360978 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165058 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 526036 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4050331 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 4050331 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6688666 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6688666 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144703 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 144703 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156474 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 156474 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1321086 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1321086 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4768994 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 4768994 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308016 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4308016 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433667 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 433667 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360978 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165058 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4768994 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5629102 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10924132 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360978 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165058 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4768994 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5629102 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10924132 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058337 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.041531 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992716 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992716 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535264 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535264 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097215 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097215 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.282838 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.282838 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620897 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620897 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058179 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097215 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341947 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.220626 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034248 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058179 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097215 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341947 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.220626 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535657 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535657 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096936 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096936 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283419 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283419 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620031 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620031 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058337 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096936 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342616 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.220865 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058337 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096936 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342616 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.220865 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 1211269 # number of writebacks -system.cpu1.l2cache.writebacks::total 1211269 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 22276444 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11381625 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5562 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4070389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6732731 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 144957 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 302533 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1324652 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1324652 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4799666 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4332288 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 438213 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 438213 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14398746 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18822028 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368476 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836878 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34426128 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 614325000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 746331191 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1473904 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3347512 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1365477607 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5687998 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 28144557 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.072239 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.258905 # Request fanout histogram +system.cpu1.l2cache.writebacks::writebacks 1200117 # number of writebacks +system.cpu1.l2cache.writebacks::total 1200117 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 22145801 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314039 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 367 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1748963 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1748793 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 607661 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9684671 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5564 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5564 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4050331 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6689033 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 144703 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156474 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 301177 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1321086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1321086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4768994 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308016 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 433667 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 433667 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14306730 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18721524 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836674 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34231694 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610398984 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432303 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1467064 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3346696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1357645047 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5675394 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 79399936 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 28001988 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.072258 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.258938 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26111598 92.78% 92.78% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2032793 7.22% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 166 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 25978793 92.77% 92.77% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2023025 7.22% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.snoop_fanout::total 28001988 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40301 # Transaction distribution system.iobus.trans_dist::ReadResp 40301 # Transaction distribution system.iobus.trans_dist::WriteReq 136636 # Transaction distribution @@ -1262,24 +1265,24 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7338888 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115590 # number of replacements -system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use +system.iocache.tags.tagsinuse 11.298808 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9107775784009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.856196 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.433018 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.241012 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464564 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705576 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.845510 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.453298 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240344 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465831 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706176 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1040838 # Number of tag accesses system.iocache.tags.data_accesses 1040838 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses @@ -1327,278 +1330,279 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1772279 # number of replacements -system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use -system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1831889 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.527460 # Average number of references to valid blocks. +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1774395 # number of replacements +system.l2c.tags.tagsinuse 63409.930559 # Cycle average of tags in use +system.l2c.tags.total_refs 4611925 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1833378 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.515534 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34852.259954 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.728290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 43.277467 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3264.617227 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6940.607740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 274.307726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 426.439632 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2871.138387 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 14482.680343 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.531803 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000545 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000660 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.049814 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004186 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.043810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.220988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964219 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 59404 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3390 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5782 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49679 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 73419992 # Number of tag accesses -system.l2c.tags.data_accesses 73419992 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15575 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33354 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2588 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2404 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4992 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 200286 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 176214 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 376500 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6410 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4846 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 439050 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 727042 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5703 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3689 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 424901 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 685160 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2296801 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 115689 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 102800 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 218489 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6410 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 439050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 927328 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5703 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3689 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 424901 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 861374 # number of demand (read+write) hits -system.l2c.demand_hits::total 2673301 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6410 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4846 # number of overall hits -system.l2c.overall_hits::cpu0.inst 439050 # number of overall hits -system.l2c.overall_hits::cpu0.data 927328 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5703 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3689 # number of overall hits -system.l2c.overall_hits::cpu1.inst 424901 # number of overall hits -system.l2c.overall_hits::cpu1.data 861374 # number of overall hits -system.l2c.overall_hits::total 2673301 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 64906 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 60031 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 124937 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 6479 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 6386 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 12865 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 376689 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 423433 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 800122 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2349 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1944 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 58179 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 178934 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3469 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3479 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 41697 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 188396 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 478447 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 477304 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 163191 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 640495 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2349 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1944 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 58179 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 555623 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3479 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 41697 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 611829 # number of demand (read+write) misses -system.l2c.demand_misses::total 1278569 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2349 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1944 # number of overall misses -system.l2c.overall_misses::cpu0.inst 58179 # number of overall misses -system.l2c.overall_misses::cpu0.data 555623 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3479 # number of overall misses -system.l2c.overall_misses::cpu1.inst 41697 # number of overall misses -system.l2c.overall_misses::cpu1.data 611829 # number of overall misses -system.l2c.overall_misses::total 1278569 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 2765418 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2765418 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 82685 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 75606 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 158291 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9067 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8790 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17857 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 576975 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 599647 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1176622 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8759 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6790 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 905976 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9172 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7168 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 466598 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 873556 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2775248 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 592993 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 265991 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 858984 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6790 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1482951 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9172 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7168 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 466598 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1473203 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3951870 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6790 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1482951 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9172 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7168 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 466598 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1473203 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3951870 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784979 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793998 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.789287 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.714569 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.726507 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.720446 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.652869 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.706137 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.680016 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286303 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.117006 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.197504 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.485352 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089364 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.215666 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.172398 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804907 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.613521 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.745643 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.286303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.117006 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.374674 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.485352 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.089364 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.415305 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.323535 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.268181 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.286303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.117006 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.374674 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.378216 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.485352 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.089364 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.415305 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.323535 # miss rate for overall accesses +system.l2c.tags.occ_blocks::writebacks 34658.678488 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 33.446161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 43.299197 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3299.237288 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7180.746684 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.688902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 432.688870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2834.364418 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 14654.780551 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.528849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.109569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004161 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006602 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.043249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.223614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.967559 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 232 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 58751 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 231 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 463 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3223 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49760 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.896469 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 73267769 # Number of tag accesses +system.l2c.tags.data_accesses 73267769 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2760080 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2760080 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 17858 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 15288 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 33146 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2554 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2409 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4963 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 196672 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 175397 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 372069 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6428 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4634 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 441340 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 728132 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5456 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3654 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 420919 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 680845 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2291408 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 115975 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 102728 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 218703 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6428 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4634 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 441340 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 924804 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5456 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3654 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 420919 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 856242 # number of demand (read+write) hits +system.l2c.demand_hits::total 2663477 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6428 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4634 # number of overall hits +system.l2c.overall_hits::cpu0.inst 441340 # number of overall hits +system.l2c.overall_hits::cpu0.data 924804 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5456 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3654 # number of overall hits +system.l2c.overall_hits::cpu1.inst 420919 # number of overall hits +system.l2c.overall_hits::cpu1.data 856242 # number of overall hits +system.l2c.overall_hits::total 2663477 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 65292 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 60363 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 125655 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 6568 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 6268 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 12836 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 377580 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 423134 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 800714 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2366 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1943 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 57862 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 180178 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3474 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3458 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 41366 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 189464 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 480111 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 478573 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 160244 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 638817 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1943 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 57862 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 557758 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3474 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3458 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 612598 # number of demand (read+write) misses +system.l2c.demand_misses::total 1280825 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2366 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1943 # number of overall misses +system.l2c.overall_misses::cpu0.inst 57862 # number of overall misses +system.l2c.overall_misses::cpu0.data 557758 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3474 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3458 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41366 # number of overall misses +system.l2c.overall_misses::cpu1.data 612598 # number of overall misses +system.l2c.overall_misses::total 1280825 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 2760080 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2760080 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 83150 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 75651 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 158801 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9122 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8677 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17799 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 574252 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 598531 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1172783 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8794 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6577 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 499202 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 908310 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8930 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7112 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 462285 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 870309 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2771519 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 594548 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 262972 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 857520 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8794 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 499202 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1482562 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8930 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7112 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 462285 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1468840 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3944302 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8794 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 499202 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1482562 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8930 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7112 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 462285 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1468840 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3944302 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785232 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.797914 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.791273 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.720018 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.722369 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.721164 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.657516 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.706954 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.682747 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.295423 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.115909 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.198366 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.486220 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089482 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.217697 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.173230 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804936 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.609358 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.744959 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.295423 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.115909 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.376212 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.486220 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.089482 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.417062 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.324728 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.295423 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.115909 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.376212 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.486220 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.089482 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.417062 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.324728 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1477304 # number of writebacks -system.l2c.writebacks::total 1477304 # number of writebacks -system.membus.snoop_filter.tot_requests 4491425 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2595543 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 1478540 # number of writebacks +system.l2c.writebacks::total 1478540 # number of writebacks +system.membus.snoop_filter.tot_requests 4495065 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2597713 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3483 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 82119 # Transaction distribution -system.membus.trans_dist::ReadResp 569484 # Transaction distribution -system.membus.trans_dist::WriteReq 38800 # Transaction distribution -system.membus.trans_dist::WriteResp 38800 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1583998 # Transaction distribution -system.membus.trans_dist::CleanEvict 246737 # Transaction distribution -system.membus.trans_dist::UpgradeReq 335468 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 307268 # Transaction distribution -system.membus.trans_dist::UpgradeResp 157952 # Transaction distribution -system.membus.trans_dist::ReadExReq 787861 # Transaction distribution -system.membus.trans_dist::ReadExResp 784470 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 487365 # Transaction distribution -system.membus.trans_dist::InvalidateReq 742728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 742728 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 82130 # Transaction distribution +system.membus.trans_dist::ReadResp 571159 # Transaction distribution +system.membus.trans_dist::WriteReq 38798 # Transaction distribution +system.membus.trans_dist::WriteResp 38798 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1585234 # Transaction distribution +system.membus.trans_dist::CleanEvict 247687 # Transaction distribution +system.membus.trans_dist::UpgradeReq 337993 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306149 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159131 # Transaction distribution +system.membus.trans_dist::ReadExReq 787924 # Transaction distribution +system.membus.trans_dist::ReadExResp 784573 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 489029 # Transaction distribution +system.membus.trans_dist::InvalidateReq 741049 # Transaction distribution +system.membus.trans_dist::InvalidateResp 741049 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6408698 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6558890 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6413605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6563815 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6905778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6910703 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175567900 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 175778835 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55084 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175760092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 175971063 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 183178003 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 183370231 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4612344 # Request fanout histogram -system.membus.snoop_fanout::mean 0.007156 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.084293 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 4615993 # Request fanout histogram +system.membus.snoop_fanout::mean 0.007281 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.085020 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4579336 99.28% 99.28% # Request fanout histogram -system.membus.snoop_fanout::1 33008 0.72% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4582382 99.27% 99.27% # Request fanout histogram +system.membus.snoop_fanout::1 33611 0.73% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4612344 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 4615993 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1608,11 +1612,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1641,67 +1645,68 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38800 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2765418 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2011530 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 348672 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 312260 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 660932 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1356975 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1356975 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3459973 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 858984 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 858984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9470177 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8222341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17692518 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254644772 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231031359 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 485676131 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1806287 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13039342 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.283997 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.453251 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 11098491 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5714084 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1638499 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 134977 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 121387 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 13590 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 82132 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3539371 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 2760080 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2007636 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 350499 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 311112 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 661611 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1354403 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1354403 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3457239 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 857520 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 857520 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9497179 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8173943 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17671122 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255360528 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229634423 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 484994951 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1809010 # Total snoops (count) +system.toL2Bus.snoopTraffic 94667072 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 13026748 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.284748 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.453600 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9349855 71.70% 71.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3675839 28.19% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 13648 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9330997 71.63% 71.63% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3682161 28.27% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 13590 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13039342 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13026748 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal index 251986706..8c0552b36 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/system.terminal @@ -91,7 +91,7 @@ [ 2.143447] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 2.143448] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 2.143450] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.143451] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.143452] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.143453] pci_bus 0000:00: scanning bus
[ 2.143455] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 2.143457] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
@@ -100,7 +100,7 @@ [ 2.143477] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 2.143479] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 2.143481] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.143482] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.143483] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 2.143484] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 2.143486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.143503] pci_bus 0000:00: fixups for bus
@@ -130,17 +130,17 @@ [ 2.144377] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.144381] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.144382] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290388] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290389] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290387] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290388] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290395] ata1.00: configured for UDMA/33
-[ 2.290412] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.290466] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.290469] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.290411] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.290465] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.290468] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.290484] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.290486] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.290493] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.290548] sda: sda1
-[ 2.290610] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.290485] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.290492] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.290547] sda: sda1
+[ 2.290609] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.410644] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.410646] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.410652] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
@@ -158,9 +158,9 @@ [ 2.411057] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.446371] udevd[609]: starting version 182
+[ 2.446370] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.521978] random: dd urandom read with 17 bits of entropy available
+[ 2.521984] random: dd urandom read with 17 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.620600] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.620646] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|