diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt | 1161 |
1 files changed, 580 insertions, 581 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 203bf8cf0..81cebbb77 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.548252 # Number of seconds simulated -sim_ticks 51548252400500 # Number of ticks simulated -final_tick 51548252400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.071102 # Number of seconds simulated +sim_ticks 51071102402000 # Number of ticks simulated +final_tick 51071102402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1717705 # Simulator instruction rate (inst/s) -host_op_rate 1880520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48787200192 # Simulator tick rate (ticks/s) -host_mem_usage 679528 # Number of bytes of host memory used -host_seconds 1056.59 # Real time elapsed on the host -sim_insts 1814916572 # Number of instructions simulated -sim_ops 1986945286 # Number of ops (including micro ops) simulated +host_inst_rate 1747137 # Simulator instruction rate (inst/s) +host_op_rate 2084338 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95484785421 # Simulator tick rate (ticks/s) +host_mem_usage 679432 # Number of bytes of host memory used +host_seconds 534.86 # Real time elapsed on the host +sim_insts 934475925 # Number of instructions simulated +sim_ops 1114831373 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 388608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 367808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5292340 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 73326152 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 442368 # Number of bytes read from this memory -system.physmem.bytes_read::total 79817276 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5292340 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5292340 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101858624 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 487168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 439168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5588020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 87025992 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439360 # Number of bytes read from this memory +system.physmem.bytes_read::total 93979708 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5588020 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5588020 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 115462912 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 101879204 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6072 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 123100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1145734 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6912 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1287565 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1591541 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 115483492 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 7612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 91720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1359794 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6865 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1472853 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1804108 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1594114 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 102668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1422476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1548399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1975986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1976385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1975986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1422875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3524784 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.physmem.num_writes::total 1806681 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 9539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 8599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 109416 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1704016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1840174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 109416 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 109416 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2260827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2261230 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2260827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 9539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 8599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 109416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1704419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4101404 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -109,47 +109,47 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 267664 # Table walker walks requested -system.cpu.dtb.walker.walksLong 267664 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 267664 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 267664 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 267664 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 206672 89.75% 89.75% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 23595 10.25% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 230267 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 267664 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 297729 # Table walker walks requested +system.cpu.dtb.walker.walksLong 297729 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 297729 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 297729 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 297729 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 228847 88.79% 88.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 28897 11.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 257744 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 297729 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 267664 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 230267 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 297729 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 257744 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 230267 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 497931 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 257744 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 555473 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 421603994 # DTB read hits -system.cpu.dtb.read_misses 196270 # DTB read misses -system.cpu.dtb.write_hits 167651282 # DTB write hits -system.cpu.dtb.write_misses 71394 # DTB write misses +system.cpu.dtb.read_hits 192113611 # DTB read hits +system.cpu.dtb.read_misses 218086 # DTB read misses +system.cpu.dtb.write_hits 176013555 # DTB write hits +system.cpu.dtb.write_misses 79643 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 81418 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 85167 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9097 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 10256 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 21656 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 421800264 # DTB read accesses -system.cpu.dtb.write_accesses 167722676 # DTB write accesses +system.cpu.dtb.perms_faults 22356 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 192331697 # DTB read accesses +system.cpu.dtb.write_accesses 176093198 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 589255276 # DTB hits -system.cpu.dtb.misses 267664 # DTB misses -system.cpu.dtb.accesses 589522940 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 368127166 # DTB hits +system.cpu.dtb.misses 297729 # DTB misses +system.cpu.dtb.accesses 368424895 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -179,470 +179,469 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 126885 # Table walker walks requested -system.cpu.itb.walker.walksLong 126885 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126885 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126885 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126885 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113624 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114746 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 128928 # Table walker walks requested +system.cpu.itb.walker.walksLong 128928 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 128928 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 128928 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 128928 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 115252 99.04% 99.04% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 0.96% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 116374 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126885 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126885 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 128928 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 128928 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114746 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114746 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241631 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 1815394284 # ITB inst hits -system.cpu.itb.inst_misses 126885 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 116374 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 116374 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 245302 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 935011975 # ITB inst hits +system.cpu.itb.inst_misses 128928 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57333 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 59711 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 1815521169 # ITB inst accesses -system.cpu.itb.hits 1815394284 # DTB hits -system.cpu.itb.misses 126885 # DTB misses -system.cpu.itb.accesses 1815521169 # DTB accesses -system.cpu.numPwrStateTransitions 33574 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16787 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3011524161.053136 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59680214632.955681 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7463 44.46% 44.46% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9289 55.33% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 935140903 # ITB inst accesses +system.cpu.itb.hits 935011975 # DTB hits +system.cpu.itb.misses 128928 # DTB misses +system.cpu.itb.accesses 935140903 # DTB accesses +system.cpu.numPwrStateTransitions 33906 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16953 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2979611399.652038 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59761128093.250465 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7631 45.01% 45.01% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.78% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16787 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 993796308901 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50554456091599 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103096521589 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988782908468 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16953 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 557750343699 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50513352058301 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 102142221758 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16787 # number of quiesce instructions executed -system.cpu.committedInsts 1814916572 # Number of instructions committed -system.cpu.committedOps 1986945286 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1711962456 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 884728 # Number of float alu accesses -system.cpu.num_func_calls 56754008 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 449117161 # number of instructions that are conditional controls -system.cpu.num_int_insts 1711962456 # number of integer instructions -system.cpu.num_fp_insts 884728 # number of float instructions -system.cpu.num_int_register_reads 2333816547 # number of times the integer registers were read -system.cpu.num_int_register_writes 1316284167 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1424283 # number of times the floating registers were read -system.cpu.num_fp_register_writes 753044 # number of times the floating registers were written -system.cpu.num_cc_register_reads 621173289 # number of times the CC registers were read -system.cpu.num_cc_register_writes 620585461 # number of times the CC registers were written -system.cpu.num_mem_refs 589476099 # number of memory refs -system.cpu.num_load_insts 421772480 # Number of load instructions -system.cpu.num_store_insts 167703619 # Number of store instructions -system.cpu.num_idle_cycles 101108928647.540985 # Number of idle cycles -system.cpu.num_busy_cycles 1987592941.459016 # Number of busy cycles -system.cpu.not_idle_fraction 0.019279 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.980721 # Percentage of idle cycles -system.cpu.Branches 576475057 # Number of branches fetched +system.cpu.kern.inst.quiesce 16953 # number of quiesce instructions executed +system.cpu.committedInsts 934475925 # Number of instructions committed +system.cpu.committedOps 1114831373 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1036744712 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 878021 # Number of float alu accesses +system.cpu.num_func_calls 59056085 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 135851428 # number of instructions that are conditional controls +system.cpu.num_int_insts 1036744712 # number of integer instructions +system.cpu.num_fp_insts 878021 # number of float instructions +system.cpu.num_int_register_reads 1380118426 # number of times the integer registers were read +system.cpu.num_int_register_writes 809399347 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1413239 # number of times the floating registers were read +system.cpu.num_fp_register_writes 747664 # number of times the floating registers were written +system.cpu.num_cc_register_reads 207723168 # number of times the CC registers were read +system.cpu.num_cc_register_writes 207152857 # number of times the CC registers were written +system.cpu.num_mem_refs 368379179 # number of memory refs +system.cpu.num_load_insts 192305014 # Number of load instructions +system.cpu.num_store_insts 176074165 # Number of store instructions +system.cpu.num_idle_cycles 101026720885.444443 # Number of idle cycles +system.cpu.num_busy_cycles 1115500872.555553 # Number of busy cycles +system.cpu.not_idle_fraction 0.010921 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.989079 # Percentage of idle cycles +system.cpu.Branches 206489174 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1395540402 70.21% 70.21% # Class of executed instruction -system.cpu.op_class::IntMult 2356131 0.12% 70.33% # Class of executed instruction -system.cpu.op_class::IntDiv 100370 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatAdd 8 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 21 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMisc 107824 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 421659035 21.21% 91.56% # Class of executed instruction -system.cpu.op_class::MemWrite 167040202 8.40% 99.96% # Class of executed instruction -system.cpu.op_class::FloatMemRead 113445 0.01% 99.97% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 663417 0.03% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 744480688 66.74% 66.74% # Class of executed instruction +system.cpu.op_class::IntMult 2418794 0.22% 66.96% # Class of executed instruction +system.cpu.op_class::IntDiv 103036 0.01% 66.97% # Class of executed instruction +system.cpu.op_class::FloatAdd 8 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatCvt 21 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMisc 106782 0.01% 66.98% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::MemRead 192192210 17.23% 84.21% # Class of executed instruction +system.cpu.op_class::MemWrite 175415772 15.73% 99.93% # Class of executed instruction +system.cpu.op_class::FloatMemRead 112804 0.01% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 658393 0.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1987580869 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11603445 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999721 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 577795083 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11603957 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 49.792936 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999721 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.op_class::total 1115488522 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 12292096 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999911 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 356005277 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 12292608 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.960923 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999911 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 1.000000 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 1.000000 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2369200172 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2369200172 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 409181313 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 409181313 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158964390 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158964390 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 425694 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 425694 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336647 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336647 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4299455 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4299455 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4553147 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4553147 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 568482350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 568482350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 568908044 # number of overall hits -system.cpu.dcache.overall_hits::total 568908044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5993326 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5993326 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2556217 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2556217 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586747 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586747 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246619 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246619 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 255495 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 255495 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1485484203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1485484203 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 178905891 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 178905891 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166844782 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166844782 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 437201 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 437201 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 338801 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 338801 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4589501 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4589501 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4852460 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4852460 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 346089474 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 346089474 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 346526675 # number of overall hits +system.cpu.dcache.overall_hits::total 346526675 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6353340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6353340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2735988 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2735988 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1721890 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1721890 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1253245 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1253245 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 264796 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 264796 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9796162 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9796162 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11382909 # number of overall misses -system.cpu.dcache.overall_misses::total 11382909 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 415174639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415174639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161520607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161520607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2012441 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2012441 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583266 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1583266 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4554950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4554950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4553148 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4553148 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 578278512 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 578278512 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 580290953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 580290953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.014436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015826 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015826 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788469 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788469 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787372 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787372 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056092 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056092 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 10342573 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10342573 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12064463 # number of overall misses +system.cpu.dcache.overall_misses::total 12064463 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 185259231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 185259231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 169580770 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 169580770 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2159091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2159091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1592046 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1592046 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4854297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4854297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4852461 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4852461 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 356432047 # 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Cycle average of tags in use -system.cpu.icache.tags.total_refs 1801219181 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14289844 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 126.048904 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.984730 # Average occupied blocks per requestor +system.cpu.dcache.writebacks::writebacks 9441403 # number of writebacks +system.cpu.dcache.writebacks::total 9441403 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14554443 # number of replacements +system.cpu.icache.tags.tagsinuse 511.984790 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 920573389 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14554955 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.248110 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6040365000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.984790 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1829798879 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1829798879 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1801219181 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1801219181 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1801219181 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1801219181 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1801219181 # number of overall hits -system.cpu.icache.overall_hits::total 1801219181 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14289849 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14289849 # 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number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14289332 # number of writebacks -system.cpu.icache.writebacks::total 14289332 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1684196 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65394.978455 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 49472483 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1746767 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.322314 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9677.706964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 426.448625 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 480.005287 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6101.422178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48709.395401 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.147670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006507 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007324 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093100 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.743246 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 329 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62242 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 328 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1404 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5082 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55348 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005020 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 422888423 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 422888423 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 482010 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237204 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 719214 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8939334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8939334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14287756 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14287756 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 30651 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 30651 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1695121 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1695121 # 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number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 237204 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14209837 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9210432 # number of overall hits -system.cpu.l2cache.overall_hits::total 24139483 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6072 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5747 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 11819 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3785 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3785 # number of UpgradeReq misses +system.cpu.icache.writebacks::writebacks 14554443 # number of writebacks +system.cpu.icache.writebacks::total 14554443 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1939529 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65410.509732 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 51207751 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2002275 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.574784 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 373950000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9607.000136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 373.212421 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 441.072045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6073.861347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48915.363784 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.146591 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005695 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006730 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092680 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.746389 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 323 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62423 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1416 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5058 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55500 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004929 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952499 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 439130926 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 439130926 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 564464 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 243894 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 808358 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 9441403 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 9441403 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 242951 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 731033 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8939334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8939334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14287756 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14287756 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34436 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 34436 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 982214 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 982214 # 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number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 36640 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 36640 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2521781 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2521781 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14289849 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14289849 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7835568 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7835568 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246619 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1246619 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 488082 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 242951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14289849 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10357349 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25378231 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 488082 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 242951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14289849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10357349 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25378231 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012441 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.023655 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016168 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.109914 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.109914 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2699348 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2699348 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14554960 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14554960 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 8340026 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 8340026 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1253245 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1253245 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 572076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 250756 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14554960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 11039374 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 26417166 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 572076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 250756 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14554960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 11039374 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 26417166 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013306 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027365 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.017590 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.105841 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.105841 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.327808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.327808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040872 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040872 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.434679 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.434679 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012441 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.023655 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.110735 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.048811 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012441 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.023655 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.110735 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.048811 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.363871 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.363871 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045415 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045415 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.455479 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.455479 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013306 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027365 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123284 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.055361 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013306 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027365 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123284 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.055361 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1484910 # number of writebacks -system.cpu.l2cache.writebacks::total 1484910 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52410934 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26517119 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2740 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2740 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.writebacks::writebacks 1697477 # number of writebacks +system.cpu.l2cache.writebacks::total 1697477 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 54350593 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 27503016 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1759 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1234221 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23359638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8939334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14289332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2664111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 34436 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1286731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 24181717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9441403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14554443 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2850693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 36640 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 34437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2521781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2521781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14289849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7835568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1246619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1246619 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42955280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35014647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1556522 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80284963 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829240084 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235177526 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3034056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6226088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3073677754 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1724598 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 95094976 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 54812635 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010876 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103719 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 36641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2699348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2699348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14554960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 8340026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1253245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1253245 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43673813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37084586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 770772 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1726308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83255479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1863020692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1310959042 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3083088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6905232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3183968054 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1977015 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 108689536 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 57027218 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104200 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54216500 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596135 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 56401167 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 626051 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 54812635 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40253 # Transaction distribution -system.iobus.trans_dist::ReadResp 40253 # Transaction distribution -system.iobus.trans_dist::WriteReq 136515 # Transaction distribution -system.iobus.trans_dist::WriteResp 136515 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 57027218 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40168 # Transaction distribution +system.iobus.trans_dist::ReadResp 40168 # Transaction distribution +system.iobus.trans_dist::WriteReq 136429 # Transaction distribution +system.iobus.trans_dist::WriteResp 136429 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47254 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -655,13 +654,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230978 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230978 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353194 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47274 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -674,56 +673,56 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155266 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115470 # number of replacements -system.iocache.tags.tagsinuse 10.454534 # Cycle average of tags in use +system.iobus.pkt_size::total 7491696 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115471 # number of replacements +system.iocache.tags.tagsinuse 10.402763 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.524459 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.930076 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220279 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433130 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653408 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13082091783509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.557357 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.845405 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222335 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.427838 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.650173 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039749 # Number of tag accesses -system.iocache.tags.data_accesses 1039749 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039758 # Number of tag accesses +system.iocache.tags.data_accesses 1039758 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8825 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8862 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses -system.iocache.demand_misses::total 115528 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115489 # number of demand (read+write) misses +system.iocache.demand_misses::total 115529 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115488 # number of overall misses -system.iocache.overall_misses::total 115528 # number of overall misses +system.iocache.overall_misses::realview.ide 115489 # number of overall misses +system.iocache.overall_misses::total 115529 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8825 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8862 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115489 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115529 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115489 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115529 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -745,71 +744,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.membus.snoop_filter.tot_requests 3698370 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1836830 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_requests 4206457 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2089632 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76703 # Transaction distribution -system.membus.trans_dist::ReadResp 497652 # Transaction distribution -system.membus.trans_dist::WriteReq 33618 # Transaction distribution -system.membus.trans_dist::WriteResp 33618 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1591541 # Transaction distribution -system.membus.trans_dist::CleanEvict 206888 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4346 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38191 # Transaction distribution +system.membus.trans_dist::ReadResp 527322 # Transaction distribution +system.membus.trans_dist::WriteReq 33519 # Transaction distribution +system.membus.trans_dist::WriteResp 33519 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1804108 # Transaction distribution +system.membus.trans_dist::CleanEvict 249631 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4439 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4347 # Transaction distribution -system.membus.trans_dist::ReadExReq 826102 # Transaction distribution -system.membus.trans_dist::ReadExResp 826102 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420949 # Transaction distribution -system.membus.trans_dist::InvalidateReq 648543 # Transaction distribution -system.membus.trans_dist::InvalidateResp 648543 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4440 # Transaction distribution +system.membus.trans_dist::ReadExReq 981656 # Transaction distribution +system.membus.trans_dist::ReadExResp 981656 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 489131 # Transaction distribution +system.membus.trans_dist::InvalidateReq 677491 # Transaction distribution +system.membus.trans_dist::InvalidateResp 677491 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122136 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6726 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5343163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5472427 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5818953 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6027224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6156066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6502595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155266 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 174471520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 174640714 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7391488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 182032202 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202241248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202409942 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7391552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 209801494 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3808691 # Request fanout histogram -system.membus.snoop_fanout::mean 0.010569 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.102262 # Request fanout histogram +system.membus.snoop_fanout::samples 4278167 # Request fanout histogram +system.membus.snoop_fanout::mean 0.008735 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.093051 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3768436 98.94% 98.94% # Request fanout histogram -system.membus.snoop_fanout::1 40255 1.06% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4240798 99.13% 99.13% # Request fanout histogram +system.membus.snoop_fanout::1 37369 0.87% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3808691 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 4278167 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -819,11 +818,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -852,28 +851,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |