diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | 5314 |
1 files changed, 2647 insertions, 2667 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index f3542cbe8..79f197f5c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.579919 # Number of seconds simulated -sim_ticks 47579919171500 # Number of ticks simulated -final_tick 47579919171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.460623 # Number of seconds simulated +sim_ticks 47460623015500 # Number of ticks simulated +final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 994477 # Simulator instruction rate (inst/s) -host_op_rate 1169790 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52043300787 # Simulator tick rate (ticks/s) -host_mem_usage 760992 # Number of bytes of host memory used -host_seconds 914.24 # Real time elapsed on the host -sim_insts 909188095 # Number of instructions simulated -sim_ops 1069465904 # Number of ops (including micro ops) simulated +host_inst_rate 557401 # Simulator instruction rate (inst/s) +host_op_rate 655644 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30226773681 # Simulator tick rate (ticks/s) +host_mem_usage 730476 # Number of bytes of host memory used +host_seconds 1570.15 # Real time elapsed on the host +sim_insts 875204273 # Number of instructions simulated +sim_ops 1029460892 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 95808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 82560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3301172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14310344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 18775424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 218368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 230464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3000056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 12646096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 13033600 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory -system.physmem.bytes_read::total 66121412 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3301172 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3000056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6301228 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 84303296 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 81920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 78144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3183732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 11874696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 12415040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 115712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 117120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2511992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9752208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 13330752 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 455552 # Number of bytes read from this memory +system.physmem.bytes_read::total 53916868 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3183732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2511992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5695724 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 73320768 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 84323880 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 91988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 223612 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 293366 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3412 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 46964 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 197608 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 203650 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1073668 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1317239 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 73341352 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1280 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1221 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 90153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 185555 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 193985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1830 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 152391 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 208293 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 882972 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1145637 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1319813 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 69382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 300764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 394608 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63053 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 265786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 273931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1389692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69382 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 132435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1771825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1148211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 67082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 250201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 261586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 205480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 280880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1136034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 67082 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 120009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1544876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1772258 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1771825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 301197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 394608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 265786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 273931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3161949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1073668 # Number of read requests accepted -system.physmem.writeReqs 1319813 # Number of write requests accepted -system.physmem.readBursts 1073668 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1319813 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 68691008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23744 # Total number of bytes read from write queue -system.physmem.bytesWritten 84321664 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 66121412 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 84323880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 371 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1545310 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1544876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 67082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 250635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 261586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 205480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 280880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2681343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 882972 # Number of read requests accepted +system.physmem.writeReqs 1148211 # Number of write requests accepted +system.physmem.readBursts 882972 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1148211 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 56486656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue +system.physmem.bytesWritten 73339968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 53916868 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 73341352 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 64017 # Per bank write bursts -system.physmem.perBankRdBursts::1 68044 # Per bank write bursts -system.physmem.perBankRdBursts::2 61517 # Per bank write bursts -system.physmem.perBankRdBursts::3 65955 # Per bank write bursts -system.physmem.perBankRdBursts::4 65874 # Per bank write bursts -system.physmem.perBankRdBursts::5 75726 # Per bank write bursts -system.physmem.perBankRdBursts::6 64933 # Per bank write bursts -system.physmem.perBankRdBursts::7 65424 # Per bank write bursts -system.physmem.perBankRdBursts::8 62003 # Per bank write bursts -system.physmem.perBankRdBursts::9 113372 # Per bank write bursts -system.physmem.perBankRdBursts::10 63434 # Per bank write bursts -system.physmem.perBankRdBursts::11 64718 # Per bank write bursts -system.physmem.perBankRdBursts::12 56904 # Per bank write bursts -system.physmem.perBankRdBursts::13 64084 # Per bank write bursts -system.physmem.perBankRdBursts::14 56898 # Per bank write bursts -system.physmem.perBankRdBursts::15 60394 # Per bank write bursts -system.physmem.perBankWrBursts::0 80527 # Per bank write bursts -system.physmem.perBankWrBursts::1 85904 # Per bank write bursts -system.physmem.perBankWrBursts::2 80420 # Per bank write bursts -system.physmem.perBankWrBursts::3 86054 # Per bank write bursts -system.physmem.perBankWrBursts::4 85401 # Per bank write bursts -system.physmem.perBankWrBursts::5 88715 # Per bank write bursts -system.physmem.perBankWrBursts::6 80808 # Per bank write bursts -system.physmem.perBankWrBursts::7 81222 # Per bank write bursts -system.physmem.perBankWrBursts::8 80522 # Per bank write bursts -system.physmem.perBankWrBursts::9 87926 # Per bank write bursts -system.physmem.perBankWrBursts::10 79616 # Per bank write bursts -system.physmem.perBankWrBursts::11 81105 # Per bank write bursts -system.physmem.perBankWrBursts::12 77689 # Per bank write bursts -system.physmem.perBankWrBursts::13 84231 # Per bank write bursts -system.physmem.perBankWrBursts::14 77252 # Per bank write bursts -system.physmem.perBankWrBursts::15 80134 # Per bank write bursts +system.physmem.perBankRdBursts::0 53897 # Per bank write bursts +system.physmem.perBankRdBursts::1 57581 # Per bank write bursts +system.physmem.perBankRdBursts::2 50596 # Per bank write bursts +system.physmem.perBankRdBursts::3 56941 # Per bank write bursts +system.physmem.perBankRdBursts::4 52224 # Per bank write bursts +system.physmem.perBankRdBursts::5 57867 # Per bank write bursts +system.physmem.perBankRdBursts::6 48622 # Per bank write bursts +system.physmem.perBankRdBursts::7 53589 # Per bank write bursts +system.physmem.perBankRdBursts::8 50057 # Per bank write bursts +system.physmem.perBankRdBursts::9 95322 # Per bank write bursts +system.physmem.perBankRdBursts::10 46946 # Per bank write bursts +system.physmem.perBankRdBursts::11 52908 # Per bank write bursts +system.physmem.perBankRdBursts::12 47194 # Per bank write bursts +system.physmem.perBankRdBursts::13 52526 # Per bank write bursts +system.physmem.perBankRdBursts::14 52237 # Per bank write bursts +system.physmem.perBankRdBursts::15 54097 # Per bank write bursts +system.physmem.perBankWrBursts::0 68696 # Per bank write bursts +system.physmem.perBankWrBursts::1 73430 # Per bank write bursts +system.physmem.perBankWrBursts::2 69832 # Per bank write bursts +system.physmem.perBankWrBursts::3 74009 # Per bank write bursts +system.physmem.perBankWrBursts::4 72053 # Per bank write bursts +system.physmem.perBankWrBursts::5 74820 # Per bank write bursts +system.physmem.perBankWrBursts::6 69700 # Per bank write bursts +system.physmem.perBankWrBursts::7 72497 # Per bank write bursts +system.physmem.perBankWrBursts::8 69824 # Per bank write bursts +system.physmem.perBankWrBursts::9 74930 # Per bank write bursts +system.physmem.perBankWrBursts::10 66965 # Per bank write bursts +system.physmem.perBankWrBursts::11 71787 # Per bank write bursts +system.physmem.perBankWrBursts::12 69900 # Per bank write bursts +system.physmem.perBankWrBursts::13 73092 # Per bank write bursts +system.physmem.perBankWrBursts::14 71437 # Per bank write bursts +system.physmem.perBankWrBursts::15 72965 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 116 # Number of times write queue was full causing retry -system.physmem.totGap 47579915806000 # Total gap between requests +system.physmem.numWrRetry 49 # Number of times write queue was full causing retry +system.physmem.totGap 47460619650000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1030443 # Read request sizes (log2) +system.physmem.readPktSize::6 839747 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1317239 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 761963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 94096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 44762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 33193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 29336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 25572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 22083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1145637 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 632223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 27029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 24072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 21057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -188,168 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 42279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 54831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 58608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 69713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 74423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 78144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 80302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 80268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 82803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 85991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 84137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 91440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 82956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 77042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 74792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 302 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1107709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 138.133954 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 95.206974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.490982 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 762645 68.85% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 210995 19.05% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48832 4.41% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22284 2.01% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16979 1.53% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10320 0.93% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6180 0.56% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5743 0.52% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23731 2.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1107709 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 70958 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.125666 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 121.252784 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 70954 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 33201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 52179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 63950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 69091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 68874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 71191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 73992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 71007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 71950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 78189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 71162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 64454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 141 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 939668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 138.161751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 95.082106 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 185.728908 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 647019 68.86% 68.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 180648 19.22% 88.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 40379 4.30% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17830 1.90% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14299 1.52% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8441 0.90% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5223 0.56% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4905 0.52% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20924 2.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 939668 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60779 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.521496 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.920998 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60776 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 70958 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 70958 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.567688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.991036 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.306981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 58539 82.50% 82.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9965 14.04% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 642 0.90% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 182 0.26% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 135 0.19% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 121 0.17% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 191 0.27% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 83 0.12% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 286 0.40% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 59 0.08% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 34 0.05% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 42 0.06% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 259 0.37% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 42 0.06% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 31 0.04% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 116 0.16% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 167 0.24% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60779 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60779 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.854160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.212866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.632019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48749 80.21% 80.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9610 15.81% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 589 0.97% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 189 0.31% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 137 0.23% 97.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 124 0.20% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 218 0.36% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 91 0.15% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 270 0.44% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 61 0.10% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 30 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 50 0.08% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 255 0.42% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 52 0.09% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 99 0.16% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 170 0.28% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 22 0.04% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 70958 # Writes before turning the bus around for reads -system.physmem.totQLat 35332291342 # Total ticks spent queuing -system.physmem.totMemAccLat 55456610092 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5366485000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32919.40 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60779 # Writes before turning the bus around for reads +system.physmem.totQLat 27990688881 # Total ticks spent queuing +system.physmem.totMemAccLat 44539513881 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4413020000 # Total ticks spent in databus transfers +system.physmem.avgQLat 31713.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51669.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.77 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 50463.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing -system.physmem.readRowHits 793862 # Number of row buffer hits during reads -system.physmem.writeRowHits 489250 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.13 # Row buffer hit rate for writes -system.physmem.avgGap 19878961.15 # Average gap between requests -system.physmem.pageHitRate 53.67 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4296030480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2344064250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4145606400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4335450480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1225363115070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27473067932250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31821240813090 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.795690 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45703113685218 # Time in different power states -system.physmem_0.memoryStateTime::REF 1588797860000 # Time in different power states +system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing +system.physmem.readRowHits 659544 # Number of row buffer hits during reads +system.physmem.writeRowHits 429323 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.46 # Row buffer hit rate for writes +system.physmem.avgGap 23365998.85 # Average gap between requests +system.physmem.pageHitRate 53.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3575759040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1951059000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3364272600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3726194400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1199863250505 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27423860344500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31736237846445 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.685699 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45621402632571 # Time in different power states +system.physmem_0.memoryStateTime::REF 1584814400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 288003145282 # Time in different power states +system.physmem_0.memoryStateTime::ACT 254405603429 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4078249560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2225235375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4226055600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4202118000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3107688614160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1219254807825 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27478426088250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31820101168770 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.771738 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45712034121275 # Time in different power states -system.physmem_1.memoryStateTime::REF 1588797860000 # Time in different power states +system.physmem_1.actEnergy 3528047880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1925026125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3519999600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3699373680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3099896966400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1198418138910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27425127986250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31736115538845 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.683122 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45623502554973 # Time in different power states +system.physmem_1.memoryStateTime::REF 1584814400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 279086495725 # Time in different power states +system.physmem_1.memoryStateTime::ACT 252305273527 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -413,70 +409,69 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 116306 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 116306 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10885 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88573 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 116284 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.223591 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 76.245351 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 116283 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 102194 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 102194 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9208 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76624 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 102185 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.254440 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 81.335431 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 102184 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 116284 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 99480 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22519.581825 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21136.105654 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15840.339731 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 98726 99.24% 99.24% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 154 0.15% 99.40% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 495 0.50% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 15 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 37 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 102185 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22586.042800 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20965.618936 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16893.735669 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 85046 99.07% 99.07% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 170 0.20% 99.27% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 522 0.61% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 25 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 28 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 99480 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 8374009004 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.680543 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.466266 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2675132860 31.95% 31.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 5698876144 68.05% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 8374009004 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 88573 89.06% 89.06% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10885 10.94% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 99458 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116306 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 85841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 4536625496 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.282786 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.450353 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 3253731032 71.72% 71.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 1282894464 28.28% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 4536625496 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 76625 89.27% 89.27% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9208 10.73% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85833 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 102194 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116306 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 99458 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 102194 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85833 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 99458 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 215764 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85833 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 188027 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86290817 # DTB read hits -system.cpu0.dtb.read_misses 86990 # DTB read misses -system.cpu0.dtb.write_hits 77965379 # DTB write hits -system.cpu0.dtb.write_misses 29316 # DTB write misses +system.cpu0.dtb.read_hits 85563003 # DTB read hits +system.cpu0.dtb.read_misses 75756 # DTB read misses +system.cpu0.dtb.write_hits 77475573 # DTB write hits +system.cpu0.dtb.write_misses 26438 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36691 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34001 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4448 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4044 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9789 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86377807 # DTB read accesses -system.cpu0.dtb.write_accesses 77994695 # DTB write accesses +system.cpu0.dtb.perms_faults 8915 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85638759 # DTB read accesses +system.cpu0.dtb.write_accesses 77502011 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 164256196 # DTB hits -system.cpu0.dtb.misses 116306 # DTB misses -system.cpu0.dtb.accesses 164372502 # DTB accesses +system.cpu0.dtb.hits 163038576 # DTB hits +system.cpu0.dtb.misses 102194 # DTB misses +system.cpu0.dtb.accesses 163140770 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -506,239 +501,235 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 53337 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53337 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 559 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47077 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 53337 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53337 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53337 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 47636 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25421.330506 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23137.989766 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 22597.528238 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 46963 98.59% 98.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 37 0.08% 98.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 536 1.13% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 19 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 27 0.06% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 47636 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 56381 # Table walker walks requested +system.cpu0.itb.walker.walksLong 56381 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 642 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50009 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 56381 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 56381 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 56381 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 50651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25304.495469 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23033.115990 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 21560.503846 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 49913 98.54% 98.54% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 55 0.11% 98.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 593 1.17% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 11 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 28 0.06% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 34 0.07% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 50651 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 47077 98.83% 98.83% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 559 1.17% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 47636 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 50009 98.73% 98.73% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 642 1.27% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 50651 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53337 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53337 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56381 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56381 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47636 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47636 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 100973 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 461259285 # ITB inst hits -system.cpu0.itb.inst_misses 53337 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50651 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50651 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 107032 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 455204971 # ITB inst hits +system.cpu0.itb.inst_misses 56381 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25459 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24108 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 461312622 # ITB inst accesses -system.cpu0.itb.hits 461259285 # DTB hits -system.cpu0.itb.misses 53337 # DTB misses -system.cpu0.itb.accesses 461312622 # DTB accesses -system.cpu0.numCycles 95159838338 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 455261352 # ITB inst accesses +system.cpu0.itb.hits 455204971 # DTB hits +system.cpu0.itb.misses 56381 # DTB misses +system.cpu0.itb.accesses 455261352 # DTB accesses +system.cpu0.numCycles 94921246031 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13594 # number of quiesce instructions executed -system.cpu0.committedInsts 460977499 # Number of instructions committed -system.cpu0.committedOps 540688150 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 495872658 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 377758 # Number of float alu accesses -system.cpu0.num_func_calls 27096084 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 70442961 # number of instructions that are conditional controls -system.cpu0.num_int_insts 495872658 # number of integer instructions -system.cpu0.num_fp_insts 377758 # number of float instructions -system.cpu0.num_int_register_reads 724744849 # number of times the integer registers were read -system.cpu0.num_int_register_writes 393986605 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 623895 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 289632 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 122670714 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 122315787 # number of times the CC registers were written -system.cpu0.num_mem_refs 164249297 # number of memory refs -system.cpu0.num_load_insts 86287437 # Number of load instructions -system.cpu0.num_store_insts 77961860 # Number of store instructions -system.cpu0.num_idle_cycles 93938070746.252213 # Number of idle cycles -system.cpu0.num_busy_cycles 1221767591.747779 # Number of busy cycles -system.cpu0.not_idle_fraction 0.012839 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.987161 # Percentage of idle cycles -system.cpu0.Branches 102925889 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 375485543 69.40% 69.40% # Class of executed instruction -system.cpu0.op_class::IntMult 1178634 0.22% 69.62% # Class of executed instruction -system.cpu0.op_class::IntDiv 59866 0.01% 69.63% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 39720 0.01% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction -system.cpu0.op_class::MemRead 86287437 15.95% 85.59% # Class of executed instruction -system.cpu0.op_class::MemWrite 77961860 14.41% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 13214 # number of quiesce instructions executed +system.cpu0.committedInsts 454926589 # Number of instructions committed +system.cpu0.committedOps 534313943 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 491049300 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 395385 # Number of float alu accesses +system.cpu0.num_func_calls 27308099 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68959046 # number of instructions that are conditional controls +system.cpu0.num_int_insts 491049300 # number of integer instructions +system.cpu0.num_fp_insts 395385 # number of float instructions +system.cpu0.num_int_register_reads 709557386 # number of times the integer registers were read +system.cpu0.num_int_register_writes 389375063 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 654866 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 293356 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117980325 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117652107 # number of times the CC registers were written +system.cpu0.num_mem_refs 163029477 # number of memory refs +system.cpu0.num_load_insts 85557806 # Number of load instructions +system.cpu0.num_store_insts 77471671 # Number of store instructions +system.cpu0.num_idle_cycles 93727706914.782028 # Number of idle cycles +system.cpu0.num_busy_cycles 1193539116.217975 # Number of busy cycles +system.cpu0.not_idle_fraction 0.012574 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.987426 # Percentage of idle cycles +system.cpu0.Branches 101606994 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 370328410 69.27% 69.27% # Class of executed instruction +system.cpu0.op_class::IntMult 1177627 0.22% 69.49% # Class of executed instruction +system.cpu0.op_class::IntDiv 60510 0.01% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 39424 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::MemRead 85557806 16.00% 85.51% # Class of executed instruction +system.cpu0.op_class::MemWrite 77471671 14.49% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 541013060 # Class of executed instruction -system.cpu0.dcache.tags.replacements 5729731 # number of replacements -system.cpu0.dcache.tags.tagsinuse 475.426094 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 158277130 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5730241 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.621374 # Average number of references to valid blocks. +system.cpu0.op_class::total 534635449 # Class of executed instruction +system.cpu0.dcache.tags.replacements 5459134 # number of replacements +system.cpu0.dcache.tags.tagsinuse 479.881862 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 157334556 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5459646 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.817721 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.426094 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.928567 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.928567 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 334208607 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 334208607 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80244173 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80244173 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73488227 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73488227 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200421 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 200421 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 184838 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 184838 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1883304 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1883304 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1842196 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1842196 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153732400 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153732400 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153932821 # number of overall hits -system.cpu0.dcache.overall_hits::total 153932821 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3080001 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3080001 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1447988 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1447988 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 695954 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 695954 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 768699 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 768699 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 158470 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 158470 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198134 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 198134 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4527989 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4527989 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5223943 # number of overall misses -system.cpu0.dcache.overall_misses::total 5223943 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52478340000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52478340000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 38322628500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 38322628500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 49559521500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 49559521500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2516267500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2516267500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5589291500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5589291500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2738500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2738500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 90800968500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 90800968500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 90800968500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 90800968500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83324174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83324174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74936215 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74936215 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 896375 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 896375 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 953537 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 953537 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2041774 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2041774 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2040330 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2040330 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 158260389 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 158260389 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 159156764 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 159156764 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036964 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036964 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019323 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.019323 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.776409 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.776409 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.806155 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.806155 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077614 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077614 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097109 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097109 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028611 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028611 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032823 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032823 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17038.416546 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17038.416546 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26466.122993 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 26466.122993 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 64471.947407 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 64471.947407 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15878.510128 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15878.510128 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28209.653568 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28209.653568 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.881862 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937269 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.937269 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 331496751 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 331496751 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 79723477 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79723477 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73152105 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73152105 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199556 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 199556 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 181390 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 181390 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847375 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1847375 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1814831 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1814831 # 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number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 159632 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191006 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 191006 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4334677 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4334677 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4954267 # number of overall misses +system.cpu0.dcache.overall_misses::total 4954267 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47916762500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 47916762500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34952130000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34952130000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46124909500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 46124909500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2449383000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2449383000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5329904000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5329904000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5776000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5776000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 82868892500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 82868892500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 82868892500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 82868892500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82707420 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82707420 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74502839 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74502839 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 819146 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 819146 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 931520 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 931520 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2007007 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2007007 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2005837 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2005837 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 157210259 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 157210259 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 158029405 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 158029405 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036078 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036078 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018130 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018130 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756385 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756385 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.805275 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.805275 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079537 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079537 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095225 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095225 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027572 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027572 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031350 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031350 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16058.203022 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16058.203022 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25876.397573 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25876.397573 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 61489.221202 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 61489.221202 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15343.934800 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15343.934800 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27904.379967 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27904.379967 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20053.266141 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20053.266141 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17381.692048 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17381.692048 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19117.662631 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19117.662631 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16726.771589 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16726.771589 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -747,158 +738,157 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5729731 # number of writebacks -system.cpu0.dcache.writebacks::total 5729731 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28073 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 28073 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21239 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21239 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41058 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41058 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 49312 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 49312 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 49312 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 49312 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3051928 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3051928 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1426749 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1426749 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 694810 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 694810 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 768699 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 768699 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117412 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117412 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 198134 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 198134 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4478677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4478677 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5173487 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5173487 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 28514 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 28514 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 27871 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27871 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 56385 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 56385 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47315434500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47315434500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36384996000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36384996000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17003029000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17003029000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 48790822500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 48790822500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1643233500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1643233500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5391195500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5391195500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2700500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2700500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83700430500 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036627 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036627 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019040 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019040 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775133 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775133 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.806155 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.806155 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097109 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097109 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028299 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028299 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032506 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032506 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15503.456995 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15503.456995 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25502.030140 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25502.030140 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24471.479973 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24471.479973 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 63471.947407 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 63471.947407 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13995.447654 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13995.447654 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27209.845357 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27209.845357 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5459134 # 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number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2959708 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1329332 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1329332 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 618446 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 618446 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 750130 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 750130 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 116332 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116332 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191006 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 191006 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4289040 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4289040 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4907486 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4907486 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29450 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29450 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28924 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28924 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 58374 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58374 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43283569500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43283569500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33090463000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33090463000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14878889500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14878889500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45374779500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45374779500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1623777500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1623777500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5138961000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5138961000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5713000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5713000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 76374032500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 76374032500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91252922000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 91252922000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5439516500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5439516500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5307758000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5307758000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10747274500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10747274500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035785 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035785 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017843 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017843 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754989 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754989 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.805275 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.805275 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057963 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057963 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095225 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095225 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027282 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031054 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031054 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14624.270198 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14624.270198 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24892.549792 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24892.549792 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24058.510363 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24058.510363 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60489.221202 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60489.221202 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13958.132758 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13958.132758 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26904.709800 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26904.709800 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18688.650800 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18688.650800 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19465.296714 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19465.296714 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185184.523392 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185184.523392 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182514.082738 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182514.082738 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183864.529573 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 183864.529573 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17806.789515 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17806.789515 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18594.637254 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18594.637254 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184703.446520 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184703.446520 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 183507.052966 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183507.052966 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184110.640011 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184110.640011 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4741257 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.854043 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 456517510 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4741769 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 96.275780 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 5000286 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.853700 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 450204172 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5000798 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 90.026466 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 46470060000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.854043 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999715 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999715 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.853700 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999714 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999714 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # 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average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11365.051800 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11365.051800 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11365.051800 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 915410741 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 915410741 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 450204172 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 450204172 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 450204172 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 450204172 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 450204172 # number of overall hits +system.cpu0.icache.overall_hits::total 450204172 # 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number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 455204971 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 455204971 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 455204971 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 455204971 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 455204971 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 455204971 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010986 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010986 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010986 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010986 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010986 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 51519631500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51519631500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 51519631500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51519631500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 51519631500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 52987673000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 52987673000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 52987673000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 52987673000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 52987673000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 52987673000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010280 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010280 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010280 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010280 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10865.051906 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10865.051906 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10865.051906 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10865.051906 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010986 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010986 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010986 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010986 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10595.841385 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10595.841385 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10595.841385 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8039497 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8039521 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7383328 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7383330 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1012143 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2514209 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16169.325614 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 14408578 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2529817 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.695502 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 974782 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2298690 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16186.717586 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 14759696 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2314768 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.376318 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 8106870500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15164.632353 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 45.004325 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 56.118535 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 903.570401 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.925576 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002747 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003425 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.055150 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986897 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1599 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13927 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 253 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 682 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 664 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 76 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2528 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5951 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5308 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.097595 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.850037 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 356318803 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 356318803 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 276065 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 135571 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 411636 # 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number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10002 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7458 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 17460 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 252814 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 252814 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 198129 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 198129 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 262789 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 262789 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 467509 # 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number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7458 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 467509 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1245407 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1730376 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 427118500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 335132000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 762250500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3305201500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3305201500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2087626000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2087626000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2642498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2642498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18677102500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 18677102500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18746620500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 18746620500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41394693000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41394693000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 415110500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 415110500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 427118500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 335132000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 18746620500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 60071795500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 79580666500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 427118500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 335132000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 18746620500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 60071795500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 79580666500 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 286067 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 143029 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 429096 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3830429 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3830429 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 6639546 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 6639546 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 253314 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 253314 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 198129 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 198129 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1192750 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1192750 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4741775 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 4741775 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3864150 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 3864150 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 766846 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1043 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4210 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6256 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080872 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897156 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 354680611 # 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number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190989 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 190989 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 17 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 17 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1106507 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1106507 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5000799 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5000799 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3694486 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3694486 # 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mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998394 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998394 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212204 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212204 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254110 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254110 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.778461 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.778461 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.168169 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.034964 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052143 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098594 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244226 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221718 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221718 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091775 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.245719 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245719 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755778 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755778 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159779 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039628 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050848 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091775 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240188 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.246709 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 37656.958763 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69416.351262 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30104.940787 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30104.940787 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19703.980740 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19703.980740 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 482899.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 482899.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62918.364243 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62918.364243 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34098.951036 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36088.202106 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36088.202106 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71877.062952 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71877.062952 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39511.624446 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36703.309338 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38935.907750 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34098.951036 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41586.766119 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69416.351262 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49031.784454 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226157 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35218.843326 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55618.555748 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30327.980817 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30327.980817 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19401.010006 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19401.010006 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 308176.294118 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 308176.294118 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57887.022480 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57887.022480 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33672.786836 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33686.225156 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33686.225156 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70074.831676 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70074.831676 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37342.411589 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34090.241397 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36649.993487 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33672.786836 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38834.979997 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55618.555748 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42706.485834 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177171.722663 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149117.743129 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175001.040508 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175001.040508 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176686.417657 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149282.624871 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175993.534781 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 175993.534781 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176098.758535 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156367.199276 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176343.097955 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 156894.388122 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 21737448 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11172038 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879362 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879064 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_requests 21678176 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128402 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 962 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1759585 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1759287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 298 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 568365 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9266330 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 27872 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 27871 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5482404 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6640558 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2386717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 980471 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 448075 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 360841 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 517122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1223880 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1201425 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4741775 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4748017 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 819035 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 766846 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14311056 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18559366 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 302345 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 623475 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 33796242 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607086484 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696970881 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1144232 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2288536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1307490133 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6577979 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 17957076 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.118626 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.323399 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 537700 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9321471 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28925 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28924 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5081322 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6856856 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2248329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 834929 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 427184 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348871 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 496915 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1135852 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1114697 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5000799 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4556956 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 799366 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 748142 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15088134 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17701155 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 319339 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542421 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 33651049 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 640241940 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 663021135 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1207824 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1965272 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1306436171 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6076867 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 17397758 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.114750 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.318774 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15827205 88.14% 88.14% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2129573 11.86% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15401663 88.53% 88.53% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1995797 11.47% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 298 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 17957076 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 21527019496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 17397758 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 21478508994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 184192978 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 177190009 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7155786000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7544323500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8237151691 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7836374127 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 159316000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 168361000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 337408998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 296762000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1403,71 +1395,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 108188 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 108188 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9416 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83328 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 108184 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.073948 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 24.322514 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 108183 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 108457 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 108457 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9827 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84631 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 108435 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.073777 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.294348 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 108434 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 108184 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 92748 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25260.781904 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21819.891311 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 28424.827210 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 90515 97.59% 97.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.18% 97.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1735 1.87% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 64 0.07% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.12% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.05% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 73 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 92748 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -800290088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean -1.452962 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1963081332 245.30% 245.30% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1162791244 -145.30% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -800290088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 83329 89.85% 89.85% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9416 10.15% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 92745 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 108435 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 94480 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23264.092930 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21359.678554 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 19330.218287 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 93351 98.81% 98.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 176 0.19% 98.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 798 0.84% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 94480 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 3353012192 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.550742 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1846644332 -55.07% -55.07% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 5199656524 155.07% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 3353012192 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 84631 89.60% 89.60% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9827 10.40% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 94458 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108457 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108188 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92745 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108457 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 94458 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92745 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 200933 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 94458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 202915 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84911532 # DTB read hits -system.cpu1.dtb.read_misses 79075 # DTB read misses -system.cpu1.dtb.write_hits 77663318 # DTB write hits -system.cpu1.dtb.write_misses 29113 # DTB write misses +system.cpu1.dtb.read_hits 79507348 # DTB read hits +system.cpu1.dtb.read_misses 80723 # DTB read misses +system.cpu1.dtb.write_hits 72319570 # DTB write hits +system.cpu1.dtb.write_misses 27734 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39584 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39844 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5277 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4607 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10813 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 84990607 # DTB read accesses -system.cpu1.dtb.write_accesses 77692431 # DTB write accesses +system.cpu1.dtb.perms_faults 10580 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 79588071 # DTB read accesses +system.cpu1.dtb.write_accesses 72347304 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162574850 # DTB hits -system.cpu1.dtb.misses 108188 # DTB misses -system.cpu1.dtb.accesses 162683038 # DTB accesses +system.cpu1.dtb.hits 151826918 # DTB hits +system.cpu1.dtb.misses 108457 # DTB misses +system.cpu1.dtb.accesses 151935375 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1497,239 +1487,236 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 63937 # Table walker walks requested -system.cpu1.itb.walker.walksLong 63937 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 631 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57861 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 63937 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 63937 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 63937 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 58492 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 30403.747521 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24852.510144 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 37514.660324 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 55985 95.71% 95.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 47 0.08% 95.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 2099 3.59% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.15% 99.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 102 0.17% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 51 0.09% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 79 0.14% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 15 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 17 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 58492 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 59789 # Table walker walks requested +system.cpu1.itb.walker.walksLong 59789 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 555 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54230 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 59789 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 59789 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 59789 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 54785 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26806.178699 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23797.611376 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 25937.791406 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 53612 97.86% 97.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 36 0.07% 97.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 992 1.81% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 28 0.05% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 57 0.10% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 37 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 54785 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1988115332 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1988115332 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -1988115332 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 57861 98.92% 98.92% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 631 1.08% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 58492 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 54230 98.99% 98.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 555 1.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 54785 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63937 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63937 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59789 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59789 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58492 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58492 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 122429 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 448499634 # ITB inst hits -system.cpu1.itb.inst_misses 63937 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54785 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54785 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 114574 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 420546617 # ITB inst hits +system.cpu1.itb.inst_misses 59789 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 43834 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 27923 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 40703 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1030 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27682 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448563571 # ITB inst accesses -system.cpu1.itb.hits 448499634 # DTB hits -system.cpu1.itb.misses 63937 # DTB misses -system.cpu1.itb.accesses 448563571 # DTB accesses -system.cpu1.numCycles 95159838343 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 420606406 # ITB inst accesses +system.cpu1.itb.hits 420546617 # DTB hits +system.cpu1.itb.misses 59789 # DTB misses +system.cpu1.itb.accesses 420606406 # DTB accesses +system.cpu1.numCycles 94920662633 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5923 # number of quiesce instructions executed -system.cpu1.committedInsts 448210596 # Number of instructions committed -system.cpu1.committedOps 528777754 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 486415785 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 519922 # Number of float alu accesses -system.cpu1.num_func_calls 27136019 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67942031 # number of instructions that are conditional controls -system.cpu1.num_int_insts 486415785 # number of integer instructions -system.cpu1.num_fp_insts 519922 # number of float instructions -system.cpu1.num_int_register_reads 706615491 # number of times the integer registers were read -system.cpu1.num_int_register_writes 385601488 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 832776 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 452540 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 115428294 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 115157338 # number of times the CC registers were written -system.cpu1.num_mem_refs 162566757 # number of memory refs -system.cpu1.num_load_insts 84909557 # Number of load instructions -system.cpu1.num_store_insts 77657200 # Number of store instructions -system.cpu1.num_idle_cycles 94045434394.442017 # Number of idle cycles -system.cpu1.num_busy_cycles 1114403948.557976 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011711 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988289 # Percentage of idle cycles -system.cpu1.Branches 99989008 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 365279701 69.04% 69.04% # Class of executed instruction -system.cpu1.op_class::IntMult 1087060 0.21% 69.25% # Class of executed instruction -system.cpu1.op_class::IntDiv 61840 0.01% 69.26% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 71500 0.01% 69.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.27% # Class of executed instruction -system.cpu1.op_class::MemRead 84909557 16.05% 85.32% # Class of executed instruction -system.cpu1.op_class::MemWrite 77657200 14.68% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 5531 # number of quiesce instructions executed +system.cpu1.committedInsts 420277684 # Number of instructions committed +system.cpu1.committedOps 495146949 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 454880180 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 506575 # Number of float alu accesses +system.cpu1.num_func_calls 25039229 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 63957319 # number of instructions that are conditional controls +system.cpu1.num_int_insts 454880180 # number of integer instructions +system.cpu1.num_fp_insts 506575 # number of float instructions +system.cpu1.num_int_register_reads 664278142 # number of times the integer registers were read +system.cpu1.num_int_register_writes 361063382 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 809640 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 450820 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 110083158 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 109779727 # number of times the CC registers were written +system.cpu1.num_mem_refs 151817768 # number of memory refs +system.cpu1.num_load_insts 79504880 # Number of load instructions +system.cpu1.num_store_insts 72312888 # Number of store instructions +system.cpu1.num_idle_cycles 93883487625.302155 # Number of idle cycles +system.cpu1.num_busy_cycles 1037175007.697842 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010927 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989073 # Percentage of idle cycles +system.cpu1.Branches 93646526 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 342430715 69.12% 69.12% # Class of executed instruction +system.cpu1.op_class::IntMult 1035788 0.21% 69.33% # Class of executed instruction +system.cpu1.op_class::IntDiv 58966 0.01% 69.34% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.34% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 72713 0.01% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::MemRead 79504880 16.05% 85.40% # Class of executed instruction +system.cpu1.op_class::MemWrite 72312888 14.60% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 529066901 # Class of executed instruction -system.cpu1.dcache.tags.replacements 5332630 # number of replacements -system.cpu1.dcache.tags.tagsinuse 455.913081 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 157043226 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5333142 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.446661 # Average number of references to valid blocks. +system.cpu1.op_class::total 495415992 # Class of executed instruction +system.cpu1.dcache.tags.replacements 5111729 # number of replacements +system.cpu1.dcache.tags.tagsinuse 453.815972 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 146515734 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5112105 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.660549 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8395596843000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.913081 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890455 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.890455 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 330516943 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 330516943 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79081838 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79081838 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 73714078 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 73714078 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184325 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 184325 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 141992 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 141992 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768915 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1768915 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1742986 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1742986 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 152795916 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 152795916 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 152980241 # number of overall hits -system.cpu1.dcache.overall_hits::total 152980241 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3051137 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3051137 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1365469 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1365469 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 638330 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 638330 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 475836 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 475836 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 176856 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 176856 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201345 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 201345 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4416606 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4416606 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5054936 # number of overall misses -system.cpu1.dcache.overall_misses::total 5054936 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51930161500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 51930161500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 32223402000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 32223402000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17094390000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 17094390000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3024227500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3024227500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5760420500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5760420500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4429500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4429500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 84153563500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 84153563500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 84153563500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 84153563500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82132975 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82132975 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75079547 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75079547 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 822655 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 822655 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 617828 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 617828 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945771 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1945771 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944331 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1944331 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 157212522 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 157212522 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 158035177 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 158035177 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037149 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037149 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018187 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018187 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775939 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775939 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.770176 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.770176 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.090893 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.090893 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103555 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103555 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028093 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.028093 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031986 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031986 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17019.937649 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 17019.937649 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23598.779613 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23598.779613 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35924.961541 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35924.961541 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17099.942891 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17099.942891 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28609.702252 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28609.702252 # average StoreCondReq miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.815972 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886359 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.886359 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 373 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 308802786 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 308802786 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 74029008 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 74029008 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68561672 # 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number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2729020500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5550193500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5550193500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6333000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6333000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 75378951500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 75378951500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 75378951500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 75378951500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 76904053 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 76904053 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69874902 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69874902 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 797400 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 797400 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 628953 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 628953 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1797202 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1797202 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1795813 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1795813 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146778955 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146778955 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 147576355 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 147576355 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037385 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037385 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018794 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018794 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.785429 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.785429 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.768730 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.768730 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092098 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092098 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.107688 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.107688 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.028535 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032624 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.032624 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15749.154709 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15749.154709 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22920.145748 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22920.145748 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37427.166775 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37427.166775 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16487.657006 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16487.657006 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28699.930709 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28699.930709 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19053.898740 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19053.898740 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16647.799992 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16647.799992 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17997.612740 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17997.612740 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15656.404946 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15656.404946 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1738,157 +1725,156 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5332630 # number of writebacks -system.cpu1.dcache.writebacks::total 5332630 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 22206 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 22206 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 454 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 454 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46550 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46550 # 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number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1312828 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 626301 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 626301 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 483495 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 483495 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120540 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120540 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193387 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193387 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4171181 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4171181 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4797482 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4797482 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8711 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8711 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9093 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9093 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17804 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17804 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40977017000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40977017000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 28757951500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 28757951500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14279978500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14279978500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17612353000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17612353000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1713373500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1713373500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5356877500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5356877500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6262000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6262000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69734968500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 69734968500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84014947000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 84014947000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1460511000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1460511000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1571513500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1571513500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3032024500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3032024500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037168 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037168 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018788 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018788 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.785429 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.785429 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.768730 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.768730 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067071 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067071 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.107688 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.107688 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028418 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028418 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032508 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032508 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14335.883986 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14335.883986 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21905.345940 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21905.345940 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22800.504071 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22800.504071 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36427.166775 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36427.166775 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14214.148830 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14214.148830 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27700.297848 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27700.297848 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17695.527323 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17695.527323 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18616.275320 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18616.275320 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162817.765297 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162817.765297 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171484.884159 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171484.884159 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167249.193432 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167249.193432 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16718.279188 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16718.279188 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17512.300619 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17512.300619 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167662.840087 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167662.840087 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172826.734851 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172826.734851 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170300.185352 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170300.185352 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5368535 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.099630 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 443130586 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5369047 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 82.534309 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 4920276 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.059748 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 415625824 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4920788 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 84.463266 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8395565369000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.099630 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968945 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.968945 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.059748 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968867 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.968867 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 109 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 902368316 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 902368316 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 443130586 # 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average overall miss latency +system.cpu1.icache.tags.tag_accesses 846014027 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 846014027 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 415625824 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 415625824 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 415625824 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 415625824 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 415625824 # number of overall hits +system.cpu1.icache.overall_hits::total 415625824 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4920793 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4920793 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4920793 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4920793 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4920793 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10923.162994 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10923.162994 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10923.162994 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1897,253 +1883,248 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 5368535 # number of writebacks -system.cpu1.icache.writebacks::total 5368535 # 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number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4920793 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4920793 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56017036000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 56017036000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56017036000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 56017036000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56017036000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 56017036000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51290227500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 51290227500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51290227500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 51290227500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51290227500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 51290227500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14763500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14763500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14763500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 14763500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011971 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011971 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011971 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011971 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10433.327473 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10433.327473 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10433.327473 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011701 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011701 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011701 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011701 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10423.162994 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10423.162994 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10423.162994 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134213.636364 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134213.636364 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134213.636364 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7379094 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7379143 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7108517 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7108606 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 880313 # 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Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003173 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003659 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.814661 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1312 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14621 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 231 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 561 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 989 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4575 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5108 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3891 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080078 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892395 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 362674413 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 362674413 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 250614 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 164455 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 415069 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3362211 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3362211 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7338042 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7338042 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 793 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 793 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 895753 # 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number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2907292000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041059 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996187 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996187 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997567 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997567 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222290 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222290 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087248 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.243922 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243922 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.545288 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.545288 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.238862 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155561 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044490 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058050 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.238862 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212405 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212405 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091496 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.237963 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237963 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.551002 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.551002 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231908 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155189 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036189 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048991 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091496 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231908 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.224069 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 59015.868648 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53443.738662 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32420.177903 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32420.177903 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20104.409004 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20104.409004 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574428.428571 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574428.428571 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49441.389291 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49441.389291 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33509.163433 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37517.049925 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37517.049925 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49915.483741 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49915.483741 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38511.337017 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55403.890650 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 63174.543661 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33509.163433 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40112.725623 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53443.738662 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43076.877448 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.223558 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 43725.358499 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58844.826929 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32316.734905 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32316.734905 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20196.741531 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20196.741531 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 409178.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409178.428571 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47670.371889 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47670.371889 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31865.767877 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33190.039911 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.039911 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 52151.457317 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 52151.457317 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35129.272040 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41747.456923 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 46104.569859 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31865.767877 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36331.942504 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58844.826929 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42382.031452 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154769.189083 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154468.369237 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163932.755698 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163932.755698 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159620.192860 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159209.840154 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165281.205323 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165281.205323 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126713.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159454.446959 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159281.937060 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162511.430016 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162291.615496 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 22159802 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11360195 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 912 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1833001 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1832814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 515851 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9779420 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 10618 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 10618 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4509550 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7338954 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2389159 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 893791 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 389403 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363316 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 479303 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1190307 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1167875 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5369048 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688099 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 521676 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 473618 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16106851 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17229570 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365629 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576836 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34278886 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 687205752 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 665341501 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1396720 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2098264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1356042237 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5987251 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 17478652 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.119213 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.324072 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 20782124 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10655468 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1707466 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1707307 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 159 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 502417 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9121363 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 9093 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 9093 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4367100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6772532 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2206652 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 838220 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 373270 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 349428 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 455882 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1149239 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1127446 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4920793 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4454860 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 528061 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 481641 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14762082 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16505656 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 342155 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 581136 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32191029 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 629828856 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 636046096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1307840 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2129720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1269312512 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5644464 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 16439738 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.118176 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.322847 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 15395152 88.08% 88.08% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2083313 11.92% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14497112 88.18% 88.18% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1942467 11.82% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 159 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 17478652 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 21924818496 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 16439738 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20566237996 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 193282156 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 185505924 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8053682000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7381299500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7892863413 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7535601373 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 191039000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 178675000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 314553499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 314921000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40370 # Transaction distribution -system.iobus.trans_dist::ReadResp 40370 # Transaction distribution -system.iobus.trans_dist::WriteReq 136628 # Transaction distribution -system.iobus.trans_dist::WriteResp 136628 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40334 # Transaction distribution +system.iobus.trans_dist::ReadResp 40334 # Transaction distribution +system.iobus.trans_dist::WriteReq 136621 # Transaction distribution +system.iobus.trans_dist::WriteResp 136621 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2381,15 +2364,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353996 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2400,19 +2383,19 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339024 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37005501 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496681 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36912500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 324001 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -2430,73 +2413,73 @@ system.iobus.reqLayer16.occupancy 13000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26468500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26561500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37415000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37416000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567277400 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567387857 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147948000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147910000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115622 # number of replacements -system.iocache.tags.tagsinuse 11.298154 # Cycle average of tags in use +system.iocache.tags.replacements 115602 # number of replacements +system.iocache.tags.tagsinuse 11.206206 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115638 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115618 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9192209246000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.385038 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.913116 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.461565 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.244570 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9192082489000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.403530 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.802676 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.462721 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.237667 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.700388 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040991 # Number of tag accesses -system.iocache.tags.data_accesses 1040991 # Number of data accesses +system.iocache.tags.tag_accesses 1040820 # Number of tag accesses +system.iocache.tags.data_accesses 1040820 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8935 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses -system.iocache.demand_misses::total 8938 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses +system.iocache.demand_misses::total 8919 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8898 # number of overall misses -system.iocache.overall_misses::total 8938 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1672896003 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1678095503 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8879 # number of overall misses +system.iocache.overall_misses::total 8919 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1680349949 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1685547949 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13552714897 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13552714897 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1672896003 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1678464503 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1672896003 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1678464503 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13547011908 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13547011908 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1680349949 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1685916949 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1680349949 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1685916949 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2510,55 +2493,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 188008.092043 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187811.472076 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189249.909787 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189047.549237 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126983.686540 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126983.686540 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 188008.092043 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 187789.718393 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 188008.092043 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 187789.718393 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33965 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126930.251743 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126930.251743 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 189025.333445 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 189249.909787 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 189025.333445 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33462 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3500 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3547 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.704286 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.433888 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8898 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8938 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8898 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8938 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1227996003 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1231345503 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236399949 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1239747949 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8209903918 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8209903918 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1227996003 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1231564503 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1227996003 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1231564503 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8204144644 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8204144644 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1236399949 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1239966949 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1236399949 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1239966949 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2572,645 +2555,642 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138008.092043 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137811.472076 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139249.909787 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139047.549237 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76923.618151 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76923.618151 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 138008.092043 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 137789.718393 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 138008.092043 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 137789.718393 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76869.655985 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76869.655985 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 139249.909787 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139025.333445 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1521682 # number of replacements -system.l2c.tags.tagsinuse 63275.480852 # Cycle average of tags in use -system.l2c.tags.total_refs 5639856 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1580939 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.567409 # Average number of references to valid blocks. +system.l2c.tags.replacements 1288575 # number of replacements +system.l2c.tags.tagsinuse 63334.482670 # Cycle average of tags in use +system.l2c.tags.total_refs 5304464 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1347256 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.937235 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 17731050500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 23300.510768 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 120.316787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 198.572474 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3006.389178 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5620.523219 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9896.072880 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 161.524171 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 257.856403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3567.908148 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7366.209685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9779.597138 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.355538 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001836 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.045874 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.151002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002465 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003935 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054442 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.112399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.149225 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965507 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10707 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48305 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 740 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9837 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 245 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41466 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163376 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.737076 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74056413 # Number of tag accesses -system.l2c.tags.data_accesses 74056413 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2788899 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2788899 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 164206 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 131282 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 295488 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38310 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 41053 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 79363 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 46553 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57229 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 103782 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5034 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3536 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 418413 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 580330 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 274635 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4587 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 421326 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 539744 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292866 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2546044 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 113687 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 125274 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 238961 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5034 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3536 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 418413 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 626883 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 274635 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 421326 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 596973 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 292866 # number of demand (read+write) hits -system.l2c.demand_hits::total 2649826 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5034 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3536 # number of overall hits -system.l2c.overall_hits::cpu0.inst 418413 # number of overall hits -system.l2c.overall_hits::cpu0.data 626883 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 274635 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4587 # number of overall hits -system.l2c.overall_hits::cpu1.inst 421326 # number of overall hits -system.l2c.overall_hits::cpu1.data 596973 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 292866 # number of overall hits -system.l2c.overall_hits::total 2649826 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 62081 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 62914 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 124995 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13155 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 14316 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 27471 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 85397 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 60501 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 145898 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1497 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1290 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 49096 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 140382 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 293392 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3412 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3601 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 47112 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 140231 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 203866 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 883879 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 471175 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 117804 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 588979 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1497 # 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number of overall misses -system.l2c.overall_misses::cpu0.inst 49096 # number of overall misses -system.l2c.overall_misses::cpu0.data 225779 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 293392 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3412 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3601 # number of overall misses -system.l2c.overall_misses::cpu1.inst 47112 # number of overall misses -system.l2c.overall_misses::cpu1.data 200732 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 203866 # number of overall misses -system.l2c.overall_misses::total 1029777 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 990526500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1021428000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2011954500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 200664500 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1722 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5705 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 40867 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.151978 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003510 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 68640564 # Number of tag accesses +system.l2c.tags.data_accesses 68640564 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2576614 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2576614 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 159474 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128945.611264 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157398.925958 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 143922.799278 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275559 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.315189 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.293598 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.244994 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.272905 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.259336 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.594480 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.506582 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.554187 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.173160 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164796 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.224898 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.777857 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.520791 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.698024 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.239577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.214149 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.247032 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.199563 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.237687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.239577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.412406 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.255728 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.298776 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087163 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.214149 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.434993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.247032 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70695.590175 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70766.608588 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70730.293272 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73743.774026 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73774.575910 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73760.429860 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 126619.025979 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124220.934858 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 125614.163873 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127719.546737 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129921.775101 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 145844.077680 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68994.942002 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69165.770374 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69034.523384 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 127289.062269 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130436.335938 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128401.316953 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125250.014682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 127289.062269 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 158491.805667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130757.481195 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129439.901639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124737.940144 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127974.476238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 160885.420087 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 142793.482590 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159169.005787 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158683.209610 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136788.857298 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131789.337281 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157986.725916 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146905.077510 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154929.620177 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 141646.746814 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132359.879610 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158981.245471 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148246.684922 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156413.726754 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158584.607059 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158830.884760 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108700 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141961.697472 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 139187.653919 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145017.898214 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 140017.927084 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 81896 # Transaction distribution -system.membus.trans_dist::ReadResp 974121 # Transaction distribution -system.membus.trans_dist::WriteReq 38489 # Transaction distribution -system.membus.trans_dist::WriteResp 38489 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1317239 # Transaction distribution -system.membus.trans_dist::CleanEvict 246913 # Transaction distribution -system.membus.trans_dist::UpgradeReq 405326 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 320030 # Transaction distribution -system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 159351 # Transaction distribution -system.membus.trans_dist::ReadExResp 141190 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 892225 # Transaction distribution -system.membus.trans_dist::InvalidateReq 691970 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 81394 # Transaction distribution +system.membus.trans_dist::ReadResp 801457 # Transaction distribution +system.membus.trans_dist::WriteReq 38017 # Transaction distribution +system.membus.trans_dist::WriteResp 38017 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1145637 # Transaction distribution +system.membus.trans_dist::CleanEvict 202586 # Transaction distribution +system.membus.trans_dist::UpgradeReq 388021 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 309846 # Transaction distribution +system.membus.trans_dist::UpgradeResp 24 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 139521 # Transaction distribution +system.membus.trans_dist::ReadExResp 122200 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 720063 # Transaction distribution +system.membus.trans_dist::InvalidateReq 663960 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4917130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5066302 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5304270 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24516 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4262617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4409841 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238367 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238367 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4648208 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143189356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 143398186 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7255936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 150654122 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 585601 # Total snoops (count) -system.membus.snoop_fanout::samples 4153558 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 119974316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 120179275 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7283904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 127463179 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 565217 # Total snoops (count) +system.membus.snoop_fanout::samples 3689099 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4153558 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3689099 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4153558 # Request fanout histogram -system.membus.reqLayer0.occupancy 101297998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3689099 # Request fanout histogram +system.membus.reqLayer0.occupancy 101296000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21722999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20132498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9168141817 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7983633356 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5620018463 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4606610325 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45534588 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45425919 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3227,11 +3207,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -3264,53 +3244,53 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11339751 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6165572 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1768705 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 157796 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 143620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14176 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 81898 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4275837 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38489 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38489 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4106250 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2453030 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 692369 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 399393 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1091762 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 305771 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 305771 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4201160 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 934668 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 827940 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9127029 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7489964 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16616993 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 227401989 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 187094309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 414496298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3137723 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8291271 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.336829 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.476230 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 10607741 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5778542 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1706398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 126357 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 115095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11262 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 81396 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3972795 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38017 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38017 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3722299 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2264546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 665609 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 384259 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1049868 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 134 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 281631 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 281631 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3898638 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 910400 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 803672 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8440853 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7105433 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15546286 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 205041299 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177324920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 382366219 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2848440 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7664337 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.347835 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5512705 66.49% 66.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2764390 33.34% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14176 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5009678 65.36% 65.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2643397 34.49% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11262 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8291271 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8991327701 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7664337 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8363064932 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2644911 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2585436 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4134292430 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3816515270 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3690529810 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3482933794 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |