diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | 5576 |
1 files changed, 2788 insertions, 2788 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 815a8f351..c73396a86 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.403575 # Number of seconds simulated -sim_ticks 47403574916500 # Number of ticks simulated -final_tick 47403574916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.374315 # Number of seconds simulated +sim_ticks 47374315410500 # Number of ticks simulated +final_tick 47374315410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 473223 # Simulator instruction rate (inst/s) -host_op_rate 556671 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25492174892 # Simulator tick rate (ticks/s) -host_mem_usage 749540 # Number of bytes of host memory used -host_seconds 1859.53 # Real time elapsed on the host -sim_insts 879974755 # Number of instructions simulated -sim_ops 1035148021 # Number of ops (including micro ops) simulated +host_inst_rate 573964 # Simulator instruction rate (inst/s) +host_op_rate 675116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30496109280 # Simulator tick rate (ticks/s) +host_mem_usage 762100 # Number of bytes of host memory used +host_seconds 1553.45 # Real time elapsed on the host +sim_insts 891626325 # Number of instructions simulated +sim_ops 1048762579 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 121792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3082292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13718664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15413504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 111872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 105344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2806840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9358928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11301824 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428736 # Number of bytes read from this memory -system.physmem.bytes_read::total 56576516 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3082292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2806840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5889132 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75184384 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 107264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 103104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3762996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12951880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13484096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 112000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 117056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2426936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10199632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12856576 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 431488 # Number of bytes read from this memory +system.physmem.bytes_read::total 56553028 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3762996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2426936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6189932 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74832448 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75204968 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1903 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 88568 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 214367 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 240836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 43945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 146246 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 176591 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6699 # Number of read requests responded to by this memory -system.physmem.num_reads::total 924529 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1174756 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74853032 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1676 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 99204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 202386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 210689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1829 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 38009 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 159382 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 200884 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6742 # Number of read requests responded to by this memory +system.physmem.num_reads::total 924162 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1169257 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1177330 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 65022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 289401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 325155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 197431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 238417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1193507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 65022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59212 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 124234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1586049 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1171831 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 79431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 273395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 284629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 215299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 271383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1193749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 79431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51229 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 130660 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1579600 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1586483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1586049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 65022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 289836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 325155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 197431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 238417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2779990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 924529 # Number of read requests accepted -system.physmem.writeReqs 1177330 # Number of write requests accepted -system.physmem.readBursts 924529 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1177330 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59142848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 27008 # Total number of bytes read from write queue -system.physmem.bytesWritten 75203008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56576516 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75204968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 422 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2259 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1580034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1579600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 79431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 273829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 284629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 215299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 271383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2773783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 924162 # Number of read requests accepted +system.physmem.writeReqs 1171831 # Number of write requests accepted +system.physmem.readBursts 924162 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1171831 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59123712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22656 # Total number of bytes read from write queue +system.physmem.bytesWritten 74852544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56553028 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74853032 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 354 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 51848 # Per bank write bursts -system.physmem.perBankRdBursts::1 60547 # Per bank write bursts -system.physmem.perBankRdBursts::2 52943 # Per bank write bursts -system.physmem.perBankRdBursts::3 59873 # Per bank write bursts -system.physmem.perBankRdBursts::4 53995 # Per bank write bursts -system.physmem.perBankRdBursts::5 59394 # Per bank write bursts -system.physmem.perBankRdBursts::6 55656 # Per bank write bursts -system.physmem.perBankRdBursts::7 56350 # Per bank write bursts -system.physmem.perBankRdBursts::8 47470 # Per bank write bursts -system.physmem.perBankRdBursts::9 98045 # Per bank write bursts -system.physmem.perBankRdBursts::10 51346 # Per bank write bursts -system.physmem.perBankRdBursts::11 58216 # Per bank write bursts -system.physmem.perBankRdBursts::12 52575 # Per bank write bursts -system.physmem.perBankRdBursts::13 60842 # Per bank write bursts -system.physmem.perBankRdBursts::14 50185 # Per bank write bursts -system.physmem.perBankRdBursts::15 54822 # Per bank write bursts -system.physmem.perBankWrBursts::0 69717 # Per bank write bursts -system.physmem.perBankWrBursts::1 76530 # Per bank write bursts -system.physmem.perBankWrBursts::2 71410 # Per bank write bursts -system.physmem.perBankWrBursts::3 77292 # Per bank write bursts -system.physmem.perBankWrBursts::4 71372 # Per bank write bursts -system.physmem.perBankWrBursts::5 75019 # Per bank write bursts -system.physmem.perBankWrBursts::6 75211 # Per bank write bursts -system.physmem.perBankWrBursts::7 75617 # Per bank write bursts -system.physmem.perBankWrBursts::8 67898 # Per bank write bursts -system.physmem.perBankWrBursts::9 76939 # Per bank write bursts -system.physmem.perBankWrBursts::10 70016 # Per bank write bursts -system.physmem.perBankWrBursts::11 75357 # Per bank write bursts -system.physmem.perBankWrBursts::12 71664 # Per bank write bursts -system.physmem.perBankWrBursts::13 78615 # Per bank write bursts -system.physmem.perBankWrBursts::14 70257 # Per bank write bursts -system.physmem.perBankWrBursts::15 72133 # Per bank write bursts +system.physmem.perBankRdBursts::0 54791 # Per bank write bursts +system.physmem.perBankRdBursts::1 60963 # Per bank write bursts +system.physmem.perBankRdBursts::2 51680 # Per bank write bursts +system.physmem.perBankRdBursts::3 61600 # Per bank write bursts +system.physmem.perBankRdBursts::4 56399 # Per bank write bursts +system.physmem.perBankRdBursts::5 67623 # Per bank write bursts +system.physmem.perBankRdBursts::6 62592 # Per bank write bursts +system.physmem.perBankRdBursts::7 58195 # Per bank write bursts +system.physmem.perBankRdBursts::8 51047 # Per bank write bursts +system.physmem.perBankRdBursts::9 95684 # Per bank write bursts +system.physmem.perBankRdBursts::10 47816 # Per bank write bursts +system.physmem.perBankRdBursts::11 53141 # Per bank write bursts +system.physmem.perBankRdBursts::12 48535 # Per bank write bursts +system.physmem.perBankRdBursts::13 54663 # Per bank write bursts +system.physmem.perBankRdBursts::14 49130 # Per bank write bursts +system.physmem.perBankRdBursts::15 49949 # Per bank write bursts +system.physmem.perBankWrBursts::0 71660 # Per bank write bursts +system.physmem.perBankWrBursts::1 78743 # Per bank write bursts +system.physmem.perBankWrBursts::2 71851 # Per bank write bursts +system.physmem.perBankWrBursts::3 78616 # Per bank write bursts +system.physmem.perBankWrBursts::4 73485 # Per bank write bursts +system.physmem.perBankWrBursts::5 81529 # Per bank write bursts +system.physmem.perBankWrBursts::6 75635 # Per bank write bursts +system.physmem.perBankWrBursts::7 74455 # Per bank write bursts +system.physmem.perBankWrBursts::8 70456 # Per bank write bursts +system.physmem.perBankWrBursts::9 72917 # Per bank write bursts +system.physmem.perBankWrBursts::10 67611 # Per bank write bursts +system.physmem.perBankWrBursts::11 70918 # Per bank write bursts +system.physmem.perBankWrBursts::12 67621 # Per bank write bursts +system.physmem.perBankWrBursts::13 71486 # Per bank write bursts +system.physmem.perBankWrBursts::14 70570 # Per bank write bursts +system.physmem.perBankWrBursts::15 72018 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 33 # Number of times write queue was full causing retry -system.physmem.totGap 47403571626000 # Total gap between requests +system.physmem.numWrRetry 85 # Number of times write queue was full causing retry +system.physmem.totGap 47374312061000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 881304 # Read request sizes (log2) +system.physmem.readPktSize::6 880937 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1174756 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 659566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 77579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 24996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 21849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1169257 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 656925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 77551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -189,169 +189,173 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 73262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 73463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 77885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 70974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 65826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 970623 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 138.411655 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 95.318742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 185.703174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 665453 68.56% 68.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189210 19.49% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42199 4.35% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19114 1.97% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13470 1.39% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8660 0.89% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6031 0.62% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4990 0.51% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21496 2.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 970623 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60964 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.158028 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.577791 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60961 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 29578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 64054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 66659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 77359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 72784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 77929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 71715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 64345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 259 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 927168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 144.500035 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.409552 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.008164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 615708 66.41% 66.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189300 20.42% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44500 4.80% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20695 2.23% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14869 1.60% 95.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9173 0.99% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6380 0.69% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5518 0.60% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21025 2.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 927168 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60983 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.148533 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.608088 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60979 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60964 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60964 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.274441 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.533375 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.742081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49066 80.48% 80.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4709 7.72% 88.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2977 4.88% 93.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1753 2.88% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 988 1.62% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 316 0.52% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 174 0.29% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 124 0.20% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 67 0.11% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 44 0.07% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 37 0.06% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 48 0.08% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 425 0.70% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 48 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 48 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.07% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 26 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 10 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60964 # Writes before turning the bus around for reads -system.physmem.totQLat 29056215697 # Total ticks spent queuing -system.physmem.totMemAccLat 46383221947 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4620535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31442.48 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60983 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60983 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.178640 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.436589 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.785486 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49393 80.99% 80.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4571 7.50% 88.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2800 4.59% 93.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1776 2.91% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1006 1.65% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 308 0.51% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 149 0.24% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 125 0.20% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 64 0.10% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 38 0.06% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.05% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 41 0.07% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 435 0.71% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 54 0.09% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 52 0.09% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 33 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60983 # Writes before turning the bus around for reads +system.physmem.totQLat 30413749694 # Total ticks spent queuing +system.physmem.totMemAccLat 47735149694 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4619040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32922.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50192.48 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 51672.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.95 # Average write queue length when enqueuing -system.physmem.readRowHits 688543 # Number of row buffer hits during reads -system.physmem.writeRowHits 439987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.44 # Row buffer hit rate for writes -system.physmem.avgGap 22553164.43 # Average gap between requests -system.physmem.pageHitRate 53.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3707333280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2022850500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3514687800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3837248640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1188225117900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27399839328750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31697317314150 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.669411 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45581711195731 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582909380000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing +system.physmem.readRowHits 683627 # Number of row buffer hits during reads +system.physmem.writeRowHits 482581 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.26 # Row buffer hit rate for writes +system.physmem.avgGap 22602323.61 # Average gap between requests +system.physmem.pageHitRate 55.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3700302480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2019014250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3695975400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3926705040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1192499073090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27378533808750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31678634457810 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.688048 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45546210437205 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581932300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 238953890769 # Time in different power states +system.physmem_0.memoryStateTime::ACT 246167130795 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3630576600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1980969375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3693307800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3777055920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1193695955100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27395040340500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31697988952575 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.683580 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45573641620138 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582909380000 # Time in different power states +system.physmem_1.actEnergy 3308936400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1805471250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3509181000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3651784560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1178425765395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27390878815500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31675839532905 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.629051 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45566794873385 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581932300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 247019106112 # Time in different power states +system.physmem_1.memoryStateTime::ACT 225582219115 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -378,17 +382,17 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -418,75 +422,73 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 114038 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 114038 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12642 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85549 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 114019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.228032 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 76.998938 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 114018 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 114019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 98210 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 93486 95.19% 95.19% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3452 3.51% 98.70% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 155 0.16% 98.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 934 0.95% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 20 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 48 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 37 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 30 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 101108 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 101108 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9051 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76906 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 101094 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 101094 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 101094 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85971 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 76182 88.61% 88.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 8727 10.15% 98.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 200 0.23% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 718 0.84% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 29 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 34 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 12 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 19 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 98210 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 3576910072 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.522403 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -1868589580 -52.24% -52.24% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 5445499652 152.24% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 3576910072 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 85549 87.13% 87.13% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12642 12.87% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 98191 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 114038 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 85971 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -250064880 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.334382 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.471774 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -166447796 66.56% 66.56% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -83617084 33.44% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -250064880 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 76906 89.47% 89.47% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9051 10.53% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85957 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101108 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 114038 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 98191 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101108 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85957 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 98191 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 212229 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85957 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 187065 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86092375 # DTB read hits -system.cpu0.dtb.read_misses 87013 # DTB read misses -system.cpu0.dtb.write_hits 77928513 # DTB write hits -system.cpu0.dtb.write_misses 27025 # DTB write misses +system.cpu0.dtb.read_hits 84046306 # DTB read hits +system.cpu0.dtb.read_misses 73432 # DTB read misses +system.cpu0.dtb.write_hits 77237834 # DTB write hits +system.cpu0.dtb.write_misses 27676 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38112 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 35922 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4351 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4635 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9561 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86179388 # DTB read accesses -system.cpu0.dtb.write_accesses 77955538 # DTB write accesses +system.cpu0.dtb.perms_faults 9711 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 84119738 # DTB read accesses +system.cpu0.dtb.write_accesses 77265510 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 164020888 # DTB hits -system.cpu0.dtb.misses 114038 # DTB misses -system.cpu0.dtb.accesses 164134926 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 161284140 # DTB hits +system.cpu0.dtb.misses 101108 # DTB misses +system.cpu0.dtb.accesses 161385248 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -516,891 +518,888 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 57747 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57747 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51498 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 57747 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57747 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57747 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52059 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25570.833093 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48075 92.35% 92.35% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2753 5.29% 97.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 34 0.07% 97.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 1024 1.97% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 15 0.03% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 43 0.08% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 19 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 37 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 21 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52059 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 58460 # Table walker walks requested +system.cpu0.itb.walker.walksLong 58460 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 540 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52669 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 58460 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 58460 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 58460 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 53209 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26190.982728 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 47169 88.65% 88.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 4943 9.29% 97.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 65 0.12% 98.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 859 1.61% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.07% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 25 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 53209 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51498 98.92% 98.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 561 1.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52059 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 52669 98.99% 98.99% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 540 1.01% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 53209 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57747 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57747 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 58460 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 58460 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52059 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52059 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 109806 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 458544228 # ITB inst hits -system.cpu0.itb.inst_misses 57747 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53209 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53209 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 111669 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 449335815 # ITB inst hits +system.cpu0.itb.inst_misses 58460 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26949 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24946 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 458601975 # ITB inst accesses -system.cpu0.itb.hits 458544228 # DTB hits -system.cpu0.itb.misses 57747 # DTB misses -system.cpu0.itb.accesses 458601975 # DTB accesses -system.cpu0.numPwrStateTransitions 27516 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13758 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3404463734.886103 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 97180881292.374130 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3759 27.32% 27.32% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9972 72.48% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 12 0.09% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 449394275 # ITB inst accesses +system.cpu0.itb.hits 449335815 # DTB hits +system.cpu0.itb.misses 58460 # DTB misses +system.cpu0.itb.accesses 449394275 # DTB accesses +system.cpu0.numPwrStateTransitions 8624 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 4312 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 10857440365.954313 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 156382311444.961365 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3059 70.94% 70.94% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1229 28.50% 99.44% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.05% 99.49% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.54% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.65% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 14 0.32% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7033293879000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13758 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 564962851937 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94807149833 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7470353528320 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 4312 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 557032552505 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94748630821 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13758 # number of quiesce instructions executed -system.cpu0.committedInsts 458270897 # Number of instructions committed -system.cpu0.committedOps 538093671 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 494447989 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 420942 # Number of float alu accesses -system.cpu0.num_func_calls 27507374 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 69395953 # number of instructions that are conditional controls -system.cpu0.num_int_insts 494447989 # number of integer instructions -system.cpu0.num_fp_insts 420942 # number of float instructions -system.cpu0.num_int_register_reads 717601691 # number of times the integer registers were read -system.cpu0.num_int_register_writes 392303230 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 699105 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 312628 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 119518995 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 119177994 # number of times the CC registers were written -system.cpu0.num_mem_refs 164010919 # number of memory refs -system.cpu0.num_load_insts 86087147 # Number of load instructions -system.cpu0.num_store_insts 77923772 # Number of store instructions -system.cpu0.num_idle_cycles 93677224129.124023 # Number of idle cycles -system.cpu0.num_busy_cycles 1129925703.875976 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011918 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988082 # Percentage of idle cycles -system.cpu0.Branches 102213618 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 373117768 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1177948 0.22% 69.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 60910 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 42581 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 86087147 15.99% 85.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 77923772 14.47% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 4312 # number of quiesce instructions executed +system.cpu0.committedInsts 449083110 # Number of instructions committed +system.cpu0.committedOps 528384419 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 485390643 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 507449 # Number of float alu accesses +system.cpu0.num_func_calls 26866500 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68160489 # number of instructions that are conditional controls +system.cpu0.num_int_insts 485390643 # number of integer instructions +system.cpu0.num_fp_insts 507449 # number of float instructions +system.cpu0.num_int_register_reads 703891240 # number of times the integer registers were read +system.cpu0.num_int_register_writes 384865941 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 816779 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 435492 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117650799 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117386896 # number of times the CC registers were written +system.cpu0.num_mem_refs 161276211 # number of memory refs +system.cpu0.num_load_insts 84042257 # Number of load instructions +system.cpu0.num_store_insts 77233954 # Number of store instructions +system.cpu0.num_idle_cycles 93634565715.988022 # Number of idle cycles +system.cpu0.num_busy_cycles 1114065105.011976 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011758 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988242 # Percentage of idle cycles +system.cpu0.Branches 100200450 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 366086093 69.25% 69.25% # Class of executed instruction +system.cpu0.op_class::IntMult 1185979 0.22% 69.47% # Class of executed instruction +system.cpu0.op_class::IntDiv 59083 0.01% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 72839 0.01% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::MemRead 84042257 15.90% 85.39% # Class of executed instruction +system.cpu0.op_class::MemWrite 77233954 14.61% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 538410126 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5755741 # number of replacements -system.cpu0.dcache.tags.tagsinuse 471.832715 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 158017240 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5756252 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.451411 # Average number of references to valid blocks. +system.cpu0.op_class::total 528680248 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5566798 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.671926 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155470196 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5567308 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.925560 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.832715 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921548 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.921548 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 333769183 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 333769183 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80089936 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80089936 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73524451 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73524451 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195750 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 195750 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 158273 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 158273 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1825906 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1825906 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1807959 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1807959 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153772660 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153772660 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153968410 # number of overall hits -system.cpu0.dcache.overall_hits::total 153968410 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3122111 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3122111 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1430717 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1430717 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657703 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 657703 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 783281 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 783281 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173414 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 173414 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190134 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 190134 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5336109 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5336109 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5993812 # number of overall misses -system.cpu0.dcache.overall_misses::total 5993812 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46238724000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 46238724000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29544894000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29544894000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25637315000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25637315000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2487014500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2487014500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4740803500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4740803500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2810500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2810500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 101420933000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 101420933000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83212047 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83212047 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74955168 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74955168 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853453 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 853453 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 941554 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 941554 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1999320 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1999320 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1998093 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1998093 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 159108769 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 159108769 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 159962222 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 159962222 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037520 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037520 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019088 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.019088 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770638 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770638 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.831902 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.831902 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086736 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086736 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095158 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095158 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033537 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033537 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037470 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037470 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14810.083306 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14810.083306 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20650.410948 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20650.410948 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32730.673922 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32730.673922 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14341.486270 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.671926 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981781 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.981781 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 328131694 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 328131694 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 78275725 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78275725 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72837974 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72837974 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200143 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 200143 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 232092 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 232092 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1764306 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1764306 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721538 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1721538 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 151345791 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 151345791 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 151545934 # number of overall hits +system.cpu0.dcache.overall_hits::total 151545934 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2974115 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2974115 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1412109 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1412109 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649854 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 649854 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801670 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 801670 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 161158 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 161158 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202775 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 202775 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5187894 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5187894 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5837748 # number of overall misses +system.cpu0.dcache.overall_misses::total 5837748 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44497648000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 44497648000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28844482000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 28844482000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25694293000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 25694293000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2462602000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2462602000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4821620000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4821620000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2416000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2416000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 99036423000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 99036423000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 99036423000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 99036423000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 81249840 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 81249840 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74250083 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74250083 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 849997 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 849997 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033762 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1033762 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1925464 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1925464 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1924313 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1924313 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 156533685 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156533685 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 157383682 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 157383682 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036605 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036605 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019018 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.019018 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764537 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.764537 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.775488 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.775488 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.105375 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.105375 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033142 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033142 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037092 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037092 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19006.533225 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16920.939963 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19089.908738 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19089.908738 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16964.833528 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16964.833528 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5755741 # number of writebacks -system.cpu0.dcache.writebacks::total 5755741 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25545 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25545 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21233 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21233 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44607 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44607 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 46778 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 46778 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 46778 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 46778 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3096566 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3096566 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1409484 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1409484 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656541 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 656541 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 783281 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 783281 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128807 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128807 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190134 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 190134 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5289331 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5289331 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5945872 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5945872 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54115 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42074729000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42074729000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27794776000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27794776000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13747691500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13747691500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24854034000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24854034000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1645535500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1645535500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4550721500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4550721500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2758500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2758500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94723539000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 94723539000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 108471230500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5071681500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5071681500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5071681500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5071681500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037213 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037213 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.769276 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.769276 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.831902 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.831902 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064425 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064425 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095158 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095158 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033243 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037170 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.037170 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5566798 # number of writebacks +system.cpu0.dcache.writebacks::total 5566798 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 29633 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 29633 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21518 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21518 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45711 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45711 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 51151 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 51151 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 51151 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 51151 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2944482 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2944482 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1390591 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1390591 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648168 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 648168 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801670 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 801670 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202775 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 202775 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5136743 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5136743 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5784911 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5784911 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21025 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22388 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 43413 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40085054500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40085054500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26946583500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26946583500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14957704500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14957704500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24892623000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24892623000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1575244000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1575244000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4618898000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4618898000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2363000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2363000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 91924261000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 91924261000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 106881965500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3989550000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3989550000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3989550000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3989550000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036240 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036240 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018728 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018728 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.775488 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.775488 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059958 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059958 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.105375 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.105375 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032816 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032816 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036757 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036757 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 4916262 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.907947 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 453627454 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4916774 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 92.261197 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907947 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5174135 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.907744 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 444161163 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5174647 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.834099 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30089682000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907744 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 922005230 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 922005230 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 453627454 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 453627454 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 453627454 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 453627454 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 453627454 # number of overall hits -system.cpu0.icache.overall_hits::total 453627454 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4916774 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4916774 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4916774 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4916774 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4916774 # number of overall misses -system.cpu0.icache.overall_misses::total 4916774 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52276659500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 52276659500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 52276659500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 52276659500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 52276659500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 52276659500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 458544228 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 458544228 # 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average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10632.308807 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10632.308807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10632.308807 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 903846282 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 903846282 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 444161163 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 444161163 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 444161163 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 444161163 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 55704586500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 55704586500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 449335815 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 449335815 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 449335815 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 449335815 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 449335815 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 449335815 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011516 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011516 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011516 # 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number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 4916262 # number of writebacks -system.cpu0.icache.writebacks::total 4916262 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4916774 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4916774 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4916774 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4916774 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4916774 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4916774 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 5174135 # number of writebacks +system.cpu0.icache.writebacks::total 5174135 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5174652 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5174652 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5174652 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5174652 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5174652 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5174652 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 53117260500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 53117260500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010723 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010723 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010723 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011516 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011516 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10264.895205 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7829609 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7829625 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7568346 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7568354 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1043159 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2362641 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16162.227513 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 14986861 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2378231 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.301684 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 981182 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2342884 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15723.839714 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9135802 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2358598 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.873404 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15129.176557 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 55.599278 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 80.860024 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 896.591654 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.923412 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003394 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004935 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054724 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986464 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1593 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 15407.459260 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.158261 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.135006 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 251.087187 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.940397 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002329 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001656 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.015325 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.959707 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 345 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13925 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 258 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 732 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 603 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2612 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5888 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5210 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.097229 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15297 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 167 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 53 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1333 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5696 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7896 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021057 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.849915 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 362405390 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 362405390 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 268274 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147126 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 415400 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3821588 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3821588 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346781000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3820807000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7316839500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850748500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346781000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042089 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3820807000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7316839500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.072634 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997739 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997739 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208334 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208334 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092312 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.237547 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237547 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734749 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734749 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157547 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236016 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236016 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092581 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257538 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257538 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728943 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728943 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.166278 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229341 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.235841 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 22110497 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11343995 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 879 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1795730 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1795410 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 572087 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9462372 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26540 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26540 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5352908 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6850414 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2268094 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 917561 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 438813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347856 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 497865 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1218452 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1195725 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4916774 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4752404 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 832834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 781464 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14836060 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18594952 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327877 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 607160 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34366049 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 629486804 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699379029 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1242688 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2226528 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1332335049 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6259200 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 105003768 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 17822799 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.114255 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.318177 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 22270826 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11431607 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 634641 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 634635 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 532548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9516927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 22389 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 22388 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5262772 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7044356 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1133181 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 892107 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 438346 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 371201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 524392 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1190804 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1167926 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5174652 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4606140 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 845268 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 799396 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15609689 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18074319 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 333482 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 538074 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34555564 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662494868 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 674962485 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1270200 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1955080 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1340682633 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5171785 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 107950516 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 16772894 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.051983 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.221994 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15786774 88.58% 88.58% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2035705 11.42% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 320 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15900995 94.80% 94.80% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 871893 5.20% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 17822799 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 21920125505 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 16772894 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 22046960997 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 184217084 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 203834159 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7418286000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7805103000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8250668056 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7957435977 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 172541000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 174707000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 328844000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 293689000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1430,69 +1429,75 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 102344 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 102344 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10188 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77277 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 102334 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.244298 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 78.150189 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 102333 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 113512 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 113512 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10824 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86665 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 27 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 113485 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.290787 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 77.918264 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 113483 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 102334 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 87475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 86378 98.75% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 960 1.10% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 39 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 87475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -5328755248 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.736470 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.440547 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1404285148 26.35% 26.35% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -3924470100 73.65% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -5328755248 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 77278 88.35% 88.35% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10188 11.65% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 87466 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102344 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 113485 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 97516 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 88342 90.59% 90.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 8042 8.25% 98.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 147 0.15% 98.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 810 0.83% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 18 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 45 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 17 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 36 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 97516 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 14762172 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 194.841712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 2876286860 19484.17% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 14762172 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 86666 88.90% 88.90% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10824 11.10% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97490 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 113512 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102344 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87466 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 113512 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97490 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87466 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 189810 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97490 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 211002 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79660508 # DTB read hits -system.cpu1.dtb.read_misses 74735 # DTB read misses -system.cpu1.dtb.write_hits 72705787 # DTB write hits -system.cpu1.dtb.write_misses 27609 # DTB write misses +system.cpu1.dtb.read_hits 83873503 # DTB read hits +system.cpu1.dtb.read_misses 85876 # DTB read misses +system.cpu1.dtb.write_hits 75393075 # DTB write hits +system.cpu1.dtb.write_misses 27636 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36374 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39012 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4588 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3907 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10004 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79735243 # DTB read accesses -system.cpu1.dtb.write_accesses 72733396 # DTB write accesses +system.cpu1.dtb.perms_faults 10199 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83959379 # DTB read accesses +system.cpu1.dtb.write_accesses 75420711 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 152366295 # DTB hits -system.cpu1.dtb.misses 102344 # DTB misses -system.cpu1.dtb.accesses 152468639 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 159266578 # DTB hits +system.cpu1.dtb.misses 113512 # DTB misses +system.cpu1.dtb.accesses 159380090 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1522,897 +1527,889 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 58593 # Table walker walks requested -system.cpu1.itb.walker.walksLong 58593 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 620 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52801 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 58593 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 58593 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 58593 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53421 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25912.740308 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47948 89.75% 89.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 4330 8.11% 97.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 49 0.09% 97.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.73% 99.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.05% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 42 0.08% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53421 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1503171148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1503171148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1503171148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 52801 98.84% 98.84% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 620 1.16% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53421 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 59776 # Table walker walks requested +system.cpu1.itb.walker.walksLong 59776 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 674 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53293 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 59776 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 59776 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 59776 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53967 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25622.306224 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 52820 97.87% 97.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 977 1.81% 99.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 34 0.06% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.11% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 61 0.11% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 53967 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1314622148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1314622148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1314622148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 53293 98.75% 98.75% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 674 1.25% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53967 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58593 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58593 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59776 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59776 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53421 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53421 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 112014 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 421982441 # ITB inst hits -system.cpu1.itb.inst_misses 58593 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53967 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53967 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 113743 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 442849873 # ITB inst hits +system.cpu1.itb.inst_misses 59776 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25297 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27503 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 422041034 # ITB inst accesses -system.cpu1.itb.hits 421982441 # DTB hits -system.cpu1.itb.misses 58593 # DTB misses -system.cpu1.itb.accesses 422041034 # DTB accesses -system.cpu1.numPwrStateTransitions 9904 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4952 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9471329494.171041 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 145765994017.543427 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3395 68.56% 68.56% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1531 30.92% 99.47% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.72% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.28% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 442909649 # ITB inst accesses +system.cpu1.itb.hits 442849873 # DTB hits +system.cpu1.itb.misses 59776 # DTB misses +system.cpu1.itb.accesses 442909649 # DTB accesses +system.cpu1.numPwrStateTransitions 28574 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 14287 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3279405691.982362 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 123453533761.994095 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4140 28.98% 28.98% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10126 70.88% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7470352176392 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4952 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 501551261365 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94807149833 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11813601970000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 14287 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 521446289148 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94748630821 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4952 # number of quiesce instructions executed -system.cpu1.committedInsts 421703858 # Number of instructions committed -system.cpu1.committedOps 497054350 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 456781482 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 475663 # Number of float alu accesses -system.cpu1.num_func_calls 25188507 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 64210733 # number of instructions that are conditional controls -system.cpu1.num_int_insts 456781482 # number of integer instructions -system.cpu1.num_fp_insts 475663 # number of float instructions -system.cpu1.num_int_register_reads 664763727 # number of times the integer registers were read -system.cpu1.num_int_register_writes 362355133 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 757340 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 426036 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 109701618 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 109432507 # number of times the CC registers were written -system.cpu1.num_mem_refs 152358964 # number of memory refs -system.cpu1.num_load_insts 79658830 # Number of load instructions -system.cpu1.num_store_insts 72700134 # Number of store instructions -system.cpu1.num_idle_cycles 93804047310.268021 # Number of idle cycles -system.cpu1.num_busy_cycles 1003102522.731979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010580 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989420 # Percentage of idle cycles -system.cpu1.Branches 94064671 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 343802607 69.13% 69.13% # Class of executed instruction -system.cpu1.op_class::IntMult 1044362 0.21% 69.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 57840 0.01% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 69226 0.01% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::MemRead 79658830 16.02% 85.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 72700134 14.62% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 14287 # number of quiesce instructions executed +system.cpu1.committedInsts 442543215 # Number of instructions committed +system.cpu1.committedOps 520378160 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 478315040 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 404780 # Number of float alu accesses +system.cpu1.num_func_calls 26483096 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 67217461 # number of instructions that are conditional controls +system.cpu1.num_int_insts 478315040 # number of integer instructions +system.cpu1.num_fp_insts 404780 # number of float instructions +system.cpu1.num_int_register_reads 696723237 # number of times the integer registers were read +system.cpu1.num_int_register_writes 379679857 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 664337 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 317564 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 114632172 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 114267384 # number of times the CC registers were written +system.cpu1.num_mem_refs 159256484 # number of memory refs +system.cpu1.num_load_insts 83870110 # Number of load instructions +system.cpu1.num_store_insts 75386374 # Number of store instructions +system.cpu1.num_idle_cycles 93705738242.702026 # Number of idle cycles +system.cpu1.num_busy_cycles 1042892578.297978 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011007 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988993 # Percentage of idle cycles +system.cpu1.Branches 98643380 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 360264761 69.19% 69.19% # Class of executed instruction +system.cpu1.op_class::IntMult 1062033 0.20% 69.39% # Class of executed instruction +system.cpu1.op_class::IntDiv 60918 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 40731 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::MemRead 83870110 16.11% 85.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 75386374 14.48% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 497333042 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5003393 # number of replacements -system.cpu1.dcache.tags.tagsinuse 453.941998 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 147178696 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5003905 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.412768 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378733231000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.941998 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886605 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.886605 # Average percentage of cache occupancy +system.cpu1.op_class::total 520684927 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5203972 # number of replacements +system.cpu1.dcache.tags.tagsinuse 424.411021 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153866536 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5204484 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.564225 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8378899013000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 424.411021 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.828928 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.828928 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 309758535 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 309758535 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 74209320 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74209320 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68941180 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68941180 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175621 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 175621 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 163479 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 163479 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1660182 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1660182 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1630108 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1630108 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 143313979 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 143313979 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 143489600 # number of overall hits -system.cpu1.dcache.overall_hits::total 143489600 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2836392 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2836392 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1297238 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1297238 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 605603 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 605603 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 460373 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 460373 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162387 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 162387 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 191354 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 191354 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4594003 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4594003 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5199606 # number of overall misses -system.cpu1.dcache.overall_misses::total 5199606 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40714366500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 40714366500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24361465000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 24361465000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11037691000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11037691000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2429522000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2429522000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4779056000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4779056000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2991500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2991500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 76113522500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 76113522500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 76113522500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 76113522500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 77045712 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 77045712 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70238418 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70238418 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 781224 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 781224 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 623852 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 623852 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1822569 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1822569 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1821462 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1821462 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 147907982 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 147907982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 148689206 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 148689206 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036814 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036814 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018469 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018469 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775198 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775198 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.737952 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.737952 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089098 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089098 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105055 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105055 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031060 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031060 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034970 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034970 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 323742508 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 323742508 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 78110378 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78110378 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71558729 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71558729 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177304 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 177304 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 95899 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 95899 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1773602 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1773602 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1738086 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1738086 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 149765006 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 149765006 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 149942310 # number of overall hits +system.cpu1.dcache.overall_hits::total 149942310 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2993339 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2993339 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1322577 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1322577 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630415 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 630415 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446111 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 446111 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170906 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 170906 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 205163 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 205163 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4762027 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4762027 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5392442 # number of overall misses +system.cpu1.dcache.overall_misses::total 5392442 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43487315000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 43487315000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24009342500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 24009342500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10785817000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10785817000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2544188500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2544188500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4864957000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4864957000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2180500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2180500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 78282474500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 78282474500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 78282474500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 78282474500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81103717 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81103717 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72881306 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72881306 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807719 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 807719 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 542010 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 542010 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1944508 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1944508 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1943249 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1943249 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154527033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154527033 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 155334752 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 155334752 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036908 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036908 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018147 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018147 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780488 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780488 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.823068 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.823068 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087892 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087892 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105577 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105577 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030817 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.030817 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034715 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034715 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16568.017587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14638.325000 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16438.897658 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14517.073063 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5003393 # number of writebacks -system.cpu1.dcache.writebacks::total 5003393 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17753 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 17753 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 420 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 420 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44380 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44380 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 18173 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 18173 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 18173 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 18173 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2818639 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2818639 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1296818 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1296818 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 605603 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 605603 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460373 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 460373 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118007 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118007 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 191354 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 191354 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4575830 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4575830 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5181433 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5181433 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11021 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22945 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36912397500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36912397500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23044975500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23044975500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12992134000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12992134000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10577318000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10577318000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1572635000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1572635000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4587759000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4587759000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2934500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2934500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70534691000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 70534691000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83526825000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 83526825000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1888408000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1888408000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1888408000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1888408000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036584 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036584 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018463 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018463 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775198 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775198 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.737952 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.737952 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064748 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064748 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105055 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105055 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030937 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030937 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034847 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034847 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5203972 # number of writebacks +system.cpu1.dcache.writebacks::total 5203972 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14156 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 14156 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 216 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44175 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44175 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 14372 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 14372 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 14372 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 14372 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2979183 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2979183 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1322361 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1322361 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630415 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 630415 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446111 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 446111 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126731 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126731 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 205163 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 205163 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4747655 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4747655 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5378070 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5378070 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17577 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33702 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39805955500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39805955500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22681350000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22681350000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12330973000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12330973000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10339706000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10339706000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1686365000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1686365000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4659843000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4659843000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2131500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2131500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72827011500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 72827011500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85157984500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 85157984500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2978895500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2978895500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2978895500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2978895500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036733 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036733 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018144 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018144 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780488 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780488 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.823068 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.823068 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105577 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105577 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030724 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030724 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034622 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034622 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5018955 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.221127 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 416962969 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5019467 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.069172 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378705112000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.221127 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969182 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969182 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4895837 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.209399 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 437953524 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4896349 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 89.444916 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378871626000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.209399 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969159 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969159 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 848984354 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 848984354 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 416962969 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 416962969 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 416962969 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 416962969 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 416962969 # number of overall hits -system.cpu1.icache.overall_hits::total 416962969 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5019472 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5019472 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5019472 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5019472 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5019472 # number of overall misses -system.cpu1.icache.overall_misses::total 5019472 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53186343000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 53186343000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 53186343000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 53186343000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 53186343000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 53186343000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 421982441 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 421982441 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 421982441 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 421982441 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 421982441 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 421982441 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011895 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011895 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011895 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011895 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011895 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011895 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10596.003524 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10596.003524 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10596.003524 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10596.003524 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 890596095 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 890596095 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 437953524 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 437953524 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 437953524 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 437953524 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 437953524 # number of overall hits +system.cpu1.icache.overall_hits::total 437953524 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4896349 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4896349 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4896349 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4896349 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4896349 # number of overall misses +system.cpu1.icache.overall_misses::total 4896349 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51444170000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 51444170000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 51444170000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 51444170000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 51444170000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 51444170000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 442849873 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 442849873 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 442849873 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 442849873 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 442849873 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 442849873 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011056 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011056 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011056 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011056 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011056 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011056 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10506.638722 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10506.638722 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5018955 # number of writebacks -system.cpu1.icache.writebacks::total 5018955 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5019472 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5019472 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5019472 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5019472 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5019472 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5019472 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 4895837 # number of writebacks +system.cpu1.icache.writebacks::total 4895837 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4896349 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4896349 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4896349 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 4896349 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4896349 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4896349 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50676607000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 50676607000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50676607000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 50676607000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50676607000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 50676607000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011895 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011895 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011895 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6881080 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6881096 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48995995500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 48995995500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48995995500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 48995995500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48995995500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 48995995500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10402000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10402000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10402000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10402000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011056 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011056 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011056 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10006.638722 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94563.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94563.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7252070 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7252079 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 8 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 855832 # 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Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 976 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4506 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5198 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3947 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080261 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897583 # 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number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159422 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5019472 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4633714 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10059121 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.042570 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057382 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.048387 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998054 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998054 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 909185 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 868 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6435 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7258 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940491 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 348956442 # 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mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.156724 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226443 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30905.584971 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39436.606887 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21015.139744 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21015.139744 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16470.098826 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16470.098826 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 358071.285714 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 358071.285714 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32795.710752 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32795.710752 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28018.546747 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26819.950937 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26819.950937 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20762161 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10650842 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1727817 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1727605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 482395 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9130479 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4254476 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6851297 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2274133 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 818827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 384823 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346834 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 460171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1120311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1099104 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5019472 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4398430 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 506547 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 458275 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15058119 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16186537 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 334443 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 542756 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32121855 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 642459768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 622853650 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1275376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1972104 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1268560898 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5663025 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 75880456 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 16447181 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.119069 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.323910 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.225464 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 588000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 20954555 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10760929 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 564007 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 564007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 525208 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9244496 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 16125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 16125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4351848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6833141 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1083593 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 850253 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 408331 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 372440 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 477174 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1146242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1123232 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4896349 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4644090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 493781 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 444195 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14688755 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16849115 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339302 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 606054 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32483226 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 626700344 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 649733422 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1286368 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2216312 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1279936446 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4601099 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75959664 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 15521649 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.052382 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.222797 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14489040 88.09% 88.09% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1957929 11.90% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 212 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14708591 94.76% 94.76% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 813058 5.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 16447181 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20541870997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 15521649 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20731667993 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 171936035 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 171895510 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7529318000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7344633500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7396555908 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7734220026 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 175021499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 178506000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 296243499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 329015998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40346 # Transaction distribution -system.iobus.trans_dist::ReadResp 40346 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 136621 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40399 # Transaction distribution +system.iobus.trans_dist::ReadResp 40399 # Transaction distribution +system.iobus.trans_dist::WriteReq 136980 # Transaction distribution +system.iobus.trans_dist::WriteResp 136980 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47798 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2423,15 +2420,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231238 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231738 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231738 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354758 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47818 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2442,21 +2439,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155955 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355304 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496777 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36887001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513345 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37010502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -2464,7 +2461,7 @@ system.iobus.reqLayer10.occupancy 8000 # La system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -2472,75 +2469,75 @@ system.iobus.reqLayer16.occupancy 14000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26455501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26741000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569241095 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570750713 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92947000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147934000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148178000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115616 # number of replacements -system.iocache.tags.tagsinuse 11.233110 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115853 # number of replacements +system.iocache.tags.tagsinuse 11.245503 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115632 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115869 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9095552544000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.412176 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.820935 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463261 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.238808 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.702069 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9136243501000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.839816 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.405687 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239988 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.462855 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.702844 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040928 # Number of tag accesses -system.iocache.tags.data_accesses 1040928 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1043178 # Number of tag accesses +system.iocache.tags.data_accesses 1043178 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8891 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8928 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8885 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8922 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115619 # number of demand (read+write) misses -system.iocache.demand_misses::total 115659 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115869 # number of demand (read+write) misses +system.iocache.demand_misses::total 115909 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115619 # number of overall misses -system.iocache.overall_misses::total 115659 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1628324544 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1633522544 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115869 # number of overall misses +system.iocache.overall_misses::total 115909 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5278000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1633593087 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1638871087 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12891433551 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12891433551 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14519758095 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14525325095 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14519758095 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14525325095 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12911092626 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12911092626 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5647000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14544685713 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14550332713 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5647000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14544685713 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14550332713 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8891 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8928 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8885 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8922 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115619 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115659 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115869 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115909 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115619 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115659 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115869 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2554,53 +2551,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182966.234767 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183688.756669 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120787.736592 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125587.503739 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125587.503739 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31812 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120682.463041 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 141175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125532.380687 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 141175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125532.380687 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31750 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3498 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3454 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.094340 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.192241 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106953 # number of writebacks +system.iocache.writebacks::total 106953 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8891 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8928 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8885 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8922 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115619 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115659 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115869 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115909 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115619 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115659 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183774544 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1187122544 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115869 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115909 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3428000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189343087 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1192771087 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7546042407 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7546042407 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8729816951 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8733383951 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8729816951 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8733383951 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7553188799 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7553188799 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3647000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8742531886 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8746178886 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3647000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8742531886 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8746178886 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2614,659 +2611,662 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1334376 # number of replacements -system.l2c.tags.tagsinuse 63294.471519 # Cycle average of tags in use -system.l2c.tags.total_refs 5390543 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1393372 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.868703 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 22223.163606 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 261.500257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 456.360455 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3501.846073 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10429.068271 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16721.904383 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.820782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 49.581814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3191.520948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3798.713740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2618.991189 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.339099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003990 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.006964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.053434 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.159135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.255156 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000638 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000757 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.048699 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.039963 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965797 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10362 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 274 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48360 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 245 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9869 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 274 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1630 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5501 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41094 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.158112 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004181 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.737915 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 69824789 # Number of tag accesses -system.l2c.tags.data_accesses 69824789 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2605015 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2605015 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 157240 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 131498 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 288738 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36551 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 35663 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72214 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 46670 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57995 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 104665 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4832 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3674 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 408343 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 539971 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 281420 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5997 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5496 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 419901 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 530515 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 275271 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2475420 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 117433 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 122622 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 240055 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4832 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3674 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 408343 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 586641 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 281420 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5997 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5496 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 419901 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 588510 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 275271 # number of demand (read+write) hits -system.l2c.demand_hits::total 2580085 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4832 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3674 # number of overall hits -system.l2c.overall_hits::cpu0.inst 408343 # number of overall hits -system.l2c.overall_hits::cpu0.data 586641 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 281420 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5997 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5496 # number of overall hits -system.l2c.overall_hits::cpu1.inst 419901 # number of overall hits -system.l2c.overall_hits::cpu1.data 588510 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 275271 # number of overall hits -system.l2c.overall_hits::total 2580085 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 61532 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 60685 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 122217 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 12602 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 13049 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25651 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 81623 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50736 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132359 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1903 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1980 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 45534 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 135010 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 240877 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1748 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1646 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 43900 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 98157 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176782 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 747537 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 445868 # 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 7745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7142 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 463801 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 737403 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 452053 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3459981 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.281261 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.315767 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.297398 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.256383 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.267881 # 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Cycle average of tags in use +system.l2c.tags.total_refs 6107230 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1440978 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.238253 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9552186500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 11716.268844 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.184810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 146.917074 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4004.381376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 14231.433494 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7902.194687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 315.518093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 369.695425 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2763.350410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11175.503416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.178776 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002242 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061102 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.217154 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.120578 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004814 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005641 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.170525 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.186773 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.991803 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 12060 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 189 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50714 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 60 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 153 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1009 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1115 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9723 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 184 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9563 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 39124 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.184021 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002884 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.773834 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 69629880 # Number of tag accesses +system.l2c.tags.data_accesses 69629880 # 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number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5935 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 422841 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 567260 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276728 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 9775 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4116 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 406188 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 512398 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 278781 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2494703 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 136557 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 120325 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 256882 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.251369 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.135632 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.251369 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20538.269992 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20386.227310 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20460.713143 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24842.964824 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24346.060606 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.067859 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79084.015183 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76663.895097 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78070.533332 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80725.208799 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3668271 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2217535 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3586859 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2135577 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81829 # Transaction distribution -system.membus.trans_dist::ReadResp 838129 # Transaction distribution -system.membus.trans_dist::WriteReq 38464 # Transaction distribution -system.membus.trans_dist::WriteResp 38464 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1174756 # Transaction distribution -system.membus.trans_dist::CleanEvict 216961 # Transaction distribution -system.membus.trans_dist::UpgradeReq 398327 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 309165 # Transaction distribution -system.membus.trans_dist::UpgradeResp 22 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 145872 # Transaction distribution -system.membus.trans_dist::ReadExResp 127949 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 756300 # Transaction distribution -system.membus.trans_dist::InvalidateReq 666856 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 81835 # Transaction distribution +system.membus.trans_dist::ReadResp 841453 # Transaction distribution +system.membus.trans_dist::WriteReq 38513 # Transaction distribution +system.membus.trans_dist::WriteResp 38513 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1169257 # Transaction distribution +system.membus.trans_dist::CleanEvict 224172 # Transaction distribution +system.membus.trans_dist::UpgradeReq 330190 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306798 # Transaction distribution +system.membus.trans_dist::UpgradeResp 21 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 142313 # Transaction distribution +system.membus.trans_dist::ReadExResp 124217 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 759618 # Transaction distribution +system.membus.trans_dist::InvalidateReq 654423 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4552154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4790128 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4320804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4469902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238504 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238504 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4708406 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155955 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124524268 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124732755 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131989971 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 572885 # Total snoops (count) -system.membus.snoopTraffic 188480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2396814 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013654 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.116050 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124129580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124337871 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7276480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131614351 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 603280 # Total snoops (count) +system.membus.snoopTraffic 185472 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2313692 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013382 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.114902 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2364088 98.63% 98.63% # Request fanout histogram -system.membus.snoop_fanout::1 32726 1.37% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2282731 98.66% 98.66% # Request fanout histogram +system.membus.snoop_fanout::1 30961 1.34% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2396814 # Request fanout histogram -system.membus.reqLayer0.occupancy 101168498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2313692 # Request fanout histogram +system.membus.reqLayer0.occupancy 101576998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21745999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21542999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8211058586 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8037178912 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4830240380 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4828786098 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45484396 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45456460 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3309,78 +3309,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10770571 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5860830 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1720391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 132185 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 120739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11446 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81831 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4048119 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38464 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38464 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3673076 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2310912 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 679438 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 381379 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1060817 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 109 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291982 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291982 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3967045 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 832947 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 803400 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8640930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144066 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15784996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 212830169 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175839034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 388669203 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2716758 # Total snoops (count) -system.toL2Bus.snoopTraffic 119453392 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7607581 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.354994 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.481646 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10929949 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5951808 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1800454 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 181173 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 166358 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14815 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 81837 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4119674 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38513 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38513 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3703405 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2363493 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 695815 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 407836 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1103651 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 294367 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 294367 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4038548 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 834564 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 806756 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8843715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7139942 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15983657 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216752505 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175713942 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 392466447 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2839573 # Total snoops (count) +system.toL2Bus.snoopTraffic 122328784 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7769609 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.368989 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486467 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4918380 64.65% 64.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2677755 35.20% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11446 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4917524 63.29% 63.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2837270 36.52% 99.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14815 0.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7607581 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8483488339 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7769609 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8597464366 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2591888 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2599172 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3918166834 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4012155776 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3514899349 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3555978029 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |