diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | 5191 |
1 files changed, 2587 insertions, 2604 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index d1847bb61..afe64e1a8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.602568 # Number of seconds simulated -sim_ticks 47602567962500 # Number of ticks simulated -final_tick 47602567962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.593744 # Number of seconds simulated +sim_ticks 47593744171500 # Number of ticks simulated +final_tick 47593744171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 603747 # Simulator instruction rate (inst/s) -host_op_rate 710316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32933076215 # Simulator tick rate (ticks/s) -host_mem_usage 740648 # Number of bytes of host memory used -host_seconds 1445.43 # Real time elapsed on the host -sim_insts 872675802 # Number of instructions simulated -sim_ops 1026715135 # Number of ops (including micro ops) simulated +host_inst_rate 618435 # Simulator instruction rate (inst/s) +host_op_rate 727668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34163076444 # Simulator tick rate (ticks/s) +host_mem_usage 740160 # Number of bytes of host memory used +host_seconds 1393.13 # Real time elapsed on the host +sim_insts 861562684 # Number of instructions simulated +sim_ops 1013739401 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 97216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 105280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3176436 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 39189384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13261312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 67968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2473528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13920528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 8902656 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417088 # Number of bytes read from this memory -system.physmem.bytes_read::total 81676100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3176436 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2473528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5649964 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69006208 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 69440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 68224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3088500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37423496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 12959872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 98944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 107776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2567544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 15084176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 9154944 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory +system.physmem.bytes_read::total 81051908 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3088500 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2567544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5656044 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 68863296 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 69026792 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1645 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 90039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 612347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 207208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1011 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 38737 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 217521 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 139104 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6517 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1316710 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1078222 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 68883880 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 88665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 584755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 202498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1684 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 40206 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 235703 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 143046 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1306957 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1075989 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1080796 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 66728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 823262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 278584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 292432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 187020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1715792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 66728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 118690 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1449632 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1078563 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 64893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 786311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 272302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 316936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 192356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1702995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 64893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 118840 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1446898 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1450064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1449632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 66728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 823694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 278584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 292432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 187020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3165856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1316710 # Number of read requests accepted -system.physmem.writeReqs 1080796 # Number of write requests accepted -system.physmem.readBursts 1316710 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1080796 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 84239104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 30336 # Total number of bytes read from write queue -system.physmem.bytesWritten 69025088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 81676100 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 69026792 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 474 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 461546 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74138 # Per bank write bursts -system.physmem.perBankRdBursts::1 82827 # Per bank write bursts -system.physmem.perBankRdBursts::2 74957 # Per bank write bursts -system.physmem.perBankRdBursts::3 82122 # Per bank write bursts -system.physmem.perBankRdBursts::4 83077 # Per bank write bursts -system.physmem.perBankRdBursts::5 87558 # Per bank write bursts -system.physmem.perBankRdBursts::6 81167 # Per bank write bursts -system.physmem.perBankRdBursts::7 84127 # Per bank write bursts -system.physmem.perBankRdBursts::8 76730 # Per bank write bursts -system.physmem.perBankRdBursts::9 122410 # Per bank write bursts -system.physmem.perBankRdBursts::10 70954 # Per bank write bursts -system.physmem.perBankRdBursts::11 80684 # Per bank write bursts -system.physmem.perBankRdBursts::12 75912 # Per bank write bursts -system.physmem.perBankRdBursts::13 81292 # Per bank write bursts -system.physmem.perBankRdBursts::14 78761 # Per bank write bursts -system.physmem.perBankRdBursts::15 79520 # Per bank write bursts -system.physmem.perBankWrBursts::0 61777 # Per bank write bursts -system.physmem.perBankWrBursts::1 69166 # Per bank write bursts -system.physmem.perBankWrBursts::2 64147 # Per bank write bursts -system.physmem.perBankWrBursts::3 68304 # Per bank write bursts -system.physmem.perBankWrBursts::4 69323 # Per bank write bursts -system.physmem.perBankWrBursts::5 73404 # Per bank write bursts -system.physmem.perBankWrBursts::6 67894 # Per bank write bursts -system.physmem.perBankWrBursts::7 70420 # Per bank write bursts -system.physmem.perBankWrBursts::8 65275 # Per bank write bursts -system.physmem.perBankWrBursts::9 69986 # Per bank write bursts -system.physmem.perBankWrBursts::10 62072 # Per bank write bursts -system.physmem.perBankWrBursts::11 68038 # Per bank write bursts -system.physmem.perBankWrBursts::12 64002 # Per bank write bursts -system.physmem.perBankWrBursts::13 68951 # Per bank write bursts -system.physmem.perBankWrBursts::14 67347 # Per bank write bursts -system.physmem.perBankWrBursts::15 68411 # Per bank write bursts +system.physmem.bw_write::total 1447331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1446898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 64893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 786744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 272302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 316936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 192356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3150326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1306957 # Number of read requests accepted +system.physmem.writeReqs 1078563 # Number of write requests accepted +system.physmem.readBursts 1306957 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1078563 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 83609728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue +system.physmem.bytesWritten 68881216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81051908 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 68883880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 450744 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 74137 # Per bank write bursts +system.physmem.perBankRdBursts::1 79440 # Per bank write bursts +system.physmem.perBankRdBursts::2 74164 # Per bank write bursts +system.physmem.perBankRdBursts::3 81483 # Per bank write bursts +system.physmem.perBankRdBursts::4 82988 # Per bank write bursts +system.physmem.perBankRdBursts::5 89928 # Per bank write bursts +system.physmem.perBankRdBursts::6 78492 # Per bank write bursts +system.physmem.perBankRdBursts::7 81076 # Per bank write bursts +system.physmem.perBankRdBursts::8 74414 # Per bank write bursts +system.physmem.perBankRdBursts::9 117966 # Per bank write bursts +system.physmem.perBankRdBursts::10 72212 # Per bank write bursts +system.physmem.perBankRdBursts::11 83486 # Per bank write bursts +system.physmem.perBankRdBursts::12 77461 # Per bank write bursts +system.physmem.perBankRdBursts::13 81836 # Per bank write bursts +system.physmem.perBankRdBursts::14 80080 # Per bank write bursts +system.physmem.perBankRdBursts::15 77239 # Per bank write bursts +system.physmem.perBankWrBursts::0 62409 # Per bank write bursts +system.physmem.perBankWrBursts::1 67459 # Per bank write bursts +system.physmem.perBankWrBursts::2 64157 # Per bank write bursts +system.physmem.perBankWrBursts::3 68996 # Per bank write bursts +system.physmem.perBankWrBursts::4 69521 # Per bank write bursts +system.physmem.perBankWrBursts::5 74527 # Per bank write bursts +system.physmem.perBankWrBursts::6 66146 # Per bank write bursts +system.physmem.perBankWrBursts::7 68657 # Per bank write bursts +system.physmem.perBankWrBursts::8 63193 # Per bank write bursts +system.physmem.perBankWrBursts::9 66730 # Per bank write bursts +system.physmem.perBankWrBursts::10 63431 # Per bank write bursts +system.physmem.perBankWrBursts::11 70210 # Per bank write bursts +system.physmem.perBankWrBursts::12 65844 # Per bank write bursts +system.physmem.perBankWrBursts::13 70148 # Per bank write bursts +system.physmem.perBankWrBursts::14 68557 # Per bank write bursts +system.physmem.perBankWrBursts::15 66284 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 25 # Number of times write queue was full causing retry -system.physmem.totGap 47602564597000 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 47593740806000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1273485 # Read request sizes (log2) +system.physmem.readPktSize::6 1263732 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1078222 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1098528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 69154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 26336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 19787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 17170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 11894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1075989 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1091015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 68737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 19490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 16927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 14904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 11891 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -188,163 +188,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 46518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 64016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 65226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 70106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 73801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 68996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 68981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 71721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 63773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 845861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 181.192513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.718720 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 240.356894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 524023 61.95% 61.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 157589 18.63% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52244 6.18% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27763 3.28% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18582 2.20% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11693 1.38% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8942 1.06% 94.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9176 1.08% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 35849 4.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 845861 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60416 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.786182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 329.918437 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 60413 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 18318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 20896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 46603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 53376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 64132 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 840117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.511175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.812729 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 240.875315 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 520248 61.93% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 156423 18.62% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51977 6.19% 86.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27385 3.26% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18542 2.21% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11713 1.39% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8913 1.06% 94.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8910 1.06% 95.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 36006 4.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 840117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60330 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.654169 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 330.190002 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 60327 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60416 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60416 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.851513 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.268088 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.277078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56734 93.91% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1553 2.57% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 255 0.42% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 285 0.47% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 70 0.12% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 285 0.47% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 159 0.26% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 94 0.16% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 78 0.13% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 106 0.18% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 41 0.07% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 61 0.10% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 428 0.71% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 38 0.06% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 49 0.08% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 117 0.19% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 11 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60330 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60330 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.839698 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.269040 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.176072 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56620 93.85% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1546 2.56% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 276 0.46% 96.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 296 0.49% 97.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 110 0.18% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 266 0.44% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 180 0.30% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 98 0.16% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 97 0.16% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 84 0.14% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 48 0.08% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 66 0.11% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 398 0.66% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 43 0.07% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 35 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 96 0.16% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.00% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60416 # Writes before turning the bus around for reads -system.physmem.totQLat 28673044871 # Total ticks spent queuing -system.physmem.totMemAccLat 53352469871 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6581180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21784.12 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 7 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60330 # Writes before turning the bus around for reads +system.physmem.totQLat 28430560155 # Total ticks spent queuing +system.physmem.totMemAccLat 52925597655 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6532010000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21762.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40534.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 40512.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.70 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing -system.physmem.readRowHits 1054044 # Number of row buffer hits during reads -system.physmem.writeRowHits 494841 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 45.88 # Row buffer hit rate for writes -system.physmem.avgGap 19855034.61 # Average gap between requests -system.physmem.pageHitRate 64.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3265088400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1781546250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5069789400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3527867520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1219382745750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27491903982750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31834099035270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.747581 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45734675361714 # Time in different power states -system.physmem_0.memoryStateTime::REF 1589554200000 # Time in different power states +system.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing +system.physmem.readRowHits 1047491 # Number of row buffer hits during reads +system.physmem.writeRowHits 495062 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 46.00 # Row buffer hit rate for writes +system.physmem.avgGap 19951096.95 # Average gap between requests +system.physmem.pageHitRate 64.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3221134560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1757563500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5005283400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3511330560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1216360497735 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27489261984750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31827709611225 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.737288 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45730304477620 # Time in different power states +system.physmem_0.memoryStateTime::REF 1589259620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 278338023286 # Time in different power states +system.physmem_0.memoryStateTime::ACT 274179379380 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3129537600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1707585000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5196804600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3460818960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1215349697925 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27495441752250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31833454211535 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.734035 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45740562014248 # Time in different power states -system.physmem_1.memoryStateTime::REF 1589554200000 # Time in different power states +system.physmem_1.actEnergy 3130149960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1707919125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5184613200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3462892560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1215861151230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27489700008000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31827638550795 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.735795 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45731003279682 # Time in different power states +system.physmem_1.memoryStateTime::REF 1589259620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 272450963752 # Time in different power states +system.physmem_1.memoryStateTime::ACT 273478576568 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -375,9 +375,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -408,69 +408,68 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 111926 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 111926 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10169 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86471 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 18 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 111908 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.232334 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 77.721788 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 111907 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 93408 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 93408 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7983 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 70276 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 93401 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.278370 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 85.074143 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 93400 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 111908 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 96658 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23040.705374 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21274.900589 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 18509.319790 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 95612 98.92% 98.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 152 0.16% 99.08% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 763 0.79% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 18 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 23 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 96658 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 444719432 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean -3.785405 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2128162704 478.54% 478.54% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -1683443272 -378.54% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 444719432 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 86471 89.48% 89.48% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10169 10.52% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 96640 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111926 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 93401 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 78266 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22499.341988 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20923.382111 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16650.912887 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 77590 99.14% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 164 0.21% 99.35% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 417 0.53% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 25 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 78266 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 5219685476 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.596746 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.490551 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2104860204 40.33% 40.33% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 3114825272 59.67% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 5219685476 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 70276 89.80% 89.80% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 7983 10.20% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 78259 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 93408 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111926 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96640 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 93408 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78259 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96640 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 208566 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78259 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 171667 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 87929647 # DTB read hits -system.cpu0.dtb.read_misses 85158 # DTB read misses -system.cpu0.dtb.write_hits 79744109 # DTB write hits -system.cpu0.dtb.write_misses 26768 # DTB write misses +system.cpu0.dtb.read_hits 80327529 # DTB read hits +system.cpu0.dtb.read_misses 69973 # DTB read misses +system.cpu0.dtb.write_hits 72902451 # DTB write hits +system.cpu0.dtb.write_misses 23435 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37859 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34709 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3884 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4393 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10087 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 88014805 # DTB read accesses -system.cpu0.dtb.write_accesses 79770877 # DTB write accesses +system.cpu0.dtb.perms_faults 8867 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 80397502 # DTB read accesses +system.cpu0.dtb.write_accesses 72925886 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 167673756 # DTB hits -system.cpu0.dtb.misses 111926 # DTB misses -system.cpu0.dtb.accesses 167785682 # DTB accesses +system.cpu0.dtb.hits 153229980 # DTB hits +system.cpu0.dtb.misses 93408 # DTB misses +system.cpu0.dtb.accesses 153323388 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -500,94 +499,93 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 61252 # Table walker walks requested -system.cpu0.itb.walker.walksLong 61252 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 842 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54849 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 61252 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 61252 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 61252 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 55691 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26308.021045 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23499.981275 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 25689.449100 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 54619 98.08% 98.08% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.08% 98.15% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 884 1.59% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 24 0.04% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.09% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 35 0.06% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 55691 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 52417 # Table walker walks requested +system.cpu0.itb.walker.walksLong 52417 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 598 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 46386 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 52417 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 52417 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 52417 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 46984 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25232.568534 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 22985.913240 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 21269.412068 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 46328 98.60% 98.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.09% 98.69% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 530 1.13% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 16 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 24 0.05% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 22 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 46984 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54849 98.49% 98.49% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 842 1.51% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 55691 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 46386 98.73% 98.73% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 598 1.27% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 46984 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61252 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61252 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52417 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52417 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55691 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55691 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 116943 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 467202921 # ITB inst hits -system.cpu0.itb.inst_misses 61252 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 46984 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 46984 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 99401 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 426699171 # ITB inst hits +system.cpu0.itb.inst_misses 52417 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 27100 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24801 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 467264173 # ITB inst accesses -system.cpu0.itb.hits 467202921 # DTB hits -system.cpu0.itb.misses 61252 # DTB misses -system.cpu0.itb.accesses 467264173 # DTB accesses -system.cpu0.numCycles 95205135902 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 426751588 # ITB inst accesses +system.cpu0.itb.hits 426699171 # DTB hits +system.cpu0.itb.misses 52417 # DTB misses +system.cpu0.itb.accesses 426751588 # DTB accesses +system.cpu0.numCycles 95186924479 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5123 # number of quiesce instructions executed -system.cpu0.committedInsts 466948479 # Number of instructions committed -system.cpu0.committedOps 548389991 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 504092161 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 464416 # Number of float alu accesses -system.cpu0.num_func_calls 27983491 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 70438282 # number of instructions that are conditional controls -system.cpu0.num_int_insts 504092161 # number of integer instructions -system.cpu0.num_fp_insts 464416 # number of float instructions -system.cpu0.num_int_register_reads 728885661 # number of times the integer registers were read -system.cpu0.num_int_register_writes 399652952 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 772857 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 344936 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 120908457 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 120465396 # number of times the CC registers were written -system.cpu0.num_mem_refs 167663327 # number of memory refs -system.cpu0.num_load_insts 87924608 # Number of load instructions -system.cpu0.num_store_insts 79738719 # Number of store instructions -system.cpu0.num_idle_cycles 93943889977.646729 # Number of idle cycles -system.cpu0.num_busy_cycles 1261245924.353277 # Number of busy cycles -system.cpu0.not_idle_fraction 0.013248 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.986752 # Percentage of idle cycles -system.cpu0.Branches 104008564 # Number of branches fetched +system.cpu0.kern.inst.quiesce 4674 # number of quiesce instructions executed +system.cpu0.committedInsts 426454163 # Number of instructions committed +system.cpu0.committedOps 501120280 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 460758133 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 395268 # Number of float alu accesses +system.cpu0.num_func_calls 25675920 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 64224693 # number of instructions that are conditional controls +system.cpu0.num_int_insts 460758133 # number of integer instructions +system.cpu0.num_fp_insts 395268 # number of float instructions +system.cpu0.num_int_register_reads 666544840 # number of times the integer registers were read +system.cpu0.num_int_register_writes 365452769 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 661868 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 282064 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 110079606 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 109774743 # number of times the CC registers were written +system.cpu0.num_mem_refs 153223313 # number of memory refs +system.cpu0.num_load_insts 80324545 # Number of load instructions +system.cpu0.num_store_insts 72898768 # Number of store instructions +system.cpu0.num_idle_cycles 94023627088.560516 # Number of idle cycles +system.cpu0.num_busy_cycles 1163297390.439485 # Number of busy cycles +system.cpu0.not_idle_fraction 0.012221 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.987779 # Percentage of idle cycles +system.cpu0.Branches 94888903 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 379698158 69.20% 69.20% # Class of executed instruction -system.cpu0.op_class::IntMult 1212773 0.22% 69.42% # Class of executed instruction -system.cpu0.op_class::IntDiv 66852 0.01% 69.43% # Class of executed instruction +system.cpu0.op_class::IntAlu 346960051 69.20% 69.20% # Class of executed instruction +system.cpu0.op_class::IntMult 1125201 0.22% 69.42% # Class of executed instruction +system.cpu0.op_class::IntDiv 62694 0.01% 69.43% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction @@ -610,127 +608,126 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 46447 0.01% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 37154 0.01% 69.44% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::MemRead 87924608 16.02% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 79738719 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 80324545 16.02% 85.46% # Class of executed instruction +system.cpu0.op_class::MemWrite 72898768 14.54% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 548687557 # Class of executed instruction -system.cpu0.dcache.tags.replacements 5767473 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.102777 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 161665939 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5767985 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.028148 # Average number of references to valid blocks. +system.cpu0.op_class::total 501408413 # Class of executed instruction +system.cpu0.dcache.tags.replacements 5237512 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.877232 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 147745204 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5237891 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.207002 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.102777 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988482 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988482 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 341141490 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 341141490 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 81909684 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 81909684 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75364450 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75364450 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195602 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 195602 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 139312 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 139312 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1827663 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1827663 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798607 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1798607 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 157274134 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 157274134 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 157469736 # number of overall hits -system.cpu0.dcache.overall_hits::total 157469736 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3156555 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3156555 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1440320 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1440320 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 651795 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 651795 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 776738 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 776738 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172749 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 172749 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200464 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200464 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4596875 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4596875 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5248670 # number of overall misses -system.cpu0.dcache.overall_misses::total 5248670 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52100226500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52100226500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36687284500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36687284500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65915448000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 65915448000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2830376000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2830376000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5792176500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5792176500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4797000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4797000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 88787511000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 88787511000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 88787511000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 88787511000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 85066239 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 85066239 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76804770 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76804770 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 847397 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 847397 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 916050 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 916050 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2000412 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2000412 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1999071 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1999071 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 161871009 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 161871009 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 162718406 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 162718406 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037107 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037107 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018753 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018753 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769173 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769173 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.847921 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.847921 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086357 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086357 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100279 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100279 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028398 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028398 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032256 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032256 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16505.407477 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16505.407477 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25471.620543 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25471.620543 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 84861.881355 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 84861.881355 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16384.326393 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16384.326393 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28893.848771 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28893.848771 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.877232 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988041 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988041 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 379 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 370 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.740234 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 311719457 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 311719457 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 74802484 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 74802484 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 68840975 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 68840975 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186514 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 186514 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 133741 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 133741 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1712983 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1712983 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1673957 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1673957 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 143643459 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 143643459 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 143829973 # number of overall hits +system.cpu0.dcache.overall_hits::total 143829973 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2859232 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2859232 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1316810 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1316810 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 596453 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 596453 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 721743 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 721743 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153137 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 153137 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190741 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 190741 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4176042 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4176042 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4772495 # number of overall misses +system.cpu0.dcache.overall_misses::total 4772495 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45650819500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 45650819500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34330450500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34330450500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65187396500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 65187396500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2390631500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2390631500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5489081000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5489081000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7149000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7149000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 79981270000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 79981270000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 79981270000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 79981270000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 77661716 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 77661716 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 70157785 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 70157785 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 782967 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 782967 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 855484 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 855484 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1866120 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1866120 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1864698 # 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average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15966.112404 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26070.921773 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 26070.921773 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90319.402474 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90319.402474 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15611.063949 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15611.063949 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28777.667098 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28777.667098 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # 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number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,158 +736,156 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5767473 # number of writebacks -system.cpu0.dcache.writebacks::total 5767473 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27282 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 27282 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21266 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21266 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44626 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036786 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018476 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018476 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767658 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767658 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.847921 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.847921 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064048 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064048 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100279 # 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average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24474.443937 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 83861.882643 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 83861.882643 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14012.339705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14012.339705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27894.118146 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27894.118146 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5237512 # number of writebacks +system.cpu0.dcache.writebacks::total 5237512 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25341 # 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number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32444395000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32444395000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14818032000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14818032000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 64465653500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64465653500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564895500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564895500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5298419000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5298419000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7070000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7070000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73495276000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 73495276000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 88313308000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 88313308000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897717500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897717500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3102799000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3102799000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6000516500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6000516500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036490 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036490 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018466 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760146 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760146 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.843666 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.843666 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060714 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060714 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102291 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102291 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027935 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027935 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031793 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031793 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14485.695110 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14485.695110 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25043.627438 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25043.627438 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24897.183825 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24897.183825 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89319.402474 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89319.402474 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13812.085720 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.085720 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27778.081273 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27778.081273 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17981.509795 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17981.509795 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18793.946166 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18793.946166 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172286.029835 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172286.029835 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169661.326537 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169661.326537 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170938.516418 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170938.516418 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17798.026157 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17798.026157 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18692.328516 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18692.328516 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173039.382539 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173039.382539 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172684.717275 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172684.717275 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172855.807455 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172855.807455 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5175196 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.827248 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 462027213 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5175708 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 89.268408 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 4772370 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.827216 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 421926289 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4772882 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.400738 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827248 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827216 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 395 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 117 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 939581550 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 939581550 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 462027213 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 462027213 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 462027213 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 462027213 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 462027213 # number of overall hits -system.cpu0.icache.overall_hits::total 462027213 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5175708 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5175708 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5175708 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5175708 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5175708 # number of overall misses -system.cpu0.icache.overall_misses::total 5175708 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 57336545500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 57336545500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 57336545500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 57336545500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 57336545500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 57336545500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 467202921 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 467202921 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 467202921 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 467202921 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 467202921 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 467202921 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011078 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011078 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011078 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011078 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011078 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011078 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11078.010100 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11078.010100 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11078.010100 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11078.010100 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11078.010100 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11078.010100 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 858171224 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 858171224 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 421926289 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 421926289 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 421926289 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 421926289 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 421926289 # number of overall hits +system.cpu0.icache.overall_hits::total 421926289 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4772882 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4772882 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4772882 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4772882 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4772882 # number of overall misses +system.cpu0.icache.overall_misses::total 4772882 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52975952000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 52975952000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 52975952000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 52975952000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 52975952000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 52975952000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 426699171 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 426699171 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 426699171 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 426699171 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 426699171 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 426699171 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011186 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011186 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011186 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011186 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011186 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011186 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11099.363445 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11099.363445 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11099.363445 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11099.363445 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -899,252 +894,248 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 5175196 # number of writebacks -system.cpu0.icache.writebacks::total 5175196 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5175708 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5175708 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5175708 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5175708 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5175708 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5175708 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 4772370 # number of writebacks +system.cpu0.icache.writebacks::total 4772370 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4772882 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4772882 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4772882 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4772882 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4772882 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4772882 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 54748691500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 54748691500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 54748691500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 54748691500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 54748691500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 54748691500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 50589511000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 50589511000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 50589511000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 50589511000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 50589511000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 50589511000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011078 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011078 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011078 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10578.010100 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011186 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011186 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011186 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.363445 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7857654 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7857701 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230591 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7230639 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1019611 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2391891 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16167.019190 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15476667 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2407580 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.428309 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 940745 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2188465 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16163.582102 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 14109503 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2203636 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.402828 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 8764179000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.445219 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.058428 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.612606 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 747.902937 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.932522 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003727 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004859 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.045648 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.986757 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1309 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14303 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 161 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 356 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 28 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 827 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4392 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6793 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2165 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079895 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.872986 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 371635811 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 371635811 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 264720 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157843 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 422563 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3807067 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3807067 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7134877 # 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number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157843 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4693228 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3888633 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 9004424 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 264720 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157843 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4693228 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3888633 # number of overall hits -system.cpu0.l2cache.overall_hits::total 9004424 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10067 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8203 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 18270 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 246628 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 246628 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200453 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 200453 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 262909 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 262909 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 482480 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 482480 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 947383 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 947383 # 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number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 425309500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 392962000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 818271500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3546049000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 3546049000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2066053000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2066053000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4661500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4661500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16748515499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 16748515499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18800277000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 18800277000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39672427000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 39672427000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62566205500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 62566205500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 425309500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 392962000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 18800277000 # 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number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3807067 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3807067 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7134877 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7134877 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 247085 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 247085 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200453 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 200453 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # 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miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998150 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998150 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 15163.258465 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.967950 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 74.840251 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 875.515436 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.925492 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003050 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004568 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053437 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986547 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1542 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13561 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 58 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 726 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 758 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 36 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 590 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6261 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 6710 # 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mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771799 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771799 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240179 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.160107 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240179 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226475 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38787.712096 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53581.196364 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32088.420617 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32088.420617 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.078971 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20390.078971 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 394318.181818 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 394318.181818 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56701.943312 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56701.943312 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32965.919831 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35849.796694 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35849.796694 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 104536.713237 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 104536.713237 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38214.264224 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42784.139329 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229099 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33699.841347 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55879.462450 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32045.813087 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32045.813087 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20277.253421 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20277.253421 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 208951.612903 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 208951.612903 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57464.330352 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57464.330352 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33875.330141 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33812.007674 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33812.007674 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 106116.156414 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 106116.156414 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37449.415339 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42999.554401 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164263.237083 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139527.424077 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162137.083561 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162137.083561 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165005.344560 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 140200.614655 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165162.149377 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165162.149377 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 163171.677363 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144480.491339 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165086.506885 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145962.621565 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 22685684 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11636633 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 725 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1868386 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1868205 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 181 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 566458 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9760546 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 16479 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16479 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5331858 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7134877 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2347214 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 886122 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 438453 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361903 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 524601 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1264261 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1203854 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5175708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4797612 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 779730 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 774618 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15612584 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18673898 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 348811 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 599734 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 35235027 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662612564 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 703409885 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328368 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2198296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1369549113 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6346450 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 18158816 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.116500 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.320855 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 20776945 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 10662406 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 659 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1726264 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1726085 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 488069 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8911186 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 17968 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 17968 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4874700 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6546722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2139143 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 829102 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 434919 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 350602 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 501065 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1159158 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1092705 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4772882 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4419934 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 726049 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 719547 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14404114 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17037537 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296236 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 495044 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 32232931 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 611051348 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 638823901 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1117728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1786944 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1252779921 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5965413 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 16750116 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.116655 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.321042 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 16043491 88.35% 88.35% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2115144 11.65% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 181 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 14796306 88.34% 88.34% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1953631 11.66% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 18158816 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 22462112497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 16750116 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 20546913496 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 223807892 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 219185391 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7806687000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7202448000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8283648998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7531952589 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 182765499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 156520499 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 324947000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 271676000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1396,69 +1387,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 92112 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 92112 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7185 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 70441 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 92107 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.086856 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 26.359895 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 92106 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 101882 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 101882 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8030 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79527 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 101873 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.078529 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 25.064580 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 101872 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 92107 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 77631 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22794.154397 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21108.718713 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 17037.529740 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 76846 98.99% 98.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 174 0.22% 99.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 527 0.68% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 77631 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -5456316576 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.616394 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.486264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2093077220 38.36% 38.36% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -3363239356 61.64% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -5456316576 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 70442 90.74% 90.74% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 7185 9.26% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 77627 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92112 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 101873 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 87566 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23519.505287 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21365.105207 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 20825.826742 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 86337 98.60% 98.60% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 178 0.20% 98.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 904 1.03% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 19 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 87566 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 239339024 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 9.661342 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2072997220 -866.13% -866.13% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 2312336244 966.13% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 239339024 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 79528 90.83% 90.83% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8030 9.17% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 87558 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101882 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92112 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77627 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101882 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87558 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77627 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 169739 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87558 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 189440 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 76812549 # DTB read hits -system.cpu1.dtb.read_misses 67403 # DTB read misses -system.cpu1.dtb.write_hits 69811450 # DTB write hits -system.cpu1.dtb.write_misses 24709 # DTB write misses +system.cpu1.dtb.read_hits 82176038 # DTB read hits +system.cpu1.dtb.read_misses 74927 # DTB read misses +system.cpu1.dtb.write_hits 74775352 # DTB write hits +system.cpu1.dtb.write_misses 26955 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34729 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37701 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4304 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4186 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9295 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 76879952 # DTB read accesses -system.cpu1.dtb.write_accesses 69836159 # DTB write accesses +system.cpu1.dtb.perms_faults 10277 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 82250965 # DTB read accesses +system.cpu1.dtb.write_accesses 74802307 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 146623999 # DTB hits -system.cpu1.dtb.misses 92112 # DTB misses -system.cpu1.dtb.accesses 146716111 # DTB accesses +system.cpu1.dtb.hits 156951390 # DTB hits +system.cpu1.dtb.misses 101882 # DTB misses +system.cpu1.dtb.accesses 157053272 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1488,236 +1479,236 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 54749 # Table walker walks requested -system.cpu1.itb.walker.walksLong 54749 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 360 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 54749 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 54749 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 54749 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 49571 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25509.592302 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23251.815503 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 21686.807401 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 48865 98.58% 98.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 34 0.07% 98.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 581 1.17% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 14 0.03% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 29 0.06% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 25 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 49571 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 63786 # Table walker walks requested +system.cpu1.itb.walker.walksLong 63786 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 574 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58046 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 63786 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 63786 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 63786 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 58620 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26694.208461 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23680.273613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 26398.773524 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 57379 97.88% 97.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 45 0.08% 97.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1025 1.75% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 33 0.06% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 49 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 9 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 58620 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 49211 99.27% 99.27% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 360 0.73% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 49571 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 58046 99.02% 99.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 574 0.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 58620 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54749 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54749 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63786 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63786 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49571 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49571 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 104320 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 406021553 # ITB inst hits -system.cpu1.itb.inst_misses 54749 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58620 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58620 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 122406 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 435405767 # ITB inst hits +system.cpu1.itb.inst_misses 63786 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24319 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26334 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 406076302 # ITB inst accesses -system.cpu1.itb.hits 406021553 # DTB hits -system.cpu1.itb.misses 54749 # DTB misses -system.cpu1.itb.accesses 406076302 # DTB accesses -system.cpu1.numCycles 95205135925 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 435469553 # ITB inst accesses +system.cpu1.itb.hits 435405767 # DTB hits +system.cpu1.itb.misses 63786 # DTB misses +system.cpu1.itb.accesses 435469553 # DTB accesses +system.cpu1.numCycles 95187488343 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14029 # number of quiesce instructions executed -system.cpu1.committedInsts 405727323 # Number of instructions committed -system.cpu1.committedOps 478325144 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 439907771 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 446670 # Number of float alu accesses -system.cpu1.num_func_calls 24605699 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 61596178 # number of instructions that are conditional controls -system.cpu1.num_int_insts 439907771 # number of integer instructions -system.cpu1.num_fp_insts 446670 # number of float instructions -system.cpu1.num_int_register_reads 637924838 # number of times the integer registers were read -system.cpu1.num_int_register_writes 348926241 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 708486 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 403472 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 104772444 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 104573998 # number of times the CC registers were written -system.cpu1.num_mem_refs 146614371 # number of memory refs -system.cpu1.num_load_insts 76808885 # Number of load instructions -system.cpu1.num_store_insts 69805486 # Number of store instructions -system.cpu1.num_idle_cycles 94195407146.248016 # Number of idle cycles -system.cpu1.num_busy_cycles 1009728778.751979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010606 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989394 # Percentage of idle cycles -system.cpu1.Branches 90553045 # Number of branches fetched +system.cpu1.kern.inst.quiesce 14345 # number of quiesce instructions executed +system.cpu1.committedInsts 435108521 # Number of instructions committed +system.cpu1.committedOps 512619121 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 471360298 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 517037 # Number of float alu accesses +system.cpu1.num_func_calls 26310177 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66181606 # number of instructions that are conditional controls +system.cpu1.num_int_insts 471360298 # number of integer instructions +system.cpu1.num_fp_insts 517037 # number of float instructions +system.cpu1.num_int_register_reads 683625420 # number of times the integer registers were read +system.cpu1.num_int_register_writes 373659475 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 819092 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 470852 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 112718016 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 112414585 # number of times the CC registers were written +system.cpu1.num_mem_refs 156939308 # number of memory refs +system.cpu1.num_load_insts 82171340 # Number of load instructions +system.cpu1.num_store_insts 74767968 # Number of store instructions +system.cpu1.num_idle_cycles 94109373851.176025 # Number of idle cycles +system.cpu1.num_busy_cycles 1078114491.823977 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011326 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988674 # Percentage of idle cycles +system.cpu1.Branches 97258514 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 330876771 69.13% 69.13% # Class of executed instruction -system.cpu1.op_class::IntMult 1002715 0.21% 69.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 57816 0.01% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 67767 0.01% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.37% # Class of executed instruction -system.cpu1.op_class::MemRead 76808885 16.05% 85.42% # Class of executed instruction -system.cpu1.op_class::MemWrite 69805486 14.58% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 354775953 69.17% 69.17% # Class of executed instruction +system.cpu1.op_class::IntMult 1066461 0.21% 69.38% # Class of executed instruction +system.cpu1.op_class::IntDiv 59336 0.01% 69.39% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.39% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 75375 0.01% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu1.op_class::MemRead 82171340 16.02% 85.42% # Class of executed instruction +system.cpu1.op_class::MemWrite 74767968 14.58% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 478619483 # Class of executed instruction -system.cpu1.dcache.tags.replacements 4731492 # number of replacements -system.cpu1.dcache.tags.tagsinuse 440.215275 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 141682703 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4732003 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.941381 # Average number of references to valid blocks. +system.cpu1.op_class::total 512916476 # Class of executed instruction +system.cpu1.dcache.tags.replacements 5113111 # number of replacements +system.cpu1.dcache.tags.tagsinuse 443.711015 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 151630595 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5113623 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.652283 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 440.215275 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.859795 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.859795 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 297963795 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 297963795 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 71617652 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 71617652 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 66171444 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 66171444 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174206 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 174206 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 185116 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 185116 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1590024 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1590024 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1548743 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1548743 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 137789096 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 137789096 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 137963302 # number of overall hits -system.cpu1.dcache.overall_hits::total 137963302 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2694357 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2694357 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1213090 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1213090 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 558664 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 558664 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466794 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 466794 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 154053 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 154053 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194127 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 194127 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 3907447 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 3907447 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4466111 # number of overall misses -system.cpu1.dcache.overall_misses::total 4466111 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40157954500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 40157954500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28157091500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 28157091500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20750751000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20750751000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2380134500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2380134500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5345117000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5345117000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6929500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6929500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 68315046000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 68315046000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 68315046000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 68315046000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 74312009 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 74312009 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 67384534 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 67384534 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 732870 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 732870 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 651910 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 651910 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1744077 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1744077 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1742870 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1742870 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 141696543 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 141696543 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 142429413 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 142429413 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036257 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036257 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018002 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018002 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.762296 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.762296 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.716041 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.716041 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088329 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088329 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111384 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111384 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027576 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027576 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031357 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031357 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14904.466817 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14904.466817 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23211.049057 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23211.049057 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 44453.765473 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 44453.765473 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15450.101588 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15450.101588 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27534.124568 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27534.124568 # average StoreCondReq miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.711015 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.866623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.866623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 319002554 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 319002554 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76632055 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76632055 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 70902064 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 70902064 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 183506 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 183506 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 192465 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 192465 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1673719 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1673719 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1647145 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1647145 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 147534119 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 147534119 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 147717625 # number of overall hits +system.cpu1.dcache.overall_hits::total 147717625 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2895739 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2895739 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1291835 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1291835 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 599128 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 599128 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 515597 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 515597 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170116 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 170116 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195350 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 195350 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4187574 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4187574 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4786702 # number of overall misses +system.cpu1.dcache.overall_misses::total 4786702 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44430252500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 44430252500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 29275459500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 29275459500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21176769000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 21176769000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2717509500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2717509500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5539928000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5539928000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5730000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5730000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 73705712000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 73705712000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 73705712000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 73705712000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79527794 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79527794 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72193899 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72193899 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 782634 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 782634 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 708062 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 708062 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843835 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1843835 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1842495 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1842495 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 151721693 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 151721693 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 152504327 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 152504327 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036412 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036412 # 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average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15398.015586 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15398.015586 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1726,157 +1717,158 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4731492 # number of writebacks -system.cpu1.dcache.writebacks::total 4731492 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13909 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 13909 # 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number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6855500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6855500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63311415500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 63311415500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75921104000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 75921104000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4287453000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4287453000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4160988000 # 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mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.716041 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063005 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063005 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111384 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111384 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027476 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027476 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031257 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031257 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13573.348560 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13573.348560 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22204.397465 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22204.397465 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22571.149206 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22571.149206 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 43453.765473 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 43453.765473 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14016.749329 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14016.749329 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26534.505762 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26534.505762 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5113111 # number of writebacks +system.cpu1.dcache.writebacks::total 5113111 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16657 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 16657 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46028 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46028 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 17059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 17059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 17059 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 17059 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879082 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2879082 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1291433 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1291433 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599128 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 599128 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 515597 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 515597 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 124088 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 124088 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195350 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 195350 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4170515 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4170515 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4769643 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4769643 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21793 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21793 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20416 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42209 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42209 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40268780500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40268780500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27960090500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27960090500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13604579000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13604579000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20661172000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20661172000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751690500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751690500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344637000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344637000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5671000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5671000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68228871000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 68228871000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81833450000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 81833450000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4030825000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4030825000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3797015500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3797015500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7827840500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7827840500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036202 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036202 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017888 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765528 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765528 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728181 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728181 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067299 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067299 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106025 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106025 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027488 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027488 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031275 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031275 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.673704 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.673704 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21650.438312 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21650.438312 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22707.299609 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22707.299609 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40072.327806 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40072.327806 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14116.518116 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14116.518116 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27359.288457 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27359.288457 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16261.987971 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16261.987971 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17053.721361 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17053.721361 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181587.099233 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181587.099233 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183951.724138 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183951.724138 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182744.067833 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182744.067833 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16359.819111 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16359.819111 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17157.143627 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17157.143627 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184959.620061 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184959.620061 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185982.342281 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185982.342281 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185454.298846 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 185454.298846 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4831573 # number of replacements -system.cpu1.icache.tags.tagsinuse 495.969883 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 401189463 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4832085 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.026160 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 5153049 # number of replacements +system.cpu1.icache.tags.tagsinuse 495.966911 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 430252201 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5153561 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 83.486390 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8408381586000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.969883 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968691 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.968691 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.966911 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968685 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.968685 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 816875196 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 816875196 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 401189463 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 401189463 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 401189463 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 401189463 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 401189463 # number of overall hits -system.cpu1.icache.overall_hits::total 401189463 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4832090 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4832090 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4832090 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4832090 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4832090 # number of overall misses -system.cpu1.icache.overall_misses::total 4832090 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52408341000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 52408341000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 52408341000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 52408341000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 52408341000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 52408341000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 406021553 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 406021553 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 406021553 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 406021553 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 406021553 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 406021553 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011901 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011901 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011901 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011901 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011901 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011901 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10845.895047 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10845.895047 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10845.895047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10845.895047 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 875965100 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 875965100 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 430252201 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 430252201 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 430252201 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 430252201 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 430252201 # number of overall hits +system.cpu1.icache.overall_hits::total 430252201 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5153566 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5153566 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5153566 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5153566 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5153566 # number of overall misses +system.cpu1.icache.overall_misses::total 5153566 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 55699016000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 55699016000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 55699016000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 55699016000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 55699016000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 55699016000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 435405767 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 435405767 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 435405767 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 435405767 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 435405767 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 435405767 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011836 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011836 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011836 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011836 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011836 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011836 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10807.859257 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10807.859257 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10807.859257 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10807.859257 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1885,252 +1877,252 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 4831573 # number of writebacks -system.cpu1.icache.writebacks::total 4831573 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4832090 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4832090 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4832090 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4832090 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4832090 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4832090 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5153049 # number of writebacks +system.cpu1.icache.writebacks::total 5153049 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5153566 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5153566 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5153566 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5153566 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5153566 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5153566 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49992296000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 49992296000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49992296000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 49992296000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49992296000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 49992296000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 53122233000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 53122233000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 53122233000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 53122233000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 53122233000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 53122233000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14799500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14799500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14799500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 14799500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011901 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011901 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011901 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10345.895047 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10345.895047 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10345.895047 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011836 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011836 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011836 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10307.859257 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6380299 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6380331 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6859303 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6859383 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 802101 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 1778912 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13269.685648 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 14051315 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1794926 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.828353 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10084696105000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12213.003078 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.894206 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 34.650770 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 988.137594 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.745423 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002069 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002115 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060311 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.809917 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1110 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14818 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 669 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 184 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 972 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4464 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8114 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1200 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067749 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.904419 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 324313053 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 324313053 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 211999 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140481 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 352480 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 2988895 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 2988895 # 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number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 211999 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140481 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4410501 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3295662 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8058643 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 211999 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140481 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4410501 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3295662 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8058643 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9285 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7506 # 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number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 831569 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 263822 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 263822 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9285 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7506 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 421589 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1067082 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1505462 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9285 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7506 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 421589 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1067082 # 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number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 12440298999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16234081000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16234081000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29105216000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29105216000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18219271500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 18219271500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 349092500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 301051000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16234081000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 41545514999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 58429739499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 349092500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 301051000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16234081000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 41545514999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 58429739499 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 221284 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 147987 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 369271 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2988895 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 2988895 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6573071 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6573071 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 201582 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 201582 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194101 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 194101 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 26 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 26 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 718 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 459 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1004 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4268 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6358 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2989 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.083923 # 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mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087453 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.241954 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241954 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.526711 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.526711 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237838 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154321 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237838 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220047 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.760586 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45637.195902 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31932.354241 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31932.354241 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19030.989016 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19030.989016 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242326.923077 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242326.923077 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.471993 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.471993 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32506.889411 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28969.286266 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28969.286266 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63058.903575 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63058.903575 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32583.945172 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36326.940014 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.217094 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 40065.171060 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43785.328080 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31874.992652 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31874.992652 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19854.780249 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19854.780249 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 348566.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 348566.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44710.637580 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44710.637580 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32004.071508 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31158.050230 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31158.050230 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61513.666347 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61513.666347 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33588.698998 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36537.046190 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173566.134429 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173350.385734 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176425.817860 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176425.817860 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176944.775845 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176694.151486 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178460.692594 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178460.692594 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174965.326296 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174851.567726 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 177678.007060 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 177546.385784 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 19832170 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10173061 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1095 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1632026 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1631848 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 178 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 456067 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 8724452 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22620 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22620 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 3978006 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6573071 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2099842 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 741149 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 395876 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358205 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 460652 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1084167 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1021480 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4832090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4231593 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 474723 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 464424 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14495311 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15429373 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 311743 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 489874 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 30726301 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 618432504 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588237954 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1183896 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1770272 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1209624626 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5375046 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 15685523 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.117781 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.322383 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 21257827 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10899393 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1702072 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1701871 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 509534 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9349922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 20416 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 20416 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4305236 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7031230 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2216107 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 785182 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 389899 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353464 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 462412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1157273 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1096575 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5153566 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4436249 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 522065 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 513183 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15459725 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16561050 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365076 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544187 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32930038 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 659580536 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 633491086 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395488 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1977568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1296444678 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5547167 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 16615326 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.116559 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.320932 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 13838252 88.22% 88.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1847093 11.78% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 178 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14678862 88.35% 88.35% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1936263 11.65% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 201 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15685523 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 19622729498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 16615326 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 21053645498 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175341179 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 168856163 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7248245000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7730459000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7009474930 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7526670911 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 163756499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 190640499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 268590000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 296991000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40469 # Transaction distribution -system.iobus.trans_dist::ReadResp 40469 # Transaction distribution -system.iobus.trans_dist::WriteReq 137017 # Transaction distribution -system.iobus.trans_dist::WriteResp 137017 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47986 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40402 # Transaction distribution +system.iobus.trans_dist::ReadResp 40402 # Transaction distribution +system.iobus.trans_dist::WriteReq 136652 # Transaction distribution +system.iobus.trans_dist::WriteResp 136652 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47834 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) @@ -2369,19 +2360,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231764 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231764 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122768 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231260 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354972 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354108 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47854 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2390,25 +2379,24 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156143 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355408 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355408 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513637 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37181500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7497017 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37033500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) @@ -2421,86 +2409,82 @@ system.iobus.reqLayer16.occupancy 13000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26640000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26450500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 37419000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 565570401 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 122000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 566572505 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93098000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92847000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148204000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147956000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115869 # number of replacements -system.iocache.tags.tagsinuse 11.294988 # Cycle average of tags in use -system.iocache.tags.total_refs 4 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115885 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9206093766000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.821408 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.473580 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.467099 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705937 # Average percentage of cache occupancy +system.iocache.tags.replacements 115605 # number of replacements +system.iocache.tags.tagsinuse 11.294118 # Cycle average of tags in use +system.iocache.tags.total_refs 10 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115621 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000086 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9206098021000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.822126 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.471992 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.238883 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705882 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043293 # Number of tag accesses -system.iocache.tags.data_accesses 1043293 # Number of data accesses +system.iocache.tags.tag_accesses 1041013 # Number of tag accesses +system.iocache.tags.data_accesses 1041013 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 5 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 5 # number of WriteLineReq hits system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8935 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106723 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106723 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses -system.iocache.demand_misses::total 8938 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses +system.iocache.demand_misses::total 8942 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8898 # number of overall misses -system.iocache.overall_misses::total 8938 # number of overall misses +system.iocache.overall_misses::realview.ide 8902 # number of overall misses +system.iocache.overall_misses::total 8942 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1681517592 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1686717092 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1679170514 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1684370014 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 14021691413 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 14021691413 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13974494387 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13974494387 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1681517592 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1687086092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1679170514 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1684739014 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1681517592 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1687086092 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1679170514 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1684739014 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999953 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999953 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses @@ -2508,61 +2492,61 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 188977.027647 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 188776.395299 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188628.455853 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188429.356080 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 131063.443253 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 131063.443253 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130941.731276 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130941.731276 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 188754.317744 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 188407.404831 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 188754.317744 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36073 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 188407.404831 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 35755 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3617 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3742 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.973182 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.555051 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106957 # number of writebacks -system.iocache.writebacks::total 106957 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106723 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106723 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8898 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8938 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8898 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8938 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236617592 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1239967092 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1234070514 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1237420014 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8672491413 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8672491413 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638344387 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8638344387 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1236617592 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1240186092 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1234070514 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1237639014 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1236617592 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1240186092 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1234070514 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1237639014 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999953 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.999953 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses @@ -2570,613 +2554,612 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138977.027647 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 138776.395299 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138628.455853 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 138429.356080 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 81063.443253 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 81063.443253 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80941.731276 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80941.731276 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1210264 # number of replacements -system.l2c.tags.tagsinuse 62755.466878 # Cycle average of tags in use -system.l2c.tags.total_refs 5212344 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1269955 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.104353 # Average number of references to valid blocks. +system.l2c.tags.replacements 1201728 # number of replacements +system.l2c.tags.tagsinuse 62776.329461 # Cycle average of tags in use +system.l2c.tags.total_refs 5149298 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1259663 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.087838 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 23285.968480 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 218.650031 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 386.944281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4588.836094 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10476.813165 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 13833.010748 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 53.974082 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 79.219380 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3039.104298 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3132.206690 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3660.739630 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.355316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003336 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005904 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070020 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.159863 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.211075 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001209 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.046373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.047794 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055858 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.957572 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10565 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48895 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 159 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1447 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8916 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1774 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 10274 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 36522 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.161209 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.746078 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 66950820 # Number of tag accesses -system.l2c.tags.data_accesses 66950820 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2504481 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2504481 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 166895 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 113960 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 280855 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38875 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 34247 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 73122 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 158326 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 166214 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 324540 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5191 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4009 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 435451 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 562405 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296765 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5208 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4285 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 382834 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 480125 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 262665 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2438938 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5191 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4009 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 435451 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 720731 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 296765 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4285 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 382834 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 646339 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 262665 # number of demand (read+write) hits -system.l2c.demand_hits::total 2763478 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5191 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4009 # number of overall hits -system.l2c.overall_hits::cpu0.inst 435451 # number of overall hits -system.l2c.overall_hits::cpu0.data 720731 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 296765 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4285 # number of overall hits -system.l2c.overall_hits::cpu1.inst 382834 # number of overall hits -system.l2c.overall_hits::cpu1.data 646339 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 262665 # number of overall hits -system.l2c.overall_hits::total 2763478 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 67422 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 57259 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 124681 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 14532 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11014 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25546 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 480698 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 148334 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 629032 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1519 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1645 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 47029 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 136142 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 207239 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1062 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1011 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 38755 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 73388 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 139305 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 647095 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1519 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1645 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 47029 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 616840 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5230 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 40901 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.148575 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004044 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.731400 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 66235328 # Number of tag accesses +system.l2c.tags.data_accesses 66235328 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2474359 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2474359 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 150616 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 127305 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 277921 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 34718 # 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average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127327.340689 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128180.440427 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140288.519066 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146258.531276 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 147000.358295 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155577.788132 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131258.418927 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145118.029007 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159414.235190 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153388.833474 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158957.895461 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131977.137651 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148142.002449 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161445.067594 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155217.746978 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145673.001433 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147591.274414 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157454.974150 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 138376.408746 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160160.968560 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 139401.382370 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 82463 # Transaction distribution -system.membus.trans_dist::ReadResp 738269 # Transaction distribution -system.membus.trans_dist::WriteReq 39099 # Transaction distribution -system.membus.trans_dist::WriteResp 39099 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1078222 # Transaction distribution -system.membus.trans_dist::CleanEvict 196131 # Transaction distribution -system.membus.trans_dist::UpgradeReq 410883 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 321341 # Transaction distribution -system.membus.trans_dist::UpgradeResp 158448 # Transaction distribution -system.membus.trans_dist::ReadExReq 644070 # Transaction distribution -system.membus.trans_dist::ReadExResp 620815 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 655806 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106983 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106983 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123128 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 81772 # Transaction distribution +system.membus.trans_dist::ReadResp 730632 # Transaction distribution +system.membus.trans_dist::WriteReq 38384 # Transaction distribution +system.membus.trans_dist::WriteResp 38384 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1075989 # Transaction distribution +system.membus.trans_dist::CleanEvict 189758 # Transaction distribution +system.membus.trans_dist::UpgradeReq 405662 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 313696 # Transaction distribution +system.membus.trans_dist::UpgradeResp 154281 # Transaction distribution +system.membus.trans_dist::ReadExReq 640388 # Transaction distribution +system.membus.trans_dist::ReadExResp 617827 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 648860 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106721 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106721 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122768 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28306 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4701222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4852748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5195460 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156143 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4655021 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4803735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5146104 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155875 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56612 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143440556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 143653515 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7262336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 150915851 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 600183 # Total snoops (count) -system.membus.snoop_fanout::samples 3537604 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51708 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142678316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 142886103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7257472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 150143575 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 590609 # Total snoops (count) +system.membus.snoop_fanout::samples 3503595 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3537604 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3503595 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3537604 # Request fanout histogram -system.membus.reqLayer0.occupancy 101645000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3503595 # Request fanout histogram +system.membus.reqLayer0.occupancy 101306500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 23516499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21492499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7437675124 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7402591959 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7217345032 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7154332547 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228825593 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228436684 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3230,52 +3213,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 10517449 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5725465 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1766756 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 114752 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 104186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 10566 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 82465 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3940978 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 39099 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 39099 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3582727 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1240251 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 683521 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 394463 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1077983 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 128 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1083401 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1083400 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3865739 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106983 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8168699 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6135080 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 14303779 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 247232417 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 172105066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 419337483 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2918298 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7581961 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.362851 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.483712 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 10356989 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5641244 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1705825 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 115755 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 104698 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11057 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 81774 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3879147 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38384 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38384 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3550378 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1245199 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 675855 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 385953 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1061806 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1071844 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1071844 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3804622 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106721 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7596632 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6529428 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14126060 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 228502049 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185064310 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 413566359 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2887820 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7482662 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.359179 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.482830 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4841404 63.85% 63.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2729991 36.01% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 10566 0.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4806103 64.23% 64.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2665502 35.62% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11057 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7581961 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8230397518 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7482662 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8118734038 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2646637 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2606433 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4512530115 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4223747952 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3554923231 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3725557524 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |