diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt | 5518 |
1 files changed, 2746 insertions, 2772 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index fcaa09afa..529d7a06f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.405013 # Number of seconds simulated -sim_ticks 47405012960500 # Number of ticks simulated -final_tick 47405012960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.405081 # Number of seconds simulated +sim_ticks 47405080882500 # Number of ticks simulated +final_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1080699 # Simulator instruction rate (inst/s) -host_op_rate 1271286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58247547339 # Simulator tick rate (ticks/s) -host_mem_usage 759864 # Number of bytes of host memory used -host_seconds 813.85 # Real time elapsed on the host -sim_insts 879531552 # Number of instructions simulated -sim_ops 1034641707 # Number of ops (including micro ops) simulated +host_inst_rate 1071981 # Simulator instruction rate (inst/s) +host_op_rate 1260946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57861452624 # Simulator tick rate (ticks/s) +host_mem_usage 765552 # Number of bytes of host memory used +host_seconds 819.29 # Real time elapsed on the host +sim_insts 878258906 # Number of instructions simulated +sim_ops 1033075205 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 107584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 111616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3269620 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13856200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15427200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 122176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 126272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2852024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9626320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10834112 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 432576 # Number of bytes read from this memory -system.physmem.bytes_read::total 56765700 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3269620 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2852024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6121644 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74832256 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory +system.physmem.bytes_read::total 56765124 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74852840 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1681 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 91495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 216516 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 241050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1909 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 150424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 169283 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6759 # Number of read requests responded to by this memory -system.physmem.num_reads::total 927485 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1169254 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74764392 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory +system.physmem.num_reads::total 927476 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1171828 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 68972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 292294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 325434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 60163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 203065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 228544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1197462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 68972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 60163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 129135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1578573 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1579007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1578573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 68972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 292728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 325434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 60163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 203066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 228544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2776469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 927485 # Number of read requests accepted -system.physmem.writeReqs 1171828 # Number of write requests accepted -system.physmem.readBursts 927485 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1171828 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59337472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21568 # Total number of bytes read from write queue -system.physmem.bytesWritten 74850880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56765700 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74852840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 337 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 927476 # Number of read requests accepted +system.physmem.writeReqs 1170446 # Number of write requests accepted +system.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue +system.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 53188 # Per bank write bursts -system.physmem.perBankRdBursts::1 58555 # Per bank write bursts -system.physmem.perBankRdBursts::2 49548 # Per bank write bursts -system.physmem.perBankRdBursts::3 58849 # Per bank write bursts -system.physmem.perBankRdBursts::4 61060 # Per bank write bursts -system.physmem.perBankRdBursts::5 64213 # Per bank write bursts -system.physmem.perBankRdBursts::6 58593 # Per bank write bursts -system.physmem.perBankRdBursts::7 62574 # Per bank write bursts -system.physmem.perBankRdBursts::8 53530 # Per bank write bursts -system.physmem.perBankRdBursts::9 96457 # Per bank write bursts -system.physmem.perBankRdBursts::10 50033 # Per bank write bursts -system.physmem.perBankRdBursts::11 57571 # Per bank write bursts -system.physmem.perBankRdBursts::12 47029 # Per bank write bursts -system.physmem.perBankRdBursts::13 51615 # Per bank write bursts -system.physmem.perBankRdBursts::14 49510 # Per bank write bursts -system.physmem.perBankRdBursts::15 54823 # Per bank write bursts -system.physmem.perBankWrBursts::0 69378 # Per bank write bursts -system.physmem.perBankWrBursts::1 74382 # Per bank write bursts -system.physmem.perBankWrBursts::2 69427 # Per bank write bursts -system.physmem.perBankWrBursts::3 75087 # Per bank write bursts -system.physmem.perBankWrBursts::4 76532 # Per bank write bursts -system.physmem.perBankWrBursts::5 78990 # Per bank write bursts -system.physmem.perBankWrBursts::6 75385 # Per bank write bursts -system.physmem.perBankWrBursts::7 77589 # Per bank write bursts -system.physmem.perBankWrBursts::8 70916 # Per bank write bursts -system.physmem.perBankWrBursts::9 76207 # Per bank write bursts -system.physmem.perBankWrBursts::10 70858 # Per bank write bursts -system.physmem.perBankWrBursts::11 75862 # Per bank write bursts -system.physmem.perBankWrBursts::12 66596 # Per bank write bursts -system.physmem.perBankWrBursts::13 70423 # Per bank write bursts -system.physmem.perBankWrBursts::14 68869 # Per bank write bursts -system.physmem.perBankWrBursts::15 73044 # Per bank write bursts +system.physmem.perBankRdBursts::0 53525 # Per bank write bursts +system.physmem.perBankRdBursts::1 58700 # Per bank write bursts +system.physmem.perBankRdBursts::2 53136 # Per bank write bursts +system.physmem.perBankRdBursts::3 59915 # Per bank write bursts +system.physmem.perBankRdBursts::4 57558 # Per bank write bursts +system.physmem.perBankRdBursts::5 67025 # Per bank write bursts +system.physmem.perBankRdBursts::6 57593 # Per bank write bursts +system.physmem.perBankRdBursts::7 57551 # Per bank write bursts +system.physmem.perBankRdBursts::8 45941 # Per bank write bursts +system.physmem.perBankRdBursts::9 94599 # Per bank write bursts +system.physmem.perBankRdBursts::10 49635 # Per bank write bursts +system.physmem.perBankRdBursts::11 57294 # Per bank write bursts +system.physmem.perBankRdBursts::12 48522 # Per bank write bursts +system.physmem.perBankRdBursts::13 56965 # Per bank write bursts +system.physmem.perBankRdBursts::14 52794 # Per bank write bursts +system.physmem.perBankRdBursts::15 56368 # Per bank write bursts +system.physmem.perBankWrBursts::0 71875 # Per bank write bursts +system.physmem.perBankWrBursts::1 75753 # Per bank write bursts +system.physmem.perBankWrBursts::2 71549 # Per bank write bursts +system.physmem.perBankWrBursts::3 77042 # Per bank write bursts +system.physmem.perBankWrBursts::4 73392 # Per bank write bursts +system.physmem.perBankWrBursts::5 80022 # Per bank write bursts +system.physmem.perBankWrBursts::6 71461 # Per bank write bursts +system.physmem.perBankWrBursts::7 73088 # Per bank write bursts +system.physmem.perBankWrBursts::8 65465 # Per bank write bursts +system.physmem.perBankWrBursts::9 74249 # Per bank write bursts +system.physmem.perBankWrBursts::10 70475 # Per bank write bursts +system.physmem.perBankWrBursts::11 74236 # Per bank write bursts +system.physmem.perBankWrBursts::12 69250 # Per bank write bursts +system.physmem.perBankWrBursts::13 75271 # Per bank write bursts +system.physmem.perBankWrBursts::14 70641 # Per bank write bursts +system.physmem.perBankWrBursts::15 74378 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 516 # Number of times write queue was full causing retry -system.physmem.totGap 47405009605000 # Total gap between requests +system.physmem.numWrRetry 399 # Number of times write queue was full causing retry +system.physmem.totGap 47405077592000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 884260 # Read request sizes (log2) +system.physmem.readPktSize::6 884251 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1169254 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 645919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 21962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1167872 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 648346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 87693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,129 +189,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 36458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 65994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 70176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 73600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 75174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 71278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1170 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 929017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 144.440810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.331936 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 191.352121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 617371 66.45% 66.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189527 20.40% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44674 4.81% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20356 2.19% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14838 1.60% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9142 0.98% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6196 0.67% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5371 0.58% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21542 2.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 929017 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60832 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.240992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.606668 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60830 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 28770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 36931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 65505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 73447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 75382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 70493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 71352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 68341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 921 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 928498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 144.423393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.327252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.341879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 616929 66.44% 66.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189662 20.43% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44616 4.81% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20270 2.18% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14755 1.59% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9179 0.99% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6168 0.66% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5453 0.59% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21466 2.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 928498 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60682 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.278254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.725132 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60680 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60832 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.225819 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.418138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.471341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49295 81.03% 81.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4521 7.43% 88.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2878 4.73% 93.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1749 2.88% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1023 1.68% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 226 0.37% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 91 0.15% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 113 0.19% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 47 0.08% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.04% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.02% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 42 0.07% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 494 0.81% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 82 0.13% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 51 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 57 0.09% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 26 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 21 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 13 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60832 # Writes before turning the bus around for reads -system.physmem.totQLat 46218732203 # Total ticks spent queuing -system.physmem.totMemAccLat 63602757203 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4635740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 49850.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60682 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.250305 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.439777 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.504538 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 53685 88.47% 88.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 4623 7.62% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 1219 2.01% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 192 0.32% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 86 0.14% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 66 0.11% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 562 0.93% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 118 0.19% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 38 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 2 0.00% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 28 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 15 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads +system.physmem.totQLat 46391884854 # Total ticks spent queuing +system.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68600.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s @@ -320,53 +303,53 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing -system.physmem.readRowHits 685692 # Number of row buffer hits during reads -system.physmem.writeRowHits 481982 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes -system.physmem.avgGap 22581201.38 # Average gap between requests +system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing +system.physmem.readRowHits 687053 # Number of row buffer hits during reads +system.physmem.writeRowHits 479716 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes +system.physmem.avgGap 22596205.96 # Average gap between requests system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3446827860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1832028660 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3331381200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3115139400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 41510941680.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 46501533090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2234866560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 80625696300 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 57761558880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11279719224960 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11520096687780 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.014314 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47297174723637 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3911587994 # Time in different power states -system.physmem_0.memoryStateTime::REF 17636282000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 46969945639000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 150420602883 # Time in different power states -system.physmem_0.memoryStateTime::ACT 86288423369 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 176810425254 # Time in different power states -system.physmem_1.actEnergy 3186367800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1693590855 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3288455520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2989885500 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 39461117280.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47361781080 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2153404320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 72224847060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 55366694400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11285008491285 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11512750460370 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.859346 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47295506898407 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3731843770 # Time in different power states -system.physmem_1.memoryStateTime::REF 16766470000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 46992934432500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 144184093324 # Time in different power states -system.physmem_1.memoryStateTime::ACT 89007700573 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 158388420333 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.004907 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states +system.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states +system.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.918480 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states +system.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states +system.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -393,9 +376,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -403,7 +386,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -433,71 +416,72 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 110745 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 110745 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10295 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84545 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 110723 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.234820 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 78.136585 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 110722 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 105104 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 110723 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 94862 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 93763 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 840 0.89% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 113 0.12% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 94862 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -2682325288 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 2.121047 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 3007013124 -112.10% -112.10% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -5689338412 212.10% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -2682325288 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 84546 89.14% 89.14% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10295 10.86% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 94841 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 110745 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 110745 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94841 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 205586 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86849149 # DTB read hits -system.cpu0.dtb.read_misses 83538 # DTB read misses -system.cpu0.dtb.write_hits 78785461 # DTB write hits -system.cpu0.dtb.write_misses 27207 # DTB write misses +system.cpu0.dtb.read_hits 85250979 # DTB read hits +system.cpu0.dtb.read_misses 79026 # DTB read misses +system.cpu0.dtb.write_hits 77401552 # DTB write hits +system.cpu0.dtb.write_misses 26078 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37555 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4746 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9443 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86932687 # DTB read accesses -system.cpu0.dtb.write_accesses 78812668 # DTB write accesses +system.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85330005 # DTB read accesses +system.cpu0.dtb.write_accesses 77427630 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 165634610 # DTB hits -system.cpu0.dtb.misses 110745 # DTB misses -system.cpu0.dtb.accesses 165745355 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 162652531 # DTB hits +system.cpu0.dtb.misses 105104 # DTB misses +system.cpu0.dtb.accesses 162757635 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -527,763 +511,759 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 57780 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57780 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 572 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51544 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 57780 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57780 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57780 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52116 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25803.102694 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 51056 97.97% 97.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 692 1.33% 99.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 219 0.42% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 60 0.12% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 14 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 55600 # Table walker walks requested +system.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51544 98.90% 98.90% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 572 1.10% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52116 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57780 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57780 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52116 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52116 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 109896 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 463942995 # ITB inst hits -system.cpu0.itb.inst_misses 57780 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 455710659 # ITB inst hits +system.cpu0.itb.inst_misses 55600 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26477 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 464000775 # ITB inst accesses -system.cpu0.itb.hits 463942995 # DTB hits -system.cpu0.itb.misses 57780 # DTB misses -system.cpu0.itb.accesses 464000775 # DTB accesses -system.cpu0.numPwrStateTransitions 8984 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 4492 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 10426010818.709705 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 169261679723.888153 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3260 72.57% 72.57% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1205 26.83% 99.40% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 8 0.18% 99.58% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.60% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 12 0.27% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 455766259 # ITB inst accesses +system.cpu0.itb.hits 455710659 # DTB hits +system.cpu0.itb.misses 55600 # DTB misses +system.cpu0.itb.accesses 455766259 # DTB accesses +system.cpu0.numPwrStateTransitions 25961 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7033293863000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 4492 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 571372362856 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94810025915 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94809604801 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4492 # number of quiesce instructions executed -system.cpu0.committedInsts 463690677 # Number of instructions committed -system.cpu0.committedOps 544305781 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 499985272 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 430429 # Number of float alu accesses -system.cpu0.num_func_calls 27825312 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 70353837 # number of instructions that are conditional controls -system.cpu0.num_int_insts 499985272 # number of integer instructions -system.cpu0.num_fp_insts 430429 # number of float instructions -system.cpu0.num_int_register_reads 725660016 # number of times the integer registers were read -system.cpu0.num_int_register_writes 396645033 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 713342 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 322808 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 121489824 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 121106505 # number of times the CC registers were written -system.cpu0.num_mem_refs 165624912 # number of memory refs -system.cpu0.num_load_insts 86844124 # Number of load instructions -system.cpu0.num_store_insts 78780788 # Number of store instructions -system.cpu0.num_idle_cycles 93667281189.358337 # Number of idle cycles -system.cpu0.num_busy_cycles 1142744725.641658 # Number of busy cycles -system.cpu0.not_idle_fraction 0.012053 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.987947 # Percentage of idle cycles -system.cpu0.Branches 103560532 # Number of branches fetched +system.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed +system.cpu0.committedInsts 455440444 # Number of instructions committed +system.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses +system.cpu0.num_func_calls 27345084 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls +system.cpu0.num_int_insts 490602455 # number of integer instructions +system.cpu0.num_fp_insts 409464 # number of float instructions +system.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read +system.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written +system.cpu0.num_mem_refs 162644052 # number of memory refs +system.cpu0.num_load_insts 85246888 # Number of load instructions +system.cpu0.num_store_insts 77397164 # Number of store instructions +system.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles +system.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988028 # Percentage of idle cycles +system.cpu0.Branches 101837898 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 377679680 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1190205 0.22% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 61578 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMisc 44848 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 86795135 15.94% 85.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 78444196 14.40% 99.93% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 48989 0.01% 99.94% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 336592 0.06% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction +system.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction +system.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction +system.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 544601223 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5731745 # number of replacements -system.cpu0.dcache.tags.tagsinuse 479.859189 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 159669170 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5732255 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.854513 # Average number of references to valid blocks. +system.cpu0.op_class::total 534571495 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5548235 # number of replacements +system.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.859189 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937225 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.937225 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 452 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 337018109 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 337018109 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80850678 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80850678 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74290365 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74290365 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 206988 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 206988 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 237888 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 237888 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1848102 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1848102 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1813975 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1813975 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 155378931 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 155378931 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 155585919 # number of overall hits -system.cpu0.dcache.overall_hits::total 155585919 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3109712 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3109712 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1421405 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1421405 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649654 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 649654 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796576 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 796576 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167654 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 167654 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200528 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200528 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5327693 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5327693 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5977347 # number of overall misses -system.cpu0.dcache.overall_misses::total 5977347 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 48841831500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 48841831500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 30112535000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 30112535000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25700725500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25700725500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2575322000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2575322000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4758884500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4758884500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2246000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 104655092000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 104655092000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 104655092000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 104655092000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83960390 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83960390 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75711770 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75711770 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 856642 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 856642 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1034464 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1034464 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015756 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2015756 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014503 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2014503 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160706624 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 160706624 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161563266 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 161563266 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037038 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037038 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018774 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018774 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758373 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.758373 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.770037 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.770037 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083172 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083172 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033152 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033152 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036997 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036997 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15706.223438 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15706.223438 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21185.049300 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21185.049300 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32263.996781 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32263.996781 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.933828 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.933828 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23731.770626 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23731.770626 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.308001 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992789 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.992789 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 330814481 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 330814481 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 79405965 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 79405965 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72971377 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72971377 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204972 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 204972 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263219 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 263219 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813440 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1813440 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787735 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1787735 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 152640561 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 152640561 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 152845533 # number of overall hits +system.cpu0.dcache.overall_hits::total 152845533 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3006341 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3006341 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1360477 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1360477 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 626311 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 626311 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 794287 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 794287 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164142 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 164142 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188530 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 188530 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5161105 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5161105 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5787416 # number of overall misses +system.cpu0.dcache.overall_misses::total 5787416 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47850868000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 47850868000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29377875000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29377875000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25259415500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 25259415500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2486803500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2486803500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4498365000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4498365000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2057500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2057500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 102488158500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 102488158500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 102488158500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 102488158500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 82412306 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 82412306 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74331854 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74331854 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 831283 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 831283 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1057506 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1057506 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1977582 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1977582 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1976265 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1976265 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 157801666 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 157801666 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 158632949 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 158632949 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036479 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036479 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018303 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018303 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.753427 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.753427 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.751095 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.751095 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083001 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083001 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095397 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095397 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032706 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032706 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036483 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036483 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21593.804967 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21593.804967 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31801.370915 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31801.370915 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15150.318017 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15150.318017 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23860.207924 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19643.604089 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19643.604089 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17508.619125 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17508.619125 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19857.793728 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19857.793728 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17708.794132 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5731745 # number of writebacks -system.cpu0.dcache.writebacks::total 5731745 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26385 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 26385 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21245 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21245 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44162 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44162 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 47630 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 47630 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 47630 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 47630 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3083327 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3083327 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1400160 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1400160 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648080 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 648080 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796576 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 796576 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123492 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123492 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200528 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 200528 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5280063 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5280063 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5928143 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5928143 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16381 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34075 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44323294000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44323294000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28148510000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28148510000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14944693500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14944693500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24904149500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24904149500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1681387500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1681387500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4558410500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4558410500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2192000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2192000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 97375953500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 97375953500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 112320647000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3040589500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3040589500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3040589500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3040589500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036724 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036724 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018493 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018493 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756535 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756535 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.770037 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.770037 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061263 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061263 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099542 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099542 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032855 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032855 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036692 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5548235 # number of writebacks +system.cpu0.dcache.writebacks::total 5548235 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26826 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 26826 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21220 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21220 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43038 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43038 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 48046 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 48046 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 48046 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 48046 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2979515 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2979515 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1339257 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1339257 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 624730 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 624730 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 794287 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 794287 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121104 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 188530 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5113059 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5113059 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5737789 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5737789 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59187 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43367868500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43367868500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27478579500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27478579500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14655261000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14655261000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24465128500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24465128500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1605767000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4309885000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4309885000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2007500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2007500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95311576500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 95311576500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109966837500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 109966837500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5687970000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018017 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018017 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.751525 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751525 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.751095 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.751095 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061238 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061238 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095397 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095397 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032402 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032402 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036170 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036170 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14555.344914 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14555.344914 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20517.779261 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20517.779261 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23458.551694 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30801.370915 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30801.370915 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13259.405139 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22860.473134 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22860.473134 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 4959559 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.903947 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 458982923 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4960071 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 92.535555 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30768955000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903947 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18640.812965 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18640.812965 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19165.367967 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19165.367967 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190692.302535 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190692.302535 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96101.677733 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96101.677733 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 4928137 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.903899 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 450782010 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4928649 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 91.461577 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30794452000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903899 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 932846061 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 932846061 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 458982923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 458982923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 458982923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 458982923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 458982923 # number of overall hits -system.cpu0.icache.overall_hits::total 458982923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4960072 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4960072 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4960072 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4960072 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4960072 # number of overall misses -system.cpu0.icache.overall_misses::total 4960072 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54306348500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 54306348500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 54306348500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 54306348500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 54306348500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 54306348500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 463942995 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 463942995 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 463942995 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 463942995 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 463942995 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 463942995 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010691 # 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average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010815 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010815 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010815 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10459.639345 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7732053 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7732077 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7424522 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7424525 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1019171 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2286879 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15893.622807 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9162734 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2302009 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.980321 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5406430500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 29.949034 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 16.856945 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 242.920764 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.952386 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001828 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001029 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014827 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.970070 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 306 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14757 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 139 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 67 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4608 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8403 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1616 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018677 # 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average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 22159208 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11368269 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 619514 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 619512 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 553426 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9465318 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 17695 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 17694 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5316723 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6896635 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1098455 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 916448 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 433150 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 369627 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 506111 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1214944 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1192020 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4960072 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4756139 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 842201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 794505 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14965952 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18512478 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327835 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 591529 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34397794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 635028820 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696134983 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2161912 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1334567371 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5130075 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 104832276 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 16684270 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.051566 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.221149 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5091046 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15823936 94.84% 94.84% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 860332 5.16% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 16684270 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 21945410994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 195855793 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7483231500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8196031021 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 172628000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 321290000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1439,71 +1418,72 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 99152 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 99152 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8586 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75770 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 99148 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.080687 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 25.406685 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 99147 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 105151 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 99148 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 84360 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 83116 98.53% 98.53% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 940 1.11% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.19% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 58 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 84360 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 407519048 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 2.490877 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -607560648 -149.09% -149.09% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1015079696 249.09% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 407519048 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 75770 89.82% 89.82% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8586 10.18% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 84356 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99152 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99152 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84356 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84356 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 183508 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 78885011 # DTB read hits -system.cpu1.dtb.read_misses 72039 # DTB read misses -system.cpu1.dtb.write_hits 71761800 # DTB write hits -system.cpu1.dtb.write_misses 27113 # DTB write misses +system.cpu1.dtb.read_hits 80227147 # DTB read hits +system.cpu1.dtb.read_misses 76874 # DTB read misses +system.cpu1.dtb.write_hits 72873093 # DTB write hits +system.cpu1.dtb.write_misses 28277 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36637 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3802 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10123 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 78957050 # DTB read accesses -system.cpu1.dtb.write_accesses 71788913 # DTB write accesses +system.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 80304021 # DTB read accesses +system.cpu1.dtb.write_accesses 72901370 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 150646811 # DTB hits -system.cpu1.dtb.misses 99152 # DTB misses -system.cpu1.dtb.accesses 150745963 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 153100240 # DTB hits +system.cpu1.dtb.misses 105151 # DTB misses +system.cpu1.dtb.accesses 153205391 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1533,763 +1513,763 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 58316 # Table walker walks requested -system.cpu1.itb.walker.walksLong 58316 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52495 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 58316 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 58316 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 58316 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53121 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27183.693831 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 51734 97.39% 97.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 949 1.79% 99.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 242 0.46% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.15% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 33 0.06% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53121 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -615394148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -615394148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -615394148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 52495 98.82% 98.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 626 1.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53121 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 60537 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58316 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58316 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53121 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53121 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 111437 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 416140593 # ITB inst hits -system.cpu1.itb.inst_misses 58316 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 423099313 # ITB inst hits +system.cpu1.itb.inst_misses 60537 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25699 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 416198909 # ITB inst accesses -system.cpu1.itb.hits 416140593 # DTB hits -system.cpu1.itb.misses 58316 # DTB misses -system.cpu1.itb.accesses 416198909 # DTB accesses -system.cpu1.numPwrStateTransitions 28692 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 14346 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3269284130.341071 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 86001867955.202789 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3953 27.55% 27.55% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10364 72.24% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 423159850 # ITB inst accesses +system.cpu1.itb.hits 423099313 # DTB hits +system.cpu1.itb.misses 60537 # DTB misses +system.cpu1.itb.accesses 423159850 # DTB accesses +system.cpu1.numPwrStateTransitions 11486 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7510077904252 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 14346 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 503862826627 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94810025921 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94810161765 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14346 # number of quiesce instructions executed -system.cpu1.committedInsts 415840875 # Number of instructions committed -system.cpu1.committedOps 490335926 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 450775425 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 467875 # Number of float alu accesses -system.cpu1.num_func_calls 24835210 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 63203882 # number of instructions that are conditional controls -system.cpu1.num_int_insts 450775425 # number of integer instructions -system.cpu1.num_fp_insts 467875 # number of float instructions -system.cpu1.num_int_register_reads 655878523 # number of times the integer registers were read -system.cpu1.num_int_register_writes 357644258 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 746575 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 415812 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 107608929 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 107374492 # number of times the CC registers were written -system.cpu1.num_mem_refs 150638767 # number of memory refs -system.cpu1.num_load_insts 78882725 # Number of load instructions -system.cpu1.num_store_insts 71756042 # Number of store instructions -system.cpu1.num_idle_cycles 93802300267.744019 # Number of idle cycles -system.cpu1.num_busy_cycles 1007725653.255979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010629 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989371 # Percentage of idle cycles -system.cpu1.Branches 92635099 # Number of branches fetched +system.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed +system.cpu1.committedInsts 422818462 # Number of instructions committed +system.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses +system.cpu1.num_func_calls 25225246 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls +system.cpu1.num_int_insts 458669371 # number of integer instructions +system.cpu1.num_fp_insts 488965 # number of float instructions +system.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read +system.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written +system.cpu1.num_mem_refs 153090665 # number of memory refs +system.cpu1.num_load_insts 80223644 # Number of load instructions +system.cpu1.num_store_insts 72867021 # Number of store instructions +system.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles +system.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989313 # Percentage of idle cycles +system.cpu1.Branches 94103649 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 338840052 69.06% 69.06% # Class of executed instruction -system.cpu1.op_class::IntMult 1031473 0.21% 69.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 58381 0.01% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 8 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatCmp 13 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatCvt 21 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.28% # Class of executed instruction -system.cpu1.op_class::FloatMisc 67037 0.01% 69.30% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::MemRead 78824615 16.07% 85.36% # Class of executed instruction -system.cpu1.op_class::MemWrite 71413356 14.56% 99.92% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 58110 0.01% 99.93% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 342686 0.07% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction +system.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction +system.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction +system.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 490635753 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 4949273 # number of replacements -system.cpu1.dcache.tags.tagsinuse 456.328608 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 145491110 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4949785 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.393420 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379669141000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.328608 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891267 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.891267 # Average percentage of cache occupancy +system.cpu1.op_class::total 499098010 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5131141 # number of replacements +system.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 306227498 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 306227498 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 73475131 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73475131 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68103188 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68103188 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168046 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 168046 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 87192 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 87192 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1644934 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1644934 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602204 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1602204 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 141665511 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 141665511 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 141833557 # number of overall hits -system.cpu1.dcache.overall_hits::total 141833557 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2804863 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2804863 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1292961 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1292961 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609189 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 609189 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 443031 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 443031 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160663 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 160663 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202242 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 202242 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4540855 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4540855 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5150044 # number of overall misses -system.cpu1.dcache.overall_misses::total 5150044 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42649111500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 42649111500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25017964000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 25017964000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10518897000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10518897000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2505987000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2505987000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4791659000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4791659000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2159000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2159000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 78185972500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 78185972500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 78185972500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 78185972500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76279994 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76279994 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69396149 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69396149 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 777235 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 777235 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 530223 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 530223 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1805597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1805597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1804446 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1804446 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 146206366 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146206366 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 146983601 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 146983601 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036771 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036771 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018632 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018632 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783790 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783790 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.835556 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.835556 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088981 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112080 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112080 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031058 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031058 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035038 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035038 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60851 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 60851 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1670690 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1670690 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1646008 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1646008 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 143907086 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 143907086 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 144074861 # number of overall hits +system.cpu1.dcache.overall_hits::total 144074861 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2897407 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2897407 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1336766 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1336766 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634591 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 634591 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446061 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 446061 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170887 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 170887 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194464 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 194464 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4680234 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4680234 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5314825 # number of overall misses +system.cpu1.dcache.overall_misses::total 5314825 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43647010000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 43647010000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25591315500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 25591315500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9621405000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 9621405000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2591957500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2591957500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4654513500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4654513500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 78859730500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 78859730500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 78859730500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 78859730500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 77574498 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 77574498 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70505910 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70505910 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 802366 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 802366 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 506912 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 506912 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1841577 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1841577 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1840472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1840472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 148587320 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 148587320 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 149389686 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 149389686 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037350 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037350 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018960 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018960 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790900 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790900 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.879957 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.879957 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092794 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092794 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105660 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105660 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031498 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031498 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035577 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035577 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15064.162543 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15064.162543 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19144.199882 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19144.199882 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 21569.706834 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 21569.706834 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15167.669279 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15167.669279 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23935.090814 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23935.090814 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17218.337185 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15181.612526 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16849.527289 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16849.527289 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14837.690893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14837.690893 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 4949273 # number of writebacks -system.cpu1.dcache.writebacks::total 4949273 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18154 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18154 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 423 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 423 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43805 # 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number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 443031 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116858 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116858 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202242 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 202242 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4522278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4522278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5131467 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5131467 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22203 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42958 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38628648000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38628648000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23695979500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23695979500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13886318000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13886318000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10075866000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10075866000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623112500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1623112500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4589466000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4589466000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2110000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2110000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72400493500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 72400493500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 86286811500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 86286811500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3923399500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3923399500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3923399500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3923399500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036533 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036533 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018626 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018626 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783790 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783790 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.835556 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.835556 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064720 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064720 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112080 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112080 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030931 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030931 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034912 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034912 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5131141 # number of writebacks +system.cpu1.dcache.writebacks::total 5131141 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17932 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 17932 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 468 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 468 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44381 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44381 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 18400 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 18400 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 18400 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 18400 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879475 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2879475 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1336298 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1336298 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634591 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 634591 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446061 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 446061 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194464 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 194464 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4661834 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4661834 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5296425 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5296425 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8724 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17779 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39613799000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39613799000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24222435000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24222435000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14015397000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14015397000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9175344000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9175344000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1695802000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1695802000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4460100500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4460100500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2195000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2195000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73011578000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 73011578000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87026975000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 87026975000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1272776000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1272776000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037119 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037119 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018953 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018953 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790900 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790900 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879957 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879957 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068694 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068694 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105660 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105660 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031374 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031374 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035454 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035454 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13757.299160 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13757.299160 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18126.521928 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18126.521928 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22085.716627 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 20569.706834 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 20569.706834 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13404.913601 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22935.353073 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22935.353073 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4981311 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.212019 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 411158765 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4981823 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 82.531789 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8379594860000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.212019 # Average occupied blocks per requestor +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15661.556804 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15661.556804 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16431.267317 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16431.267317 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145893.626777 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 145893.626777 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 71588.728275 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 71588.728275 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5003710 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.211749 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 418095086 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5004222 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 83.548469 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8379626352000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.211749 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 837263014 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 837263014 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 411158765 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 411158765 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 411158765 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 411158765 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 411158765 # number of overall hits -system.cpu1.icache.overall_hits::total 411158765 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4981828 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4981828 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4981828 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4981828 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4981828 # number of overall misses -system.cpu1.icache.overall_misses::total 4981828 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54111358000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 54111358000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 54111358000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 54111358000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 54111358000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 54111358000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 416140593 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 416140593 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 416140593 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 416140593 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 416140593 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 416140593 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011972 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011972 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011972 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011972 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011972 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011972 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10861.747535 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10861.747535 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10861.747535 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10861.747535 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 851202853 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 851202853 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 418095086 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 418095086 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 418095086 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 418095086 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 418095086 # number of overall hits +system.cpu1.icache.overall_hits::total 418095086 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5004227 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5004227 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5004227 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5004227 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5004227 # number of overall misses +system.cpu1.icache.overall_misses::total 5004227 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54129933000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 54129933000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 54129933000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 54129933000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 54129933000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 54129933000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 423099313 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 423099313 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 423099313 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 423099313 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 423099313 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 423099313 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011828 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011828 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011828 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011828 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011828 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011828 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10816.842042 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10816.842042 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10816.842042 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10816.842042 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4981311 # number of writebacks -system.cpu1.icache.writebacks::total 4981311 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4981828 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4981828 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4981828 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4981828 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4981828 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4981828 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5003710 # number of writebacks +system.cpu1.icache.writebacks::total 5003710 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5004227 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5004227 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5004227 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5004227 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5004227 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5004227 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51620444000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 51620444000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51620444000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 51620444000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51620444000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 51620444000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10472000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10472000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10472000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10472000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011972 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011972 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011972 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10361.747535 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95200 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95200 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6872416 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6872436 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 18 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51627819500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 51627819500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51627819500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 51627819500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51627819500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 51627819500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10917500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10917500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10917500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011828 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011828 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011828 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10316.842042 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99250 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99250 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7173608 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7173625 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 852028 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1861043 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 12976.163549 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 8767962 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1876890 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.671537 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 895743 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 1888854 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13151.739114 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 8987368 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1904692 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.718541 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12709.863020 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.854479 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 23.050365 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 215.395684 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.775748 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001700 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001407 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013147 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.792002 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 377 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15415 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 69 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 165 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1400 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5858 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4122 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3918 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.023010 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940857 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 342605185 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 342605185 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 220532 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 147847 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 368379 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3122709 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3122709 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6807120 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6807120 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 835381 # 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number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 220532 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 147847 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4529100 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3458960 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8356439 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 17957 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10279 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 28236 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208369 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 208369 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202239 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 202239 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 250965 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 250965 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 452728 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 452728 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 889177 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 889177 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 249433 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 249433 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 17957 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10279 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 452728 # 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number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 333590500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 333590500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2035999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2035999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11238175000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11238175000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16933068500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16933068500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31773824000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31773824000 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 70 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 46 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1447 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5487 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7313 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1113 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # 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average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20600525 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10578683 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 558580 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 558580 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 484798 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9068801 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 20755 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 20755 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4199993 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6807874 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1098101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 809012 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 385894 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368515 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 474989 # Transaction distribution +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1114310 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1093127 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4981828 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4385137 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 490192 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 441051 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14945187 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16097398 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332311 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 526789 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 31901685 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 637641336 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617397659 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1265008 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1907912 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1258211915 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4504290 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 75632944 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 15215883 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.052359 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.222750 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4569933 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14419192 94.76% 94.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 796691 5.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15215883 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20375325498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176794994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7472852000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7357432377 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 174185000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 288300000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40355 # Transaction distribution -system.iobus.trans_dist::ReadResp 40355 # Transaction distribution -system.iobus.trans_dist::WriteReq 136628 # Transaction distribution -system.iobus.trans_dist::WriteResp 136628 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40383 # Transaction distribution +system.iobus.trans_dist::ReadResp 40383 # Transaction distribution +system.iobus.trans_dist::WriteReq 136636 # Transaction distribution +system.iobus.trans_dist::WriteResp 136636 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2431,15 +2410,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2450,105 +2429,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155799 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36982500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36934001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 319001 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26451500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25636500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37417000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37418000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569427501 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570101370 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92787000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115615 # number of replacements -system.iocache.tags.tagsinuse 11.298649 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115614 # number of replacements +system.iocache.tags.tagsinuse 11.296592 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9136560427000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.416178 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.882471 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463511 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242654 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706166 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9136749782000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841541 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.455051 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240096 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465941 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706037 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040856 # Number of tag accesses -system.iocache.tags.data_accesses 1040856 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041054 # Number of tag accesses +system.iocache.tags.data_accesses 1041054 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses -system.iocache.demand_misses::total 115651 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses +system.iocache.demand_misses::total 115673 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115611 # number of overall misses -system.iocache.overall_misses::total 115651 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5193500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1828649003 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1833842503 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115633 # number of overall misses +system.iocache.overall_misses::total 115673 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1975225504 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1980423504 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13346157998 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13346157998 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5562500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15174807001 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15180369501 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5562500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15174807001 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15180369501 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13261468866 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13261468866 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15236694370 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15242261370 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15236694370 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15242261370 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2562,53 +2541,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 205587.724552 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 221810.837058 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 221474.335048 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125048.328442 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131260.166371 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131260.166371 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 41899 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124254.824095 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 124254.824095 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131770.260735 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131770.260735 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 49344 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3519 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.852617 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.022165 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106702 # number of writebacks -system.iocache.writebacks::total 106702 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3343500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1384499003 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1387842503 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529975504 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1533323504 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8000796585 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8000796585 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3562500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9385295588 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9388858088 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3562500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9385295588 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9388858088 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7919102558 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7919102558 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9449078062 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9452645062 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9449078062 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9452645062 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2622,659 +2601,654 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171810.837058 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 171474.335048 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74964.363475 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74964.363475 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81182.679683 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 128.223998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 149.509582 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3193.954857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6240.562219 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5949.868833 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.180717 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004651 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.005443 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.054714 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.291221 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002281 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.048736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.095223 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.090788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992758 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11266 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 259 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48663 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 297 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 10816 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74198.922101 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74198.922101 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1381741 # number of replacements +system.l2c.tags.tagsinuse 65067.880129 # Cycle average of tags in use +system.l2c.tags.total_refs 5923587 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1442494 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.106490 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9880371500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 12193.656277 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.628854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 215.563389 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4072.894051 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 15215.630293 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9216.886744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.489010 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 298.478725 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2688.288956 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9916.445518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10812.918313 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.186060 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003289 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062147 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.232172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.140639 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004021 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004554 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.041020 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.151313 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.164992 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992857 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10723 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49775 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 111 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10351 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 888 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4525 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43209 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.171906 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003952 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.742538 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 68586261 # Number of tag accesses -system.l2c.tags.data_accesses 68586261 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2589224 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2589224 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 191644 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 164185 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 355829 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 48914 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 48173 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 97087 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106304 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 9201 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3860 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 408160 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 537157 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 271610 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10477 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5555 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 408048 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 521656 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 272486 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2448210 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 124551 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 127410 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 251961 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9201 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 408160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 584894 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 271610 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10477 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5555 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 408048 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 580223 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 272486 # number of demand (read+write) hits -system.l2c.demand_hits::total 2554514 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9201 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3860 # number of overall hits -system.l2c.overall_hits::cpu0.inst 408160 # number of overall hits -system.l2c.overall_hits::cpu0.data 584894 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 271610 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10477 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5555 # number of overall hits -system.l2c.overall_hits::cpu1.inst 408048 # number of overall hits -system.l2c.overall_hits::cpu1.data 580223 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 272486 # number of overall hits -system.l2c.overall_hits::total 2554514 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 24439 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 23204 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 47643 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 628 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 554 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1182 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 75730 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50449 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 126179 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1681 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1744 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 48585 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 141383 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 241091 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1909 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1973 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 44680 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 100605 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 753125 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 440725 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 106525 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 547250 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1681 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1744 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 48585 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 217113 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1909 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1973 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 44680 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 151054 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 169474 # number of demand (read+write) misses -system.l2c.demand_misses::total 879304 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1681 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1744 # number of overall misses -system.l2c.overall_misses::cpu0.inst 48585 # number of overall misses -system.l2c.overall_misses::cpu0.data 217113 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 241091 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1909 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1973 # number of overall misses -system.l2c.overall_misses::cpu1.inst 44680 # number of overall misses -system.l2c.overall_misses::cpu1.data 151054 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 169474 # number of overall misses -system.l2c.overall_misses::total 879304 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 162640000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 138377500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 301017500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7502500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7047000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 14549500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8218459999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5520286999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 13738746998 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 167721500 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.257236 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20290.096507 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20772.348289 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20539.297770 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.802198 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24934.650456 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24739.158163 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98112.806773 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99551.595478 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 98686.147671 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100195.391419 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105988.701702 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114504.852155 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19702.254384 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19071.003628 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19604.820773 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3576184 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2127782 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81817 # Transaction distribution -system.membus.trans_dist::ReadResp 843472 # Transaction distribution -system.membus.trans_dist::WriteReq 38449 # Transaction distribution -system.membus.trans_dist::WriteResp 38449 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1169254 # Transaction distribution -system.membus.trans_dist::CleanEvict 223620 # Transaction distribution -system.membus.trans_dist::UpgradeReq 320332 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 305580 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 143723 # Transaction distribution -system.membus.trans_dist::ReadExResp 125482 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 761655 # Transaction distribution -system.membus.trans_dist::InvalidateReq 651499 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 81785 # Transaction distribution +system.membus.trans_dist::ReadResp 843578 # Transaction distribution +system.membus.trans_dist::WriteReq 38414 # Transaction distribution +system.membus.trans_dist::WriteResp 38414 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution +system.membus.trans_dist::CleanEvict 225685 # Transaction distribution +system.membus.trans_dist::UpgradeReq 305919 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 142258 # Transaction distribution +system.membus.trans_dist::ReadExResp 125306 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution +system.membus.trans_dist::InvalidateReq 628104 # Transaction distribution +system.membus.trans_dist::InvalidateResp 29933 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4313500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4462434 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238025 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238025 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4700459 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124357036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124565390 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7261504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131826894 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 595046 # Total snoops (count) -system.membus.snoopTraffic 184128 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2303059 # Request fanout histogram -system.membus.snoop_fanout::mean 0.014256 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.118544 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 601899 # Total snoops (count) +system.membus.snoopTraffic 182272 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2241138 # Request fanout histogram +system.membus.snoop_fanout::mean 0.014818 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2270227 98.57% 98.57% # Request fanout histogram -system.membus.snoop_fanout::1 32832 1.43% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram +system.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2303059 # Request fanout histogram -system.membus.reqLayer0.occupancy 101257500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2241138 # Request fanout histogram +system.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21679000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8033203938 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4846349578 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45469982 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3317,78 +3291,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10759482 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5851735 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1766751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 181547 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 166860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14687 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81819 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4062742 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38449 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38449 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3651776 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2342209 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 672985 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 402667 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1075652 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 288170 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 288170 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3981632 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 828938 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 799211 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8607895 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7128520 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15736415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 211923339 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 174059331 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 385982670 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2818319 # Total snoops (count) -system.toL2Bus.snoopTraffic 121467536 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7671705 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.367658 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486122 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2851175 # Total snoops (count) +system.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4865825 63.43% 63.43% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2791193 36.38% 99.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14687 0.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7671705 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8456586164 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2556167 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3921212144 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3534160915 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |