diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt | 2262 |
1 files changed, 1144 insertions, 1118 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 7790849b2..61b2291b6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.824462 # Number of seconds simulated -sim_ticks 51824462100500 # Number of ticks simulated -final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.832459 # Number of seconds simulated +sim_ticks 51832458543500 # Number of ticks simulated +final_tick 51832458543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 684695 # Simulator instruction rate (inst/s) -host_op_rate 804548 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39714246392 # Simulator tick rate (ticks/s) -host_mem_usage 713112 # Number of bytes of host memory used -host_seconds 1304.93 # Real time elapsed on the host -sim_insts 893481288 # Number of instructions simulated -sim_ops 1049881338 # Number of ops (including micro ops) simulated +host_inst_rate 757890 # Simulator instruction rate (inst/s) +host_op_rate 890582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44493723118 # Simulator tick rate (ticks/s) +host_mem_usage 717728 # Number of bytes of host memory used +host_seconds 1164.94 # Real time elapsed on the host +sim_insts 882895003 # Number of instructions simulated +sim_ops 1037473525 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory -system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 255168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 250176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5270964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 81048392 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 390144 # Number of bytes read from this memory +system.physmem.bytes_read::total 87214844 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5270964 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5270964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75813760 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory -system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75834340 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122766 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1266394 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6096 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1403152 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1184590 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1187163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1563661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1682630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1462670 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 923811 # Number of read requests accepted -system.physmem.writeReqs 1833124 # Number of write requests accepted -system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue -system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57129 # Per bank write bursts -system.physmem.perBankRdBursts::1 60965 # Per bank write bursts -system.physmem.perBankRdBursts::2 52485 # Per bank write bursts -system.physmem.perBankRdBursts::3 50413 # Per bank write bursts -system.physmem.perBankRdBursts::4 54002 # Per bank write bursts -system.physmem.perBankRdBursts::5 59718 # Per bank write bursts -system.physmem.perBankRdBursts::6 51713 # Per bank write bursts -system.physmem.perBankRdBursts::7 51669 # Per bank write bursts -system.physmem.perBankRdBursts::8 50247 # Per bank write bursts -system.physmem.perBankRdBursts::9 101235 # Per bank write bursts -system.physmem.perBankRdBursts::10 59848 # Per bank write bursts -system.physmem.perBankRdBursts::11 58323 # Per bank write bursts -system.physmem.perBankRdBursts::12 55369 # Per bank write bursts -system.physmem.perBankRdBursts::13 55988 # Per bank write bursts -system.physmem.perBankRdBursts::14 51743 # Per bank write bursts -system.physmem.perBankRdBursts::15 52477 # Per bank write bursts -system.physmem.perBankWrBursts::0 110630 # Per bank write bursts -system.physmem.perBankWrBursts::1 112240 # Per bank write bursts -system.physmem.perBankWrBursts::2 108805 # Per bank write bursts -system.physmem.perBankWrBursts::3 108103 # Per bank write bursts -system.physmem.perBankWrBursts::4 111102 # Per bank write bursts -system.physmem.perBankWrBursts::5 113339 # Per bank write bursts -system.physmem.perBankWrBursts::6 105567 # Per bank write bursts -system.physmem.perBankWrBursts::7 107723 # Per bank write bursts -system.physmem.perBankWrBursts::8 108849 # Per bank write bursts -system.physmem.perBankWrBursts::9 115780 # Per bank write bursts -system.physmem.perBankWrBursts::10 115663 # Per bank write bursts -system.physmem.perBankWrBursts::11 113049 # Per bank write bursts -system.physmem.perBankWrBursts::12 112494 # Per bank write bursts -system.physmem.perBankWrBursts::13 116984 # Per bank write bursts -system.physmem.perBankWrBursts::14 111502 # Per bank write bursts -system.physmem.perBankWrBursts::15 110389 # Per bank write bursts +system.physmem.bw_write::total 1463067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1462670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1564058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3145697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1403152 # Number of read requests accepted +system.physmem.writeReqs 1187163 # Number of write requests accepted +system.physmem.readBursts 1403152 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1187163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 89743360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 58368 # Total number of bytes read from write queue +system.physmem.bytesWritten 75832768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 87214844 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 75834340 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 912 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 142509 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 84707 # Per bank write bursts +system.physmem.perBankRdBursts::1 87220 # Per bank write bursts +system.physmem.perBankRdBursts::2 81347 # Per bank write bursts +system.physmem.perBankRdBursts::3 82774 # Per bank write bursts +system.physmem.perBankRdBursts::4 86841 # Per bank write bursts +system.physmem.perBankRdBursts::5 98270 # Per bank write bursts +system.physmem.perBankRdBursts::6 81495 # Per bank write bursts +system.physmem.perBankRdBursts::7 83122 # Per bank write bursts +system.physmem.perBankRdBursts::8 79285 # Per bank write bursts +system.physmem.perBankRdBursts::9 129613 # Per bank write bursts +system.physmem.perBankRdBursts::10 85444 # Per bank write bursts +system.physmem.perBankRdBursts::11 88159 # Per bank write bursts +system.physmem.perBankRdBursts::12 83519 # Per bank write bursts +system.physmem.perBankRdBursts::13 84779 # Per bank write bursts +system.physmem.perBankRdBursts::14 82284 # Per bank write bursts +system.physmem.perBankRdBursts::15 83381 # Per bank write bursts +system.physmem.perBankWrBursts::0 72521 # Per bank write bursts +system.physmem.perBankWrBursts::1 74576 # Per bank write bursts +system.physmem.perBankWrBursts::2 72526 # Per bank write bursts +system.physmem.perBankWrBursts::3 74694 # Per bank write bursts +system.physmem.perBankWrBursts::4 74615 # Per bank write bursts +system.physmem.perBankWrBursts::5 83452 # Per bank write bursts +system.physmem.perBankWrBursts::6 71356 # Per bank write bursts +system.physmem.perBankWrBursts::7 73404 # Per bank write bursts +system.physmem.perBankWrBursts::8 69434 # Per bank write bursts +system.physmem.perBankWrBursts::9 76014 # Per bank write bursts +system.physmem.perBankWrBursts::10 73389 # Per bank write bursts +system.physmem.perBankWrBursts::11 75855 # Per bank write bursts +system.physmem.perBankWrBursts::12 72723 # Per bank write bursts +system.physmem.perBankWrBursts::13 74909 # Per bank write bursts +system.physmem.perBankWrBursts::14 71861 # Per bank write bursts +system.physmem.perBankWrBursts::15 73558 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 145 # Number of times write queue was full causing retry -system.physmem.totGap 51824459475500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 51832455911500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 880695 # Read request sizes (log2) +system.physmem.readPktSize::6 1360036 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1830551 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1184590 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1369724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 26989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,165 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 93369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 92986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 93402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 96397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads -system.physmem.totQLat 12043609520 # Total ticks spent queuing -system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 15525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 68862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 70049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 70008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 69966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 69777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 75585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 71661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 71703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 72226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 69733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 68867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 564142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 293.500232 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.709934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.462784 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 227896 40.40% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 137874 24.44% 64.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50148 8.89% 73.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27962 4.96% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20021 3.55% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14110 2.50% 84.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11549 2.05% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10920 1.94% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63662 11.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 564142 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 68197 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.561359 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 299.455370 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 68195 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 68197 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 68197 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.374474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.924162 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.358180 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 65696 96.33% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 133 0.20% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 441 0.65% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 195 0.29% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 359 0.53% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 498 0.73% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 123 0.18% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 30 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 34 0.05% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 28 0.04% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 38 0.06% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 22 0.03% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 434 0.64% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 35 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 41 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 68197 # Writes before turning the bus around for reads +system.physmem.totQLat 16916842552 # Total ticks spent queuing +system.physmem.totMemAccLat 43208842552 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7011200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12064.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30814.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing -system.physmem.readRowHits 694872 # Number of row buffer hits during reads -system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes -system.physmem.avgGap 18797853.22 # Average gap between requests -system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.655841 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states +system.physmem.avgWrQLen 22.64 # Average write queue length when enqueuing +system.physmem.readRowHits 1132918 # Number of row buffer hits during reads +system.physmem.writeRowHits 890066 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes +system.physmem.avgGap 20010097.58 # Average gap between requests +system.physmem.pageHitRate 78.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2149066080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1172605500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5349013800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3869493120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3385443743760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308122393760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29951995045500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34658101361520 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.656420 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49827055945457 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730799460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states +system.physmem_0.memoryStateTime::ACT 274602731543 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.672178 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states +system.physmem_1.actEnergy 2115847440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1154480250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5588419200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3808574640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3385443743760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1306419956235 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29953488411750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34658019433275 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.654839 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49829529145116 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730799460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states +system.physmem_1.memoryStateTime::ACT 272122791134 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -371,68 +368,76 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 211321 # Table walker walks requested -system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 207675 # Table walker walks requested +system.cpu.dtb.walker.walksLong 207675 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15981 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 160171 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 207653 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.182998 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 62.840123 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 207651 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 207653 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 176174 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24712.505818 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21157.403643 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15094.851220 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 111064 63.04% 63.04% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 63199 35.87% 98.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 999 0.57% 99.48% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 662 0.38% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 15 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 88 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 50 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 52 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 13 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 176174 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -781821628 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.029012 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.167839 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -759139796 97.10% 97.10% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -22681832 2.90% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -781821628 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 160172 90.93% 90.93% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15981 9.07% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 176153 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 207675 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 207675 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 176153 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 176153 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 383828 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 167775531 # DTB read hits -system.cpu.dtb.read_misses 155743 # DTB read misses -system.cpu.dtb.write_hits 152648275 # DTB write hits -system.cpu.dtb.write_misses 55578 # DTB write misses +system.cpu.dtb.read_hits 165829611 # DTB read hits +system.cpu.dtb.read_misses 153241 # DTB read misses +system.cpu.dtb.write_hits 150793131 # DTB write hits +system.cpu.dtb.write_misses 54434 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 42000 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1055 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75015 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8164 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 167931274 # DTB read accesses -system.cpu.dtb.write_accesses 152703853 # DTB write accesses +system.cpu.dtb.perms_faults 19719 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 165982852 # DTB read accesses +system.cpu.dtb.write_accesses 150847565 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320423806 # DTB hits -system.cpu.dtb.misses 211321 # DTB misses -system.cpu.dtb.accesses 320635127 # DTB accesses +system.cpu.dtb.hits 316622742 # DTB hits +system.cpu.dtb.misses 207675 # DTB misses +system.cpu.dtb.accesses 316830417 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -462,97 +467,91 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 122916 # Table walker walks requested -system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated +system.cpu.itb.walker.walks 122431 # Table walker walks requested +system.cpu.itb.walker.walksLong 122431 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1128 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 110257 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 122431 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 122431 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 122431 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 111385 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28118.386677 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24591.122191 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17995.361080 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109197 98.04% 98.04% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1895 1.70% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 129 0.12% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 78 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 51 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 111385 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -887504296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -887504296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -887504296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 110257 98.99% 98.99% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1128 1.01% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 111385 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122431 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 122431 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 894030670 # ITB inst hits -system.cpu.itb.inst_misses 122916 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111385 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 111385 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 233816 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 883439249 # ITB inst hits +system.cpu.itb.inst_misses 122431 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 42000 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1055 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53485 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 894153586 # ITB inst accesses -system.cpu.itb.hits 894030670 # DTB hits -system.cpu.itb.misses 122916 # DTB misses -system.cpu.itb.accesses 894153586 # DTB accesses -system.cpu.numCycles 103648924201 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 883561680 # ITB inst accesses +system.cpu.itb.hits 883439249 # DTB hits +system.cpu.itb.misses 122431 # DTB misses +system.cpu.itb.accesses 883561680 # DTB accesses +system.cpu.numCycles 103664917087 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 893481288 # Number of instructions committed -system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses -system.cpu.num_func_calls 52999943 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls -system.cpu.num_int_insts 963989017 # number of integer instructions -system.cpu.num_fp_insts 895873 # number of float instructions -system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read -system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read -system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written -system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read -system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written -system.cpu.num_mem_refs 320407593 # number of memory refs -system.cpu.num_load_insts 167768846 # Number of load instructions -system.cpu.num_store_insts 152638747 # Number of store instructions -system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles -system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969376 # Percentage of idle cycles -system.cpu.Branches 199584978 # Number of branches fetched +system.cpu.committedInsts 882895003 # Number of instructions committed +system.cpu.committedOps 1037473525 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 952709754 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 896425 # Number of float alu accesses +system.cpu.num_func_calls 52419949 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 134729686 # number of instructions that are conditional controls +system.cpu.num_int_insts 952709754 # number of integer instructions +system.cpu.num_fp_insts 896425 # number of float instructions +system.cpu.num_int_register_reads 1388360502 # number of times the integer registers were read +system.cpu.num_int_register_writes 755717952 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1444442 # number of times the floating registers were read +system.cpu.num_fp_register_writes 761348 # number of times the floating registers were written +system.cpu.num_cc_register_reads 231664947 # number of times the CC registers were read +system.cpu.num_cc_register_writes 231068644 # number of times the CC registers were written +system.cpu.num_mem_refs 316605789 # number of memory refs +system.cpu.num_load_insts 165822487 # Number of load instructions +system.cpu.num_store_insts 150783302 # Number of store instructions +system.cpu.num_idle_cycles 100487560505.254059 # Number of idle cycles +system.cpu.num_busy_cycles 3177356581.745939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030650 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969350 # Percentage of idle cycles +system.cpu.Branches 197184546 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 719043510 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2202813 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 97927 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -575,126 +574,126 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Cl system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110813 0.01% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 165822487 15.97% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 150783302 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1050473844 # Class of executed instruction +system.cpu.op_class::total 1038060895 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10213653 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16280 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 10067650 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 306351638 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10068162 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.427762 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3466781500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.966034 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999934 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999934 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits -system.cpu.dcache.overall_hits::total 301988446 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses -system.cpu.dcache.overall_misses::total 8832117 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency +system.cpu.dcache.tags.tag_accesses 1276220350 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276220350 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 154968992 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 154968992 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 143085243 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 143085243 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 390390 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 390390 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 335374 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 335374 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3613361 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3613361 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3913213 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3913213 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 298054235 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 298054235 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 298444625 # number of overall hits +system.cpu.dcache.overall_hits::total 298444625 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5249224 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5249224 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2178798 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2178798 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1272425 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1272425 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1229487 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1229487 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 301533 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 301533 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 7428022 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7428022 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8700447 # number of overall misses +system.cpu.dcache.overall_misses::total 8700447 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82824595500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82824595500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63552242000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63552242000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 50841662000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 50841662000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4423231500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4423231500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 146376837500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 146376837500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 146376837500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 146376837500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 160218216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 160218216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 145264041 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 145264041 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1662815 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1662815 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1564861 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1564861 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3914894 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3914894 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3913214 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3913214 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 305482257 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 305482257 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 307145072 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 307145072 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032763 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032763 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014999 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014999 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.765223 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.765223 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785684 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.785684 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077022 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077022 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024316 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028327 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028327 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15778.445633 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15778.445633 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29168.487395 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29168.487395 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 41351.931334 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 41351.931334 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14669.145666 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14669.145666 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19706.031767 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19706.031767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16824.059442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16824.059442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -703,154 +702,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks -system.cpu.dcache.writebacks::total 7878976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70685 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70685 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 37134 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 37134 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 37134 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 37134 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5299807 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5299807 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2197927 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2197927 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1295520 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1295520 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232796 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232796 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7760504 # number of writebacks +system.cpu.dcache.writebacks::total 7760504 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23609 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 23609 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21261 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21261 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 71576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 71576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44870 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5225615 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5225615 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2157537 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2157537 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1270654 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1270654 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1229487 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1229487 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 229957 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 229957 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7383152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7383152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8653806 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8653806 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 77028808000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 77028808000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60744856000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 60744856000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20507265000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20507265000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 49612175000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 49612175000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3074046500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3074046500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137773664000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137773664000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 158280929000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 158280929000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831352000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831352000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5695270000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5695270000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11526622000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11526622000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032616 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014853 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014853 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.764158 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.764158 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785684 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785684 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058739 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058739 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024169 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024169 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028175 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028175 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14740.620578 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14740.620578 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28154.722723 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28154.722723 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16139.141733 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16139.141733 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 40351.931334 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 40351.931334 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13367.918785 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13367.918785 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18660.548232 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18660.548232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18290.325552 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18290.325552 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173006.349018 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173006.349018 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168948.976565 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168948.976565 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170977.542423 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170977.542423 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13753173 # number of replacements -system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999766 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13898073 # number of replacements +system.cpu.icache.tags.tagsinuse 511.854844 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 869540659 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13898585 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62.563251 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 43284980500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.854844 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999716 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999716 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 907784360 # Number of tag accesses -system.cpu.icache.tags.data_accesses 907784360 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 880276980 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 880276980 # number of overall hits -system.cpu.icache.overall_hits::total 880276980 # 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average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74879.026087 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74879.026087 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1292250 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 308.197317 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.230467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.230467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005733 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040612 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040612 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.412824 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.412824 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010860 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015359 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.085988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.036286 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010860 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015359 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.085988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.036286 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76447.885005 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20655.136744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20655.136744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70629.323660 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70629.323660 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71724.710711 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71724.710711 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73325.601104 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73325.601104 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69177.973331 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69177.973331 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71724.710711 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71598.411226 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71655.460633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71724.710711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71598.411226 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71655.460633 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62379.026087 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160506.349018 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105427.789564 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157448.976565 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157448.976565 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62379.026087 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158977.572090 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 121291.896220 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1048560 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21674258 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 470306 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33102923 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.033230 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179236 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 8945109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 16396444 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45067 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45068 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2112473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2112473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13898590 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6735107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1336151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1229487 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41779933 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30429687 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 620392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 972976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 73802988 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 889682260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1062595910 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2036024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2937088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1957251282 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1844105 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 50552964 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.048758 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.215362 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32002916 96.68% 96.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1100007 3.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 48088105 95.12% 95.12% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2464859 4.88% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33102923 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 50552964 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32307276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1324500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20891010000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13945928913 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 365889000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 605840000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40333 # Transaction distribution -system.iobus.trans_dist::ReadResp 40333 # Transaction distribution +system.iobus.trans_dist::ReadReq 40329 # Transaction distribution +system.iobus.trans_dist::ReadResp 40329 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 29907 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1260,11 +1284,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231016 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231016 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353800 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1281,11 +1305,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334496 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334496 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492416 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1314,211 +1338,213 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 568778648 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115493 # number of replacements -system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use +system.iocache.tags.replacements 115490 # number of replacements +system.iocache.tags.tagsinuse 10.455215 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13165278431000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510021 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.945193 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219376 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434075 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653451 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039965 # Number of tag accesses -system.iocache.tags.data_accesses 1039965 # Number of data accesses +system.iocache.tags.tag_accesses 1039929 # Number of tag accesses +system.iocache.tags.data_accesses 1039929 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8881 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses -system.iocache.demand_misses::total 8888 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8844 # number of demand (read+write) misses +system.iocache.demand_misses::total 8884 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8848 # number of overall misses -system.iocache.overall_misses::total 8888 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8844 # number of overall misses +system.iocache.overall_misses::total 8884 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1566099238 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1571168238 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12612607410 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12612607410 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1566099238 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1571519238 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1566099238 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1571519238 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8881 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8844 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8884 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8844 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8884 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 177080.420398 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 176913.437451 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118246.150623 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118246.150623 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 177080.420398 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 176893.205538 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 177080.420398 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 176893.205538 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29516 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3281 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.996038 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8881 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8844 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8884 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8844 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8884 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1123899238 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1127118238 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279407410 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7279407410 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1123899238 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1127319238 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1123899238 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1127319238 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127080.420398 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 126913.437451 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68246.150623 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68246.150623 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 127080.420398 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 126893.205538 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 127080.420398 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 126893.205538 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 448489 # Transaction distribution -system.membus.trans_dist::ReadResp 448489 # Transaction distribution +system.membus.trans_dist::ReadReq 76831 # Transaction distribution +system.membus.trans_dist::ReadResp 446450 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::Writeback 1214153 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution -system.membus.trans_dist::ReadExReq 512353 # Transaction distribution -system.membus.trans_dist::ReadExResp 512353 # Transaction distribution +system.membus.trans_dist::Writeback 1184590 # Transaction distribution +system.membus.trans_dist::CleanEvict 190005 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35851 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35852 # Transaction distribution +system.membus.trans_dist::ReadExReq 993855 # Transaction distribution +system.membus.trans_dist::ReadExResp 993855 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 369619 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4133679 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4263383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 340829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4604212 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3324 # Total snoops (count) -system.membus.snoop_fanout::samples 2861471 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155834656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 156004506 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7214528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7214528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 163219034 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3445 # Total snoops (count) +system.membus.snoop_fanout::samples 2994110 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2861471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2994110 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2861471 # Request fanout histogram -system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2994110 # Request fanout histogram +system.membus.reqLayer0.occupancy 107330000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5385500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7724756059 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7445249237 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228975298 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted |