diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing')
4 files changed, 1396 insertions, 1355 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini index ebadfb41e..d16508053 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -153,7 +153,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -250,7 +250,7 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -310,7 +310,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -382,7 +382,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -499,7 +499,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -544,7 +544,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -556,7 +556,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -588,29 +588,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -630,6 +637,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -639,7 +647,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -661,9 +669,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1016,7 +1024,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1329,10 +1337,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1340,7 +1349,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -1571,6 +1580,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1578,7 +1588,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout index ad2b5e63e..b93a4d4b7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:07:38 -gem5 executing on e108600-lin, pid 24412 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:50:54 +gem5 executing on e108600-lin, pid 17458 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51759347706500 because m5_exit instruction encountered +Exiting @ tick 51821888787500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index db63d86a7..39817260d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.820895 # Number of seconds simulated -sim_ticks 51820894502500 # Number of ticks simulated -final_tick 51820894502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821889 # Number of seconds simulated +sim_ticks 51821888787500 # Number of ticks simulated +final_tick 51821888787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 612269 # Simulator instruction rate (inst/s) -host_op_rate 719485 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35448799247 # Simulator tick rate (ticks/s) -host_mem_usage 680056 # Number of bytes of host memory used -host_seconds 1461.85 # Real time elapsed on the host -sim_insts 895045967 # Number of instructions simulated -sim_ops 1051780871 # Number of ops (including micro ops) simulated +host_inst_rate 515124 # Simulator instruction rate (inst/s) +host_op_rate 605315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31054928912 # Simulator tick rate (ticks/s) +host_mem_usage 676612 # Number of bytes of host memory used +host_seconds 1668.72 # Real time elapsed on the host +sim_insts 859596485 # Number of instructions simulated +sim_ops 1010098639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 268032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 256704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5200500 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 51306824 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 409600 # Number of bytes read from this memory -system.physmem.bytes_read::total 57441660 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5200500 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5200500 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78712256 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 216448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 219200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5035380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 42867656 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 394432 # Number of bytes read from this memory +system.physmem.bytes_read::total 48733116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5035380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5035380 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69868992 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 78732836 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4011 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 121665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 801682 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6400 # Number of read requests responded to by this memory -system.physmem.num_reads::total 937946 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1229879 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69889572 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3382 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3425 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 119085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 669820 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 801875 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1091703 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1232452 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 100355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 990080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1108465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 100355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1518929 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1094276 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 97167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 827211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 940396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 97167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 97167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1348253 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1519326 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1518929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 100355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 990477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2627791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 937946 # Number of read requests accepted -system.physmem.writeReqs 1232452 # Number of write requests accepted -system.physmem.readBursts 937946 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1232452 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59993856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 34688 # Total number of bytes read from write queue -system.physmem.bytesWritten 78731584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 57441660 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78732836 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 542 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1348650 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1348253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 97167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 827609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2289046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 801875 # Number of read requests accepted +system.physmem.writeReqs 1094276 # Number of write requests accepted +system.physmem.readBursts 801875 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1094276 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 51277952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 42048 # Total number of bytes read from write queue +system.physmem.bytesWritten 69886912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 48733116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 69889572 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 657 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2265 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 58989 # Per bank write bursts -system.physmem.perBankRdBursts::1 58919 # Per bank write bursts -system.physmem.perBankRdBursts::2 58679 # Per bank write bursts -system.physmem.perBankRdBursts::3 55735 # Per bank write bursts -system.physmem.perBankRdBursts::4 54249 # Per bank write bursts -system.physmem.perBankRdBursts::5 59544 # Per bank write bursts -system.physmem.perBankRdBursts::6 52586 # Per bank write bursts -system.physmem.perBankRdBursts::7 53926 # Per bank write bursts -system.physmem.perBankRdBursts::8 52975 # Per bank write bursts -system.physmem.perBankRdBursts::9 101116 # Per bank write bursts -system.physmem.perBankRdBursts::10 56481 # Per bank write bursts -system.physmem.perBankRdBursts::11 59298 # Per bank write bursts -system.physmem.perBankRdBursts::12 53072 # Per bank write bursts -system.physmem.perBankRdBursts::13 58564 # Per bank write bursts -system.physmem.perBankRdBursts::14 50527 # Per bank write bursts -system.physmem.perBankRdBursts::15 52744 # Per bank write bursts -system.physmem.perBankWrBursts::0 76908 # Per bank write bursts -system.physmem.perBankWrBursts::1 78477 # Per bank write bursts -system.physmem.perBankWrBursts::2 80133 # Per bank write bursts -system.physmem.perBankWrBursts::3 78953 # Per bank write bursts -system.physmem.perBankWrBursts::4 75778 # Per bank write bursts -system.physmem.perBankWrBursts::5 80212 # Per bank write bursts -system.physmem.perBankWrBursts::6 72590 # Per bank write bursts -system.physmem.perBankWrBursts::7 74527 # Per bank write bursts -system.physmem.perBankWrBursts::8 74121 # Per bank write bursts -system.physmem.perBankWrBursts::9 79665 # Per bank write bursts -system.physmem.perBankWrBursts::10 76241 # Per bank write bursts -system.physmem.perBankWrBursts::11 79585 # Per bank write bursts -system.physmem.perBankWrBursts::12 74881 # Per bank write bursts -system.physmem.perBankWrBursts::13 79432 # Per bank write bursts -system.physmem.perBankWrBursts::14 73606 # Per bank write bursts -system.physmem.perBankWrBursts::15 75072 # Per bank write bursts +system.physmem.perBankRdBursts::0 50164 # Per bank write bursts +system.physmem.perBankRdBursts::1 52640 # Per bank write bursts +system.physmem.perBankRdBursts::2 46199 # Per bank write bursts +system.physmem.perBankRdBursts::3 47700 # Per bank write bursts +system.physmem.perBankRdBursts::4 47678 # Per bank write bursts +system.physmem.perBankRdBursts::5 54947 # Per bank write bursts +system.physmem.perBankRdBursts::6 45482 # Per bank write bursts +system.physmem.perBankRdBursts::7 44174 # Per bank write bursts +system.physmem.perBankRdBursts::8 47146 # Per bank write bursts +system.physmem.perBankRdBursts::9 89983 # Per bank write bursts +system.physmem.perBankRdBursts::10 47048 # Per bank write bursts +system.physmem.perBankRdBursts::11 49101 # Per bank write bursts +system.physmem.perBankRdBursts::12 43837 # Per bank write bursts +system.physmem.perBankRdBursts::13 45399 # Per bank write bursts +system.physmem.perBankRdBursts::14 43891 # Per bank write bursts +system.physmem.perBankRdBursts::15 45829 # Per bank write bursts +system.physmem.perBankWrBursts::0 68109 # Per bank write bursts +system.physmem.perBankWrBursts::1 72083 # Per bank write bursts +system.physmem.perBankWrBursts::2 69263 # Per bank write bursts +system.physmem.perBankWrBursts::3 69948 # Per bank write bursts +system.physmem.perBankWrBursts::4 67942 # Per bank write bursts +system.physmem.perBankWrBursts::5 73995 # Per bank write bursts +system.physmem.perBankWrBursts::6 66206 # Per bank write bursts +system.physmem.perBankWrBursts::7 65273 # Per bank write bursts +system.physmem.perBankWrBursts::8 68509 # Per bank write bursts +system.physmem.perBankWrBursts::9 70672 # Per bank write bursts +system.physmem.perBankWrBursts::10 68078 # Per bank write bursts +system.physmem.perBankWrBursts::11 68626 # Per bank write bursts +system.physmem.perBankWrBursts::12 64922 # Per bank write bursts +system.physmem.perBankWrBursts::13 66812 # Per bank write bursts +system.physmem.perBankWrBursts::14 65438 # Per bank write bursts +system.physmem.perBankWrBursts::15 66107 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 41 # Number of times write queue was full causing retry -system.physmem.totGap 51820891581500 # Total gap between requests +system.physmem.numWrRetry 528 # Number of times write queue was full causing retry +system.physmem.totGap 51821885925500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 894830 # Read request sizes (log2) +system.physmem.readPktSize::6 758759 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1229879 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 903506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1091703 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 767795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,154 +160,185 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 67316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 70490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 74148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 71564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 70236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 72767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 75611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 72543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 77682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 70723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 68261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 67880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 67043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 563432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.214486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.153142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.290760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 250076 44.38% 44.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 147098 26.11% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49891 8.85% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26994 4.79% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18337 3.25% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11939 2.12% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8931 1.59% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7653 1.36% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 42513 7.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 563432 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 66023 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.197810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 125.335088 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 66020 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 64549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 64819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 67440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 65819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 58775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1157 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 494449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.049629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.402723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 288.016754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 219085 44.31% 44.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 131738 26.64% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 43693 8.84% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22796 4.61% 84.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15362 3.11% 87.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9595 1.94% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7428 1.50% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5929 1.20% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 38823 7.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 494449 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 57195 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.008130 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 134.294281 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 57192 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 66023 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 66023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.632613 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.082710 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.894597 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 62853 95.20% 95.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 1132 1.71% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1165 1.76% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 145 0.22% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 61 0.09% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 50 0.08% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 451 0.68% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 71 0.11% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 27 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 4 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 11 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 20 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 9 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 66023 # Writes before turning the bus around for reads -system.physmem.totQLat 12434281516 # Total ticks spent queuing -system.physmem.totMemAccLat 30010606516 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4687020000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13264.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 57195 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 57195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.092281 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.359425 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.356307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 44576 77.94% 77.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9441 16.51% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 730 1.28% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 284 0.50% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 871 1.52% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 293 0.51% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 48 0.08% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.06% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.03% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.03% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.02% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 33 0.06% 98.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 518 0.91% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 69 0.12% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 50 0.09% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 58 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 36 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.01% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 17 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 57195 # Writes before turning the bus around for reads +system.physmem.totQLat 29399013585 # Total ticks spent queuing +system.physmem.totMemAccLat 44421851085 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4006090000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36692.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32014.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 55442.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing -system.physmem.readRowHits 702833 # Number of row buffer hits during reads -system.physmem.writeRowHits 901319 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.27 # Row buffer hit rate for writes -system.physmem.avgGap 23876216.06 # Average gap between requests -system.physmem.pageHitRate 74.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2165373000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1181503125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3530451600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4001905440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384688532160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1300349435715 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29951875881000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34647793082040 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.606693 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49827060150280 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730413360000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 263420580720 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2094172920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1142653875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3781260600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3969667440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384688532160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1299689474040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29952454794750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34647820555785 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.607223 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49827979372630 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730413360000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 262496082370 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing +system.physmem.readRowHits 600273 # Number of row buffer hits during reads +system.physmem.writeRowHits 798478 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.92 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes +system.physmem.avgGap 27330041.71 # Average gap between requests +system.physmem.pageHitRate 73.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1812881700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 963565680 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2777345760 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2885715180 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 48801801360.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 38319920670 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3025839840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 94040362440 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 72590911200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12330316288695 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12595556394525 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.054753 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51729925726993 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5744734750 # Time in different power states +system.physmem_0.memoryStateTime::REF 20754236000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51334657894500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 189038733198 # Time in different power states +system.physmem_0.memoryStateTime::ACT 65464048007 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 206229141045 # Time in different power states +system.physmem_1.actEnergy 1717491300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 912868275 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2943350760 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2814436080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 46544843280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 38176673400 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2758502400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 87988375470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 69794301120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12334956932460 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12588629106345 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.921078 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51730316233255 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5091528742 # Time in different power states +system.physmem_1.memoryStateTime::REF 19793960000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51356223942250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 181755962683 # Time in different power states +system.physmem_1.memoryStateTime::ACT 66066776003 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 192956617822 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -324,9 +355,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -334,7 +365,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -364,69 +395,74 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 214264 # Table walker walks requested -system.cpu.dtb.walker.walksLong 214264 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17030 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 164948 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 214243 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.140028 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 46.737844 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 214241 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 195978 # Table walker walks requested +system.cpu.dtb.walker.walksLong 195978 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13491 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152311 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 195958 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.153094 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 48.869782 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 195956 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 214243 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 181999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24181.814186 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20419.578200 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15522.698406 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 180089 98.95% 98.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1633 0.90% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 118 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 77 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 52 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 181999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 4819875556 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 1.150179 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -723841796 -15.02% -15.02% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 5543717352 115.02% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 4819875556 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 164949 90.64% 90.64% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 17030 9.36% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 181979 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 214264 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 195958 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 165822 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23748.733582 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 19720.854851 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 19654.042010 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 164137 98.98% 98.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1390 0.84% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 75 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 54 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 79 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 53 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 165822 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -2782551036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.846086 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.360866 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -428273296 15.39% 15.39% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -2354277740 84.61% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -2782551036 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 152312 91.86% 91.86% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 13491 8.14% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 165803 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 195978 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 214264 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 181979 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 195978 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 165803 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 181979 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 396243 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 165803 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 361781 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168009449 # DTB read hits -system.cpu.dtb.read_misses 157878 # DTB read misses -system.cpu.dtb.write_hits 152852610 # DTB write hits -system.cpu.dtb.write_misses 56386 # DTB write misses +system.cpu.dtb.read_hits 161602593 # DTB read hits +system.cpu.dtb.read_misses 145506 # DTB read misses +system.cpu.dtb.write_hits 146806893 # DTB write hits +system.cpu.dtb.write_misses 50472 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43022 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 75936 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72949 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 8201 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 7287 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168167327 # DTB read accesses -system.cpu.dtb.write_accesses 152908996 # DTB write accesses +system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 161748099 # DTB read accesses +system.cpu.dtb.write_accesses 146857365 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320862059 # DTB hits -system.cpu.dtb.misses 214264 # DTB misses -system.cpu.dtb.accesses 321076323 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 308409486 # DTB hits +system.cpu.dtb.misses 195978 # DTB misses +system.cpu.dtb.accesses 308605464 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -456,674 +492,671 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 122945 # Table walker walks requested -system.cpu.itb.walker.walksLong 122945 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 120718 # Table walker walks requested +system.cpu.itb.walker.walksLong 120718 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 110624 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 122945 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 122945 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 122945 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 111743 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27331.219853 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23493.082733 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 18310.002732 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 109587 98.07% 98.07% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1865 1.67% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 133 0.12% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 84 0.08% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 22 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 111743 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -850328296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -850328296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -850328296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 110624 99.00% 99.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1119 1.00% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 111743 # Table walker page sizes translated +system.cpu.itb.walker.walksLongTerminationLevel::Level3 108838 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 120718 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 120718 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 120718 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 109957 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27485.576180 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23297.926209 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24382.701456 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 107960 98.18% 98.18% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1664 1.51% 99.70% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 68 0.06% 99.76% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 86 0.08% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 74 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 76 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 109957 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 108838 98.98% 98.98% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 109957 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122945 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 122945 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120718 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 120718 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111743 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 111743 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 234688 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 895597591 # ITB inst hits -system.cpu.itb.inst_misses 122945 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 109957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 230675 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 860126625 # ITB inst hits +system.cpu.itb.inst_misses 120718 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43022 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53957 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 52157 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 895720536 # ITB inst accesses -system.cpu.itb.hits 895597591 # DTB hits -system.cpu.itb.misses 122945 # DTB misses -system.cpu.itb.accesses 895720536 # DTB accesses -system.cpu.numPwrStateTransitions 32698 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16349 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3072754762.549147 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59826711358.002258 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7060 43.18% 43.18% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9253 56.60% 99.78% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 6 0.04% 99.82% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 860247343 # ITB inst accesses +system.cpu.itb.hits 860126625 # DTB hits +system.cpu.itb.misses 120718 # DTB misses +system.cpu.itb.accesses 860247343 # DTB accesses +system.cpu.numPwrStateTransitions 32322 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16161 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3111677574.020791 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60407510991.245888 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 6870 42.51% 42.51% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988775178432 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16349 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1584426889584 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50236467612916 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103641789005 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16161 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1534067513750 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50287821273750 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103643777575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16349 # number of quiesce instructions executed -system.cpu.committedInsts 895045967 # Number of instructions committed -system.cpu.committedOps 1051780871 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 965574423 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 894989 # Number of float alu accesses -system.cpu.num_func_calls 52935800 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 136802593 # number of instructions that are conditional controls -system.cpu.num_int_insts 965574423 # number of integer instructions -system.cpu.num_fp_insts 894989 # number of float instructions -system.cpu.num_int_register_reads 1409614532 # number of times the integer registers were read -system.cpu.num_int_register_writes 766141547 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1442074 # number of times the floating registers were read -system.cpu.num_fp_register_writes 760100 # number of times the floating registers were written -system.cpu.num_cc_register_reads 235678872 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235085086 # number of times the CC registers were written -system.cpu.num_mem_refs 320845878 # number of memory refs -system.cpu.num_load_insts 168002679 # Number of load instructions -system.cpu.num_store_insts 152843199 # Number of store instructions -system.cpu.num_idle_cycles 100472935225.830063 # Number of idle cycles -system.cpu.num_busy_cycles 3168853779.169939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030575 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969425 # Percentage of idle cycles -system.cpu.Branches 199903261 # Number of branches fetched +system.cpu.kern.inst.quiesce 16161 # number of quiesce instructions executed +system.cpu.committedInsts 859596485 # Number of instructions committed +system.cpu.committedOps 1010098639 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 927989339 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 896850 # Number of float alu accesses +system.cpu.num_func_calls 51273640 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 130821573 # number of instructions that are conditional controls +system.cpu.num_int_insts 927989339 # number of integer instructions +system.cpu.num_fp_insts 896850 # number of float instructions +system.cpu.num_int_register_reads 1348541336 # number of times the integer registers were read +system.cpu.num_int_register_writes 735865236 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1446705 # number of times the floating registers were read +system.cpu.num_fp_register_writes 758956 # number of times the floating registers were written +system.cpu.num_cc_register_reads 224361660 # number of times the CC registers were read +system.cpu.num_cc_register_writes 223761478 # number of times the CC registers were written +system.cpu.num_mem_refs 308390268 # number of memory refs +system.cpu.num_load_insts 161593947 # Number of load instructions +system.cpu.num_store_insts 146796321 # Number of store instructions +system.cpu.num_idle_cycles 100575642547.498062 # Number of idle cycles +system.cpu.num_busy_cycles 3068135027.501941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970397 # Percentage of idle cycles +system.cpu.Branches 191892206 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 729096517 69.28% 69.28% # Class of executed instruction -system.cpu.op_class::IntMult 2224980 0.21% 69.49% # Class of executed instruction -system.cpu.op_class::IntDiv 97778 0.01% 69.50% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu.op_class::MemRead 168002679 15.96% 85.48% # Class of executed instruction -system.cpu.op_class::MemWrite 152843199 14.52% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 699904687 69.25% 69.25% # Class of executed instruction +system.cpu.op_class::IntMult 2167959 0.21% 69.47% # Class of executed instruction +system.cpu.op_class::IntDiv 97409 0.01% 69.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 111537 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::MemRead 161593947 15.99% 85.48% # Class of executed instruction +system.cpu.op_class::MemWrite 146796321 14.52% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1052375619 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 10244350 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.965651 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 310416272 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10244862 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.299703 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3504161500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.965651 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy +system.cpu.op_class::total 1010671903 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9712865 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 298498000 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9713377 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.730610 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1293353364 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1293353364 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 156944978 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 156944978 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145025968 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145025968 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395817 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395817 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335163 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335163 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3689072 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3689072 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3994801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3994801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 302306109 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 302306109 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 302701926 # number of overall hits -system.cpu.dcache.overall_hits::total 302701926 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5326710 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5326710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2212553 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2212553 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1311764 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1311764 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1232866 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1232866 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 307422 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 307422 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8772129 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8772129 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10083893 # number of overall misses -system.cpu.dcache.overall_misses::total 10083893 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84631439000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84631439000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66820707500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66820707500 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 25293878500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 25293878500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4522600000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4522600000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 197000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 197000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 176746025000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 176746025000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 176746025000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 176746025000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162271688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162271688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147238521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147238521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707581 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1707581 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1568029 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1568029 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3996494 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3996494 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3994804 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3994804 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 311078238 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 311078238 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 312785819 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 312785819 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032826 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032826 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015027 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015027 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.768200 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.768200 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786252 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786252 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076923 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1243014374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1243014374 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 151150245 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 151150245 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 139360023 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 139360023 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 383359 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 383359 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 333234 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 333234 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475622 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3475622 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3766718 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3766718 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 290843502 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 290843502 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 291226861 # number of overall hits +system.cpu.dcache.overall_hits::total 291226861 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5063029 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5063029 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2070213 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2070213 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1203887 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1203887 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1226147 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1226147 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 292765 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 292765 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 8359389 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8359389 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9563276 # number of overall misses +system.cpu.dcache.overall_misses::total 9563276 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 86479051000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 86479051000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64029512000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64029512000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24965286000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 24965286000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4461300000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4461300000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 167500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 175473849000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 175473849000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 175473849000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 175473849000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 156213274 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 156213274 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 141430236 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 141430236 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587246 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1587246 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559381 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1559381 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3768387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766720 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3766720 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 299202891 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 299202891 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300790137 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300790137 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032411 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032411 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014638 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014638 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758475 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758475 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786304 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786304 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077690 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077690 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028199 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028199 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032239 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032239 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15888.125879 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15888.125879 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30200.726265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30200.726265 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20516.324159 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20516.324159 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14711.373942 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14711.373942 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 65666.666667 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 65666.666667 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20148.589356 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20148.589356 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17527.558553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17527.558553 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.027939 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.027939 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031794 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031794 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17080.496873 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17080.496873 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30928.948857 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30928.948857 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20360.760985 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20360.760985 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15238.501870 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15238.501870 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20991.229024 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20991.229024 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18348.717427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18348.717427 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7906430 # number of writebacks -system.cpu.dcache.writebacks::total 7906430 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21920 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21920 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21246 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70972 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70972 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 43166 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 43166 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 43166 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 43166 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5304790 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5304790 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2191307 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2191307 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1309953 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1309953 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1232866 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1232866 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 236450 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 236450 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8728963 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8728963 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 10038916 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 10038916 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7498102 # number of writebacks +system.cpu.dcache.writebacks::total 7498102 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21612 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21612 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21289 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21289 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70591 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70591 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 42901 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 42901 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 42901 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 42901 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5041417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5041417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2048924 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2048924 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203533 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1203533 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226147 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1226147 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222174 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 222174 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8316488 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8316488 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9520021 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9520021 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78748278500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 78748278500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63964841000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 63964841000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21083631000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21083631000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 24061012500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 24061012500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3160913500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3160913500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 194000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166774132000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 166774132000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187857763000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187857763000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6233075000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6233075000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6233075000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6233075000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032691 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032691 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014883 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014883 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.767140 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.767140 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786252 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786252 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059164 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80551413000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 80551413000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61232027000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61232027000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21569596000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21569596000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23739139000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23739139000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3061958500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3061958500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165522579000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165522579000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187092175000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187092175000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032273 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014487 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014487 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758252 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758252 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786304 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786304 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058957 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058957 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028060 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028060 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032095 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032095 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14844.749462 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14844.749462 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29190.269095 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29190.269095 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16094.952262 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16094.952262 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19516.324159 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19516.324159 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13368.211038 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13368.211038 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 64666.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19105.835596 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19105.835596 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18712.952972 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18712.952972 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184924.790838 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184924.790838 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92456.909339 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92456.909339 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13792548 # number of replacements -system.cpu.icache.tags.tagsinuse 511.891104 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 881804526 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13793060 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63.931030 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31603903500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.891104 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999787 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031650 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031650 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15977.931006 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15977.931006 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29884.967427 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29884.967427 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17921.898278 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17921.898278 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19360.760985 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19360.760985 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13781.803901 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13781.803901 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.942083 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.942083 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.496040 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.496040 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.352816 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.352816 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.690519 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.690519 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 13489644 # number of replacements +system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 846636464 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13490156 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 62.759576 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 32464202500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 909390656 # Number of tag accesses -system.cpu.icache.tags.data_accesses 909390656 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 881804526 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 881804526 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 881804526 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 881804526 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 881804526 # number of overall hits -system.cpu.icache.overall_hits::total 881804526 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13793065 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13793065 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13793065 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13793065 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13793065 # number of overall misses -system.cpu.icache.overall_misses::total 13793065 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185289814000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185289814000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185289814000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185289814000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185289814000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185289814000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 895597591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 895597591 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 895597591 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 895597591 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 895597591 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 895597591 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015401 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015401 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015401 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015401 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015401 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015401 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13433.548961 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13433.548961 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13433.548961 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13433.548961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13433.548961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13433.548961 # average overall miss latency +system.cpu.icache.tags.tag_accesses 873616786 # Number of tag accesses +system.cpu.icache.tags.data_accesses 873616786 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 846636464 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 846636464 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 846636464 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 846636464 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 846636464 # number of overall hits +system.cpu.icache.overall_hits::total 846636464 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13490161 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13490161 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13490161 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13490161 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13490161 # number of overall misses +system.cpu.icache.overall_misses::total 13490161 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 183617881000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 183617881000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 183617881000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 183617881000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 183617881000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 183617881000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 860126625 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 860126625 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 860126625 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 860126625 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 860126625 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 860126625 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015684 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015684 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015684 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015684 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015684 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015684 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13611.244595 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13611.244595 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13611.244595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13611.244595 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13792548 # number of writebacks -system.cpu.icache.writebacks::total 13792548 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13793065 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13793065 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13793065 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13793065 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13793065 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13793065 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 13489644 # number of writebacks +system.cpu.icache.writebacks::total 13489644 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13490161 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13490161 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13490161 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13490161 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13490161 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13490161 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171496749000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 171496749000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171496749000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 171496749000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171496749000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 171496749000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3263374000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3263374000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3263374000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 3263374000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015401 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015401 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015401 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015401 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12433.548961 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12433.548961 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12433.548961 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12433.548961 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12433.548961 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12433.548961 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75672.440580 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75672.440580 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75672.440580 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75672.440580 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1308215 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65291.954914 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46007809 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1371583 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 33.543584 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6631976500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10023.392915 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 424.218871 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 466.075042 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6280.682260 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48097.585826 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.152945 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006473 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007112 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.733911 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996276 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63097 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 271 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 779 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5781 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56275 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004135 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962784 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 391701839 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 391701839 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 351291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 234298 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 585589 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7906430 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7906430 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13790970 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13790970 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26514 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26514 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1636834 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1636834 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13714488 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 13714488 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6572328 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6572328 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 722608 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 722608 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 351291 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 234298 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 13714488 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8209162 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 22509239 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 351291 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 234298 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 13714488 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8209162 # number of overall hits -system.cpu.l2cache.overall_hits::total 22509239 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4188 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4011 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 8199 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3956 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3956 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 524003 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 524003 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 78577 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 78577 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 278865 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 278865 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 510258 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 510258 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 4188 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 4011 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 78577 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 802868 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 889644 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 4188 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 4011 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 78577 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 802868 # number of overall misses -system.cpu.l2cache.overall_misses::total 889644 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 360029500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 354230500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 714260000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 69357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 189500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 189500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 43047428500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 43047428500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 6529692000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 6529692000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 23627731000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 23627731000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 478000 # number of InvalidateReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::total 478000 # number of InvalidateReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 360029500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 354230500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6529692000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 66675159500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 73919111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 360029500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 354230500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6529692000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 66675159500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 73919111500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 355479 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 238309 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 593788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7906430 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 7906430 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 13790970 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 13790970 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30470 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 30470 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2160837 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2160837 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13793065 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 13793065 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6851193 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 6851193 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1232866 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1232866 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 355479 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 238309 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 13793065 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9012030 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 23398883 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 355479 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 238309 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 13793065 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9012030 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 23398883 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011781 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016831 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013808 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.129833 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.129833 # miss rate for UpgradeReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170127720000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 170127720000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170127720000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 170127720000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170127720000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 170127720000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3557271000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3557271000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3557271000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 3557271000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015684 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015684 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015684 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12611.244595 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12611.244595 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12611.244595 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12611.244595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12611.244595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12611.244595 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1158676 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65394.159072 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 44435371 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1220446 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 36.409125 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 10890.998401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 465.362855 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 539.855564 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.163394 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46827.778856 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.166183 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007101 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008238 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101779 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.714535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997836 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61492 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5790 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54645 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.938293 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 377782006 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 377782006 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 307317 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 227975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 535292 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 7498102 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7498102 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13488047 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13488047 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 24835 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 24835 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1605264 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1605264 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13414164 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 13414164 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6210983 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6210983 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 729246 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 729246 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 307317 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 227975 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 13414164 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7816247 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 21765703 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 307317 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 227975 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 13414164 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7816247 # number of overall hits +system.cpu.l2cache.overall_hits::total 21765703 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3382 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3425 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 6807 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3962 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3962 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 414863 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 414863 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 75997 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 75997 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 256141 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 256141 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 496901 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 496901 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 3382 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3425 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 75997 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 671004 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 753808 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 3382 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3425 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 75997 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 671004 # number of overall misses +system.cpu.l2cache.overall_misses::total 753808 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 458444500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 422573500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 881018000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69853000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 69853000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40877442000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40877442000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8773195000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 8773195000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30189333000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30189333000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 454500 # number of InvalidateReq miss cycles +system.cpu.l2cache.InvalidateReq_miss_latency::total 454500 # number of InvalidateReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 458444500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 422573500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8773195000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 71066775000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 80720988000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 458444500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 422573500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8773195000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 71066775000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 80720988000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 310699 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 231400 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 542099 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7498102 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 7498102 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13488047 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13488047 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28797 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 28797 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2020127 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2020127 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13490161 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 13490161 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6467124 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 6467124 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226147 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1226147 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 310699 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 231400 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 13490161 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8487251 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 22519511 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 310699 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 231400 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 13490161 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8487251 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 22519511 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010885 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.014801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.012557 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.137584 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.137584 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.242500 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.242500 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005697 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005697 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040703 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040703 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.413880 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.413880 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011781 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016831 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005697 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.089088 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.038021 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011781 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016831 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005697 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.089088 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.038021 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85966.929322 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88314.759412 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 87115.501890 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17532.229525 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17532.229525 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 63166.666667 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 63166.666667 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82151.110776 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82151.110776 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83099.278415 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83099.278415 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84728.205404 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84728.205404 # average ReadSharedReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.936781 # average InvalidateReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.936781 # average InvalidateReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85966.929322 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88314.759412 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83099.278415 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83046.228645 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83088.416827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85966.929322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88314.759412 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83099.278415 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83046.228645 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83088.416827 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205365 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.205365 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005634 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005634 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039607 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039607 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.405254 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.405254 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010885 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.014801 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005634 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.079060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.033474 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010885 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.014801 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005634 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.079060 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.033474 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135554.257836 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 123379.124088 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 129428.235640 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17630.742049 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17630.742049 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81250 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98532.387800 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98532.387800 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 115441.333211 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 115441.333211 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117862.165760 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117862.165760 # average ReadSharedReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.914669 # average InvalidateReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.914669 # average InvalidateReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135554.257836 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 123379.124088 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 115441.333211 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105911.104852 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 107084.281409 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135554.257836 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 123379.124088 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 115441.333211 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105911.104852 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 107084.281409 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1123249 # number of writebacks -system.cpu.l2cache.writebacks::total 1123249 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4188 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4011 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 8199 # number of ReadReq MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3956 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3956 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 524003 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 524003 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 78577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 78577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 278865 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 278865 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 510258 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 510258 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4188 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4011 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 78577 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 802868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 889644 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4188 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4011 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 78577 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 802868 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 889644 # number of overall MSHR misses +system.cpu.l2cache.writebacks::writebacks 985073 # number of writebacks +system.cpu.l2cache.writebacks::total 985073 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3382 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3425 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6807 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3962 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3962 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 414863 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 414863 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 75997 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 75997 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256141 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256141 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 496901 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 496901 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3382 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 75997 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 671004 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 753808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3382 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3425 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 75997 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 671004 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 753808 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable @@ -1132,156 +1165,154 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 318149500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314120500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 632270000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75426500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75426500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 159500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 159500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 37807398500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 37807398500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 5743922000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 5743922000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20839044573 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20839044573 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9521744500 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9521744500 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 318149500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314120500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5743922000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58646443073 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 65022635073 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 318149500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314120500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5743922000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58646443073 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 65022635073 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2724311500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810947000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8535258500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2724311500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810947000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8535258500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011781 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013808 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.129833 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.129833 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 424624500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 388323500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 812948000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75436500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75436500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36728812000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36728812000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8013225000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8013225000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27627908030 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27627908030 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9273801000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9273801000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 424624500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 388323500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8013225000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64356720030 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 73182893030 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 424624500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 388323500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8013225000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64356720030 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 73182893030 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3018208500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810725000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8828933500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3018208500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810725000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8828933500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012557 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.137584 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.137584 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.242500 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.242500 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005697 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040703 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040703 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.413880 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.413880 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011781 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.089088 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.038021 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011781 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.089088 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.038021 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77115.501890 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19066.354904 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19066.354904 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53166.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72151.110776 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72151.110776 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73099.278415 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73099.278415 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74728.074778 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74728.074778 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18660.647163 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18660.647163 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73099.278415 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73046.183274 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73088.375882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73099.278415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73046.183274 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73088.375882 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63172.440580 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172400.967187 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111091.336830 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63172.440580 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86195.369052 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 77213.509015 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 48633709 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 24595755 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205365 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205365 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039607 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039607 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405254 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.405254 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.033474 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014801 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005634 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.033474 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 119428.235640 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19040.005048 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19040.005048 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88532.387800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88532.387800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105441.333211 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105441.333211 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107862.107316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107862.107316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18663.276991 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18663.276991 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95911.082542 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97084.261549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125554.257836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 113379.124088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95911.082542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97084.261549 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.380822 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.687184 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.076065 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.215576 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 46934872 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23731321 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2030 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2030 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1965 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1965 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1068832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21713957 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1010835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20969000 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9029679 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13792548 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2522886 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 30473 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 30476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2160837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2160837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13793065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6853863 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1261524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1232866 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41464928 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30930790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 605749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 980040 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 73981507 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1765651732 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1083027398 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1906472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2843832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2853429434 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1738629 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 75129128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 26510522 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.020074 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.140252 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8483175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13489644 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2388366 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 28802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2020127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2020127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13490161 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6470086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1256693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1226147 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40556216 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592159 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 883944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 71365293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726880020 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023309382 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1851200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2485592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2754526194 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1584975 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66236232 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 25469090 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019778 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.139236 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 25978363 97.99% 97.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 532159 2.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24965367 98.02% 98.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 503723 1.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 26510522 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 46319770000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25469090 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 44744307000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1608386 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1625890 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20732722500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20278366500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14200291468 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13408934951 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 367440000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 360759000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 624561000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 573245000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40312 # Transaction distribution -system.iobus.trans_dist::ReadResp 40312 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40346 # Transaction distribution +system.iobus.trans_dist::ReadResp 40346 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1298,11 +1329,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230982 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230982 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353766 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1317,16 +1348,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334360 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492552 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1344,75 +1375,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25722000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25714500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38610500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568931558 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569287162 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147742000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115472 # number of replacements -system.iocache.tags.tagsinuse 10.457340 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115506 # number of replacements +system.iocache.tags.tagsinuse 10.457104 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153794616000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511175 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946165 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219448 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434135 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13154766855000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510739 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946366 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434148 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039776 # Number of tag accesses -system.iocache.tags.data_accesses 1039776 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040082 # Number of tag accesses +system.iocache.tags.data_accesses 1040082 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8827 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8864 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115491 # number of demand (read+write) misses -system.iocache.demand_misses::total 115531 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses +system.iocache.demand_misses::total 115565 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115491 # number of overall misses -system.iocache.overall_misses::total 115531 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1606262152 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1611348152 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115525 # number of overall misses +system.iocache.overall_misses::total 115565 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2019214145 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2024300645 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12771737406 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12771737406 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14377999558 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14383436558 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14377999558 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14383436558 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13409527517 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13409527517 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15428741662 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15434179162 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15428741662 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15434179162 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8827 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8864 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115491 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115531 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115491 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115531 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1426,53 +1457,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 181971.468449 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 181785.666968 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 227876.554001 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 227500.634412 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119738.031632 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119738.031632 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124494.545532 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124498.503068 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124494.545532 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124498.503068 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31144 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.463408 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125717.463408 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 133554.096500 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 133554.096500 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51750 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3368 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3356 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.247031 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.420143 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8827 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8864 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115491 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115531 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115491 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115531 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1164912152 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1168148152 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1576164145 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1579400645 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7431704095 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7431704095 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8596616247 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8600053247 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8596616247 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8600053247 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8069228353 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8069228353 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9645392498 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9648829998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9645392498 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9648829998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1486,95 +1517,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131971.468449 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 131785.666968 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177876.554001 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 177500.634412 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69673.967740 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69673.967740 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74435.378055 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74439.356078 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74435.378055 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74439.356078 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 2941993 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1455813 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3308 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75650.907082 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75650.907082 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 2643885 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1308749 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3600 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 451336 # Transaction distribution +system.membus.trans_dist::ReadResp 424674 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1229879 # Transaction distribution -system.membus.trans_dist::CleanEvict 192681 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4527 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1091703 # Transaction distribution +system.membus.trans_dist::CleanEvict 181416 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 523443 # Transaction distribution -system.membus.trans_dist::ReadExResp 523443 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 374505 # Transaction distribution -system.membus.trans_dist::InvalidateReq 616914 # Transaction distribution +system.membus.trans_dist::ReadExReq 414305 # Transaction distribution +system.membus.trans_dist::ReadExResp 414305 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 347843 # Transaction distribution +system.membus.trans_dist::InvalidateReq 603558 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3690757 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3820461 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4057864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256260 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3623198 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 128940576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 129110426 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7233920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 136344346 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3126 # Total snoops (count) -system.membus.snoopTraffic 199552 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1629933 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019638 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.138754 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111403936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111573786 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 118792538 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3397 # Total snoops (count) +system.membus.snoopTraffic 216896 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1480779 # Request fanout histogram +system.membus.snoop_fanout::mean 0.023089 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.150185 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1597924 98.04% 98.04% # Request fanout histogram -system.membus.snoop_fanout::1 32009 1.96% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1446590 97.69% 97.69% # Request fanout histogram +system.membus.snoop_fanout::1 34189 2.31% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1629933 # Request fanout histogram -system.membus.reqLayer0.occupancy 106906500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1480779 # Request fanout histogram +system.membus.reqLayer0.occupancy 106893000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5804000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5820500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8036011189 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7180364209 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4923968289 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4203282304 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44661763 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44877398 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1617,28 +1648,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal index 0cb0b7645..42937e8d5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000044] Console: colour dummy device 80x25
-[ 0.000048] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000050] pid_max: default: 32768 minimum: 301
-[ 0.000073] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000075] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000316] hw perfevents: no hardware support available
-[ 1.060136] CPU1: failed to come online
-[ 2.080267] CPU2: failed to come online
-[ 3.100398] CPU3: failed to come online
-[ 3.100403] Brought up 1 CPUs
-[ 3.100405] SMP: Total of 1 processors activated.
-[ 3.100517] devtmpfs: initialized
-[ 3.101614] atomic64_test: passed
-[ 3.101697] regulator-dummy: no parameters
-[ 3.102519] NET: Registered protocol family 16
-[ 3.102798] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.102809] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.104232] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.104240] Serial: AMBA PL011 UART driver
-[ 3.104622] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.104693] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.105277] console [ttyAMA0] enabled
-[ 3.105422] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.105471] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.105522] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.105568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130937] 3V3: 3300 mV
-[ 3.131019] vgaarb: loaded
-[ 3.131116] SCSI subsystem initialized
-[ 3.131186] libata version 3.00 loaded.
-[ 3.131272] usbcore: registered new interface driver usbfs
-[ 3.131299] usbcore: registered new interface driver hub
-[ 3.131354] usbcore: registered new device driver usb
-[ 3.131399] pps_core: LinuxPPS API ver. 1 registered
-[ 3.131409] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131433] PTP clock support registered
-[ 3.131670] Switched to clocksource arch_sys_counter
-[ 3.133769] NET: Registered protocol family 2
-[ 3.133932] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.133964] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.134004] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.134042] TCP: reno registered
-[ 3.134050] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134070] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134144] NET: Registered protocol family 1
-[ 3.134216] RPC: Registered named UNIX socket transport module.
-[ 3.134227] RPC: Registered udp transport module.
-[ 3.134236] RPC: Registered tcp transport module.
-[ 3.134245] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.134259] PCI: CLS 0 bytes, default 64
-[ 3.134575] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.134796] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.138336] fuse init (API version 7.23)
-[ 3.138502] msgmni has been set to 469
-[ 3.143073] io scheduler noop registered
-[ 3.143173] io scheduler cfq registered (default)
-[ 3.144095] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.144109] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.144122] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.144136] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.144147] pci_bus 0000:00: scanning bus
-[ 3.144161] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.144177] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.144195] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.144258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.144272] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.144285] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.144297] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.144310] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.144322] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.144336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.144395] pci_bus 0000:00: fixups for bus
-[ 3.144405] pci_bus 0000:00: bus scan returning with max=00
-[ 3.144419] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.144446] pci 0000:00:00.0: fixup irq: got 33
-[ 3.144456] pci 0000:00:00.0: assigning IRQ 33
-[ 3.144470] pci 0000:00:01.0: fixup irq: got 34
-[ 3.144480] pci 0000:00:01.0: assigning IRQ 34
-[ 3.144494] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.144509] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.144524] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.144538] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.144552] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.144565] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.144578] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.144591] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.145478] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.146000] ata_piix 0000:00:01.0: version 2.13
-[ 3.146012] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.146049] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.146644] scsi0 : ata_piix
-[ 3.146827] scsi1 : ata_piix
-[ 3.146881] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.146894] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.147093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.147106] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.147129] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.147142] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301707] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301718] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301753] ata1.00: configured for UDMA/33
-[ 3.301838] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.302037] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.302073] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.302130] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.302141] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.302170] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.302373] sda: sda1
-[ 3.302577] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.422032] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.422047] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.422076] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.422087] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.422118] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.422131] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.422262] usbcore: registered new interface driver usb-storage
-[ 3.422357] mousedev: PS/2 mouse device common for all mice
-[ 3.422646] usbcore: registered new interface driver usbhid
-[ 3.422657] usbhid: USB HID core driver
-[ 3.422710] TCP: cubic registered
-[ 3.422720] NET: Registered protocol family 17
- -[ 3.423384] devtmpfs: mounted
-[ 3.423472] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000040] Console: colour dummy device 80x25
+[ 0.000043] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000046] pid_max: default: 32768 minimum: 301
+[ 0.000066] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000069] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000252] hw perfevents: no hardware support available
+[ 1.060135] CPU1: failed to come online
+[ 2.080266] CPU2: failed to come online
+[ 3.100397] CPU3: failed to come online
+[ 3.100402] Brought up 1 CPUs
+[ 3.100404] SMP: Total of 1 processors activated.
+[ 3.100503] devtmpfs: initialized
+[ 3.101571] atomic64_test: passed
+[ 3.101646] regulator-dummy: no parameters
+[ 3.102401] NET: Registered protocol family 16
+[ 3.102664] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.102675] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.103283] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.103290] Serial: AMBA PL011 UART driver
+[ 3.103646] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.103712] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.104302] console [ttyAMA0] enabled
+[ 3.104405] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.104456] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.104507] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.104554] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.131002] 3V3: 3300 mV
+[ 3.131076] vgaarb: loaded
+[ 3.131168] SCSI subsystem initialized
+[ 3.131239] libata version 3.00 loaded.
+[ 3.131320] usbcore: registered new interface driver usbfs
+[ 3.131346] usbcore: registered new interface driver hub
+[ 3.131401] usbcore: registered new device driver usb
+[ 3.131444] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131455] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131477] PTP clock support registered
+[ 3.131699] Switched to clocksource arch_sys_counter
+[ 3.133732] NET: Registered protocol family 2
+[ 3.133887] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.133915] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.133949] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.133976] TCP: reno registered
+[ 3.133984] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134003] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134067] NET: Registered protocol family 1
+[ 3.134134] RPC: Registered named UNIX socket transport module.
+[ 3.134145] RPC: Registered udp transport module.
+[ 3.134154] RPC: Registered tcp transport module.
+[ 3.134163] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.134177] PCI: CLS 0 bytes, default 64
+[ 3.134494] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.134701] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.138130] fuse init (API version 7.23)
+[ 3.138291] msgmni has been set to 469
+[ 3.142786] io scheduler noop registered
+[ 3.142885] io scheduler cfq registered (default)
+[ 3.143673] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.143688] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.143701] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.143715] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.143727] pci_bus 0000:00: scanning bus
+[ 3.143740] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.143755] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.143773] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.143833] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.143848] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.143860] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.143873] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.143886] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.143899] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.143912] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.143970] pci_bus 0000:00: fixups for bus
+[ 3.143980] pci_bus 0000:00: bus scan returning with max=00
+[ 3.143994] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.144020] pci 0000:00:00.0: fixup irq: got 33
+[ 3.144030] pci 0000:00:00.0: assigning IRQ 33
+[ 3.144044] pci 0000:00:01.0: fixup irq: got 34
+[ 3.144054] pci 0000:00:01.0: assigning IRQ 34
+[ 3.144070] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.144084] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.144099] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.144114] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.144127] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.144141] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.144154] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.144168] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.145036] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.145534] ata_piix 0000:00:01.0: version 2.13
+[ 3.145546] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.145577] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.146149] scsi0 : ata_piix
+[ 3.146327] scsi1 : ata_piix
+[ 3.146380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.146394] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.146583] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.146596] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.146618] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.146632] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301733] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301744] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301779] ata1.00: configured for UDMA/33
+[ 3.301852] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.302048] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.302084] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.302142] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.302153] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.302182] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.302382] sda: sda1
+[ 3.302584] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.422057] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.422072] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.422102] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.422113] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.422144] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.422157] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.422289] usbcore: registered new interface driver usb-storage
+[ 3.422380] mousedev: PS/2 mouse device common for all mice
+[ 3.422670] usbcore: registered new interface driver usbhid
+[ 3.422681] usbhid: USB HID core driver
+[ 3.422731] TCP: cubic registered
+[ 3.422741] NET: Registered protocol family 17
+ +[ 3.423377] devtmpfs: mounted
+[ 3.423427] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.470435] udevd[607]: starting version 182
+[ 3.470296] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.596617] random: dd urandom read with 22 bits of entropy available
+[ 3.606651] random: dd urandom read with 20 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.791906] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.801935] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|