diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing')
4 files changed, 1105 insertions, 1116 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini index ae7f271b3..27116f25e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -415,10 +415,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -445,7 +444,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -572,12 +571,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=true -pci_io_base=788529152 system=system [system.realview.aaci_fake] @@ -670,16 +666,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -695,7 +690,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -858,13 +853,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -874,9 +869,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -918,7 +912,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -999,14 +993,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1023,7 +1016,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -1038,7 +1031,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -1161,17 +1154,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=12 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=788529152 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -1223,7 +1218,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -1238,7 +1233,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout index 481cfe065..9326fddff 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 19:39:30 -gem5 executing on e104799-lin, pid 27757 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 14:13:19 +gem5 executing on e104799-lin, pid 14780 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51811412441500 because m5_exit instruction encountered +Exiting @ tick 51811415265500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 9c2ca116d..b27222f80 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.811412 # Number of seconds simulated -sim_ticks 51811412441500 # Number of ticks simulated -final_tick 51811412441500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.811415 # Number of seconds simulated +sim_ticks 51811415265500 # Number of ticks simulated +final_tick 51811415265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 643802 # Simulator instruction rate (inst/s) -host_op_rate 756584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40241687351 # Simulator tick rate (ticks/s) -host_mem_usage 677920 # Number of bytes of host memory used -host_seconds 1287.51 # Real time elapsed on the host -sim_insts 828899207 # Number of instructions simulated -sim_ops 974107036 # Number of ops (including micro ops) simulated +host_inst_rate 625298 # Simulator instruction rate (inst/s) +host_op_rate 734839 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39084409400 # Simulator tick rate (ticks/s) +host_mem_usage 677180 # Number of bytes of host memory used +host_seconds 1325.63 # Real time elapsed on the host +sim_insts 828913449 # Number of instructions simulated +sim_ops 974124045 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 141632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4651380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65025608 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 401792 # Number of bytes read from this memory -system.physmem.bytes_read::total 70353980 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4651380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4651380 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 61199552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 133696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 141376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4656308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65123848 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 401856 # Number of bytes read from this memory +system.physmem.bytes_read::total 70457084 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4656308 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4656308 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61286080 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 61220132 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2213 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 113085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1016038 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6278 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1139701 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 956243 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 61306660 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 113162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1017573 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6279 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1141312 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 957595 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 958816 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 2734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 89775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1255044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1357886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89775 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89775 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1181198 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 960168 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 2729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 89870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1256940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1359876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1182868 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1181596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1181198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 2734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1255441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2539481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1139701 # Number of read requests accepted -system.physmem.writeReqs 958816 # Number of write requests accepted -system.physmem.readBursts 1139701 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 958816 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72891072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49792 # Total number of bytes read from write queue -system.physmem.bytesWritten 61218752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70353980 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 61220132 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 778 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 295779 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 70381 # Per bank write bursts -system.physmem.perBankRdBursts::1 75813 # Per bank write bursts -system.physmem.perBankRdBursts::2 71139 # Per bank write bursts -system.physmem.perBankRdBursts::3 67493 # Per bank write bursts -system.physmem.perBankRdBursts::4 63564 # Per bank write bursts -system.physmem.perBankRdBursts::5 70698 # Per bank write bursts -system.physmem.perBankRdBursts::6 65929 # Per bank write bursts -system.physmem.perBankRdBursts::7 63583 # Per bank write bursts -system.physmem.perBankRdBursts::8 66194 # Per bank write bursts -system.physmem.perBankRdBursts::9 109788 # Per bank write bursts -system.physmem.perBankRdBursts::10 68376 # Per bank write bursts -system.physmem.perBankRdBursts::11 70520 # Per bank write bursts -system.physmem.perBankRdBursts::12 68080 # Per bank write bursts -system.physmem.perBankRdBursts::13 71994 # Per bank write bursts -system.physmem.perBankRdBursts::14 69489 # Per bank write bursts -system.physmem.perBankRdBursts::15 65882 # Per bank write bursts -system.physmem.perBankWrBursts::0 58404 # Per bank write bursts -system.physmem.perBankWrBursts::1 62356 # Per bank write bursts -system.physmem.perBankWrBursts::2 60883 # Per bank write bursts -system.physmem.perBankWrBursts::3 59981 # Per bank write bursts -system.physmem.perBankWrBursts::4 56389 # Per bank write bursts -system.physmem.perBankWrBursts::5 60703 # Per bank write bursts -system.physmem.perBankWrBursts::6 57931 # Per bank write bursts -system.physmem.perBankWrBursts::7 57426 # Per bank write bursts -system.physmem.perBankWrBursts::8 58562 # Per bank write bursts -system.physmem.perBankWrBursts::9 60878 # Per bank write bursts -system.physmem.perBankWrBursts::10 59750 # Per bank write bursts -system.physmem.perBankWrBursts::11 62184 # Per bank write bursts -system.physmem.perBankWrBursts::12 59419 # Per bank write bursts -system.physmem.perBankWrBursts::13 62742 # Per bank write bursts -system.physmem.perBankWrBursts::14 60987 # Per bank write bursts -system.physmem.perBankWrBursts::15 57948 # Per bank write bursts +system.physmem.bw_write::total 1183265 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1182868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 2729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1257337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2543141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1141312 # Number of read requests accepted +system.physmem.writeReqs 960168 # Number of write requests accepted +system.physmem.readBursts 1141312 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 960168 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72995200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48768 # Total number of bytes read from write queue +system.physmem.bytesWritten 61305216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 70457084 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 61306660 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 762 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 295918 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 70676 # Per bank write bursts +system.physmem.perBankRdBursts::1 76921 # Per bank write bursts +system.physmem.perBankRdBursts::2 71652 # Per bank write bursts +system.physmem.perBankRdBursts::3 67938 # Per bank write bursts +system.physmem.perBankRdBursts::4 64385 # Per bank write bursts +system.physmem.perBankRdBursts::5 70205 # Per bank write bursts +system.physmem.perBankRdBursts::6 66024 # Per bank write bursts +system.physmem.perBankRdBursts::7 63727 # Per bank write bursts +system.physmem.perBankRdBursts::8 65795 # Per bank write bursts +system.physmem.perBankRdBursts::9 109889 # Per bank write bursts +system.physmem.perBankRdBursts::10 68785 # Per bank write bursts +system.physmem.perBankRdBursts::11 70022 # Per bank write bursts +system.physmem.perBankRdBursts::12 67859 # Per bank write bursts +system.physmem.perBankRdBursts::13 71968 # Per bank write bursts +system.physmem.perBankRdBursts::14 68874 # Per bank write bursts +system.physmem.perBankRdBursts::15 65830 # Per bank write bursts +system.physmem.perBankWrBursts::0 58715 # Per bank write bursts +system.physmem.perBankWrBursts::1 63168 # Per bank write bursts +system.physmem.perBankWrBursts::2 61317 # Per bank write bursts +system.physmem.perBankWrBursts::3 60411 # Per bank write bursts +system.physmem.perBankWrBursts::4 56741 # Per bank write bursts +system.physmem.perBankWrBursts::5 60657 # Per bank write bursts +system.physmem.perBankWrBursts::6 57878 # Per bank write bursts +system.physmem.perBankWrBursts::7 57357 # Per bank write bursts +system.physmem.perBankWrBursts::8 58434 # Per bank write bursts +system.physmem.perBankWrBursts::9 60882 # Per bank write bursts +system.physmem.perBankWrBursts::10 59842 # Per bank write bursts +system.physmem.perBankWrBursts::11 61839 # Per bank write bursts +system.physmem.perBankWrBursts::12 59187 # Per bank write bursts +system.physmem.perBankWrBursts::13 62791 # Per bank write bursts +system.physmem.perBankWrBursts::14 60690 # Per bank write bursts +system.physmem.perBankWrBursts::15 57985 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 40 # Number of times write queue was full causing retry -system.physmem.totGap 51811409612500 # Total gap between requests +system.physmem.numWrRetry 35 # Number of times write queue was full causing retry +system.physmem.totGap 51811412436500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1096585 # Read request sizes (log2) +system.physmem.readPktSize::6 1098196 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 956243 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1112094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see +system.physmem.writePktSize::6 957595 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1113641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,104 +159,103 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 54180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 56677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 57597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 58012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 58593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 58964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 58374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 57736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 55832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 55140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 54594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 155 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 450541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.663263 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.634069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.395643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 180604 40.09% 40.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 109821 24.38% 64.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39191 8.70% 73.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22619 5.02% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15643 3.47% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11800 2.62% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10101 2.24% 86.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8767 1.95% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 51995 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 450541 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 53849 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.149826 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 337.005181 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 53847 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 13676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 54291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 56988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 56655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 57800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 58177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 58681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 59112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 63114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 58508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 57267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 57924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 55949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 55254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 54682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 451440 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.492681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.675079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.019607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 180783 40.05% 40.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 110069 24.38% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39371 8.72% 73.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22726 5.03% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15993 3.54% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11772 2.61% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9986 2.21% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8783 1.95% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 51957 11.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 451440 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 53917 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.153458 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.779025 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 53915 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 53849 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 53849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.763431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.132779 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.573717 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51569 95.77% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 271 0.50% 96.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 0.15% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 312 0.58% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 52 0.10% 97.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 350 0.65% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 234 0.43% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.03% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 58 0.11% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 145 0.27% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 23 0.04% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 22 0.04% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 441 0.82% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 31 0.06% 99.55% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 53917 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 53917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.766085 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.131013 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.603955 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51657 95.81% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 251 0.47% 96.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 85 0.16% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 305 0.57% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 61 0.11% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 347 0.64% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 210 0.39% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 16 0.03% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 56 0.10% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 148 0.27% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.05% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 23 0.04% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 456 0.85% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 29 0.05% 99.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 32 0.06% 99.61% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 152 0.28% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.01% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 26 0.05% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads @@ -264,13 +263,13 @@ system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Wr system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 53849 # Writes before turning the bus around for reads -system.physmem.totQLat 14314490470 # Total ticks spent queuing -system.physmem.totMemAccLat 35669296720 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5694615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12568.44 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 53917 # Writes before turning the bus around for reads +system.physmem.totQLat 14358242809 # Total ticks spent queuing +system.physmem.totMemAccLat 35743555309 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5702750000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12588.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31318.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31338.88 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s @@ -280,40 +279,40 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.89 # Average write queue length when enqueuing -system.physmem.readRowHits 918030 # Number of row buffer hits during reads -system.physmem.writeRowHits 726894 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.99 # Row buffer hit rate for writes -system.physmem.avgGap 24689535.33 # Average gap between requests -system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1704243240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 929894625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4279041000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3071993040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384069106080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1294968358125 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29950905933000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34639928569110 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.577285 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49825452803142 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730096680000 # Time in different power states +system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing +system.physmem.readRowHits 919470 # Number of row buffer hits during reads +system.physmem.writeRowHits 727533 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes +system.physmem.avgGap 24654725.45 # Average gap between requests +system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1712392920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 934341375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4301879400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3086061120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384069614640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1295992039365 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29950012638750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34640108967570 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.580666 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49823953491004 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730096940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 255862301858 # Time in different power states +system.physmem_0.memoryStateTime::ACT 257364177996 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1701846720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 928587000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4604519400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3126405600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384069106080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1295387816850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29950537986750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34640356268400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.585540 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49824790858475 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730096680000 # Time in different power states +system.physmem_1.actEnergy 1700493480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 927848625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4594371600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3121092000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384069614640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1294725453480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29951123679000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34640262552825 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.583630 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49825763906946 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730096940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 256517624025 # Time in different power states +system.physmem_1.memoryStateTime::ACT 255552101804 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -367,70 +366,71 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 185269 # Table walker walks requested -system.cpu.dtb.walker.walksLong 185269 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12948 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144056 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 185250 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.215924 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.777306 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 185248 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 185222 # Table walker walks requested +system.cpu.dtb.walker.walksLong 185222 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12899 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144060 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 185205 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.215977 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.785904 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 185203 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 185250 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 157023 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24782.458621 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20866.161950 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18013.175833 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 155872 99.27% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 991 0.63% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 17 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 22 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 157023 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 3934185148 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.600903 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489713 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1570120704 39.91% 39.91% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 2364064444 60.09% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 3934185148 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 144057 91.75% 91.75% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 12948 8.25% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 157005 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185269 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 185205 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 156976 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24757.998038 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20851.674753 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 17681.260030 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 155823 99.27% 99.27% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 3 0.00% 99.27% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1006 0.64% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 72 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 20 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 156976 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 3935879148 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.602257 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489432 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1565466704 39.77% 39.77% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 2370412444 60.23% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 3935879148 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 144061 91.78% 91.78% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 12899 8.22% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 156960 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185222 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185269 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 157005 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156960 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 157005 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 342274 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156960 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 342182 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 156094559 # DTB read hits -system.cpu.dtb.read_misses 137688 # DTB read misses -system.cpu.dtb.write_hits 141675607 # DTB write hits -system.cpu.dtb.write_misses 47581 # DTB write misses +system.cpu.dtb.read_hits 156096920 # DTB read hits +system.cpu.dtb.read_misses 137670 # DTB read misses +system.cpu.dtb.write_hits 141678029 # DTB write hits +system.cpu.dtb.write_misses 47552 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 70732 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 70722 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 6720 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 156232247 # DTB read accesses -system.cpu.dtb.write_accesses 141723188 # DTB write accesses +system.cpu.dtb.read_accesses 156234590 # DTB read accesses +system.cpu.dtb.write_accesses 141725581 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 297770166 # DTB hits -system.cpu.dtb.misses 185269 # DTB misses -system.cpu.dtb.accesses 297955435 # DTB accesses +system.cpu.dtb.hits 297774949 # DTB hits +system.cpu.dtb.misses 185222 # DTB misses +system.cpu.dtb.accesses 297960171 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,43 +460,44 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 118504 # Table walker walks requested -system.cpu.itb.walker.walksLong 118504 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walks 118503 # Table walker walks requested +system.cpu.itb.walker.walksLong 118503 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107076 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 118504 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 118504 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 118504 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 108186 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28679.602721 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24825.752216 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 21031.513378 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 106793 98.71% 98.71% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.00% 98.71% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1215 1.12% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107075 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 118503 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 118503 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 118503 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 108185 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28674.682257 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24804.583165 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21241.542539 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 106795 98.72% 98.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1213 1.12% 99.84% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::196608-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 67 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 29 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 12 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 108186 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 69 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 33 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 108185 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107076 98.97% 98.97% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 107075 98.97% 98.97% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 108186 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 108185 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118504 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 118504 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118503 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 118503 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108186 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 108186 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 226690 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 829409821 # ITB inst hits -system.cpu.itb.inst_misses 118504 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108185 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 108185 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 226688 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 829424054 # ITB inst hits +system.cpu.itb.inst_misses 118503 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -512,41 +513,41 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 829528325 # ITB inst accesses -system.cpu.itb.hits 829409821 # DTB hits -system.cpu.itb.misses 118504 # DTB misses -system.cpu.itb.accesses 829528325 # DTB accesses -system.cpu.numCycles 103622824883 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 829542557 # ITB inst accesses +system.cpu.itb.hits 829424054 # DTB hits +system.cpu.itb.misses 118503 # DTB misses +system.cpu.itb.accesses 829542557 # DTB accesses +system.cpu.numCycles 103622830531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 15973 # number of quiesce instructions executed -system.cpu.committedInsts 828899207 # Number of instructions committed -system.cpu.committedOps 974107036 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 895578515 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 899571 # Number of float alu accesses -system.cpu.num_func_calls 49817464 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 125652530 # number of instructions that are conditional controls -system.cpu.num_int_insts 895578515 # number of integer instructions -system.cpu.num_fp_insts 899571 # number of float instructions -system.cpu.num_int_register_reads 1295563811 # number of times the integer registers were read -system.cpu.num_int_register_writes 709708276 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1453001 # number of times the floating registers were read -system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written -system.cpu.num_cc_register_reads 214507812 # number of times the CC registers were read -system.cpu.num_cc_register_writes 213899539 # number of times the CC registers were written -system.cpu.num_mem_refs 297748170 # number of memory refs -system.cpu.num_load_insts 156084233 # Number of load instructions -system.cpu.num_store_insts 141663937 # Number of store instructions -system.cpu.num_idle_cycles 100539253419.334061 # Number of idle cycles -system.cpu.num_busy_cycles 3083571463.665941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029758 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970242 # Percentage of idle cycles -system.cpu.Branches 184944487 # Number of branches fetched +system.cpu.committedInsts 828913449 # Number of instructions committed +system.cpu.committedOps 974124045 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 895594684 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 899411 # Number of float alu accesses +system.cpu.num_func_calls 49818288 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 125653589 # number of instructions that are conditional controls +system.cpu.num_int_insts 895594684 # number of integer instructions +system.cpu.num_fp_insts 899411 # number of float instructions +system.cpu.num_int_register_reads 1295586183 # number of times the integer registers were read +system.cpu.num_int_register_writes 709722189 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1452745 # number of times the floating registers were read +system.cpu.num_fp_register_writes 757584 # number of times the floating registers were written +system.cpu.num_cc_register_reads 214510161 # number of times the CC registers were read +system.cpu.num_cc_register_writes 213901888 # number of times the CC registers were written +system.cpu.num_mem_refs 297752944 # number of memory refs +system.cpu.num_load_insts 156086585 # Number of load instructions +system.cpu.num_store_insts 141666359 # Number of store instructions +system.cpu.num_idle_cycles 100538909625.142059 # Number of idle cycles +system.cpu.num_busy_cycles 3083920905.857941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029761 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970239 # Percentage of idle cycles +system.cpu.Branches 184946450 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 674583276 69.21% 69.21% # Class of executed instruction -system.cpu.op_class::IntMult 2119587 0.22% 69.43% # Class of executed instruction -system.cpu.op_class::IntDiv 97316 0.01% 69.44% # Class of executed instruction +system.cpu.op_class::IntAlu 674595310 69.21% 69.21% # Class of executed instruction +system.cpu.op_class::IntMult 2119774 0.22% 69.43% # Class of executed instruction +system.cpu.op_class::IntDiv 97321 0.01% 69.44% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction @@ -573,120 +574,120 @@ system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::MemRead 156084233 16.01% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 141663937 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 156086585 16.01% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 141666359 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 974660774 # Class of executed instruction -system.cpu.dcache.tags.replacements 9257757 # number of replacements +system.cpu.op_class::total 974677774 # Class of executed instruction +system.cpu.dcache.tags.replacements 9257096 # number of replacements system.cpu.dcache.tags.tagsinuse 511.942792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288314388 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9258269 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.141284 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 288320002 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9257608 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.144114 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.942792 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 400 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1200005027 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1200005027 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146175483 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146175483 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 134535173 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 134535173 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 372977 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 372977 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3285857 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3285857 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3569334 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3569334 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 280710656 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 280710656 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 281083633 # number of overall hits -system.cpu.dcache.overall_hits::total 281083633 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4833353 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4833353 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1968837 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1968837 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1108112 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1108112 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1218438 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1218438 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 285095 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 285095 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 6802190 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6802190 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7910302 # number of overall misses -system.cpu.dcache.overall_misses::total 7910302 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 82947634000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 82947634000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66857595000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66857595000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73267815000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 73267815000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4367237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4367237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149805229000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149805229000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 149805229000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 149805229000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 151008836 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 151008836 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 136504010 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 136504010 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481089 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1481089 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1200023494 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1200023494 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146178724 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146178724 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 134536913 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 134536913 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 373150 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 373150 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 333652 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 333652 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286715 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3286715 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3569347 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3569347 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 280715637 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 280715637 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 281088787 # number of overall hits +system.cpu.dcache.overall_hits::total 281088787 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4832437 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4832437 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1969504 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1969504 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1107960 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1107960 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1218811 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1218811 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 284252 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 284252 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 6801941 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6801941 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7909901 # number of overall misses +system.cpu.dcache.overall_misses::total 7909901 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82966383500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82966383500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66911897500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66911897500 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73402202000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 73402202000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4352844000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4352844000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 248500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 248500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 149878281000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 149878281000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 149878281000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 149878281000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 151011161 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 151011161 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 136506417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 136506417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481110 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1481110 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552463 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 1552463 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570952 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3570952 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3569336 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3569336 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 287512846 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 287512846 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 288993935 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 288993935 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032007 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032007 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014423 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014423 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748174 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.748174 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.784842 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.784842 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079837 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079837 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570967 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3570967 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3569350 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3569350 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 287517578 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 287517578 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 288998688 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 288998688 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014428 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014428 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748061 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.748061 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785082 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.785082 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079601 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079601 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023659 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023659 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027372 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027372 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17161.509619 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17161.509619 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33957.912717 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33957.912717 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60132.575478 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60132.575478 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15318.532419 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15318.532419 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.088005 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22023.088005 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18937.991116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18937.991116 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023657 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023657 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027370 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027370 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17168.642550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17168.642550 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33973.984059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33973.984059 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60224.433485 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60224.433485 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15313.327611 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15313.327611 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82833.333333 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82833.333333 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22034.634085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22034.634085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18948.186709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18948.186709 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -695,154 +696,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7254734 # number of writebacks -system.cpu.dcache.writebacks::total 7254734 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23450 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 23450 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21299 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67486 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 67486 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 44749 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 44749 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 44749 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 44749 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4809903 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 4809903 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1947538 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1947538 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1106332 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1106332 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1218438 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1218438 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 217609 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 217609 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 6757441 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 6757441 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 7863773 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 7863773 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7253164 # number of writebacks +system.cpu.dcache.writebacks::total 7253164 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23327 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 23327 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21303 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21303 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67434 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 67434 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44630 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4809110 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 4809110 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1948201 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1948201 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1106180 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1106180 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1218811 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1218811 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 216818 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 216818 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 6757311 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6757311 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 7863491 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 7863491 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76766734500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 76766734500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63925265000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 63925265000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20988734000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20988734000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72049377000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72049377000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2989622500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2989622500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140691999500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 140691999500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161680733500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161680733500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6200659500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6200659500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217612000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217612000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12418271500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12418271500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031852 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031852 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746972 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746972 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.784842 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.784842 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060939 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060939 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76783212500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76783212500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63978351000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 63978351000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20966645000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20966645000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72183391000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72183391000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2984919500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2984919500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140761563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 140761563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161728208500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161728208500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199745000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199745000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217608000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217608000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417353000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031846 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014272 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014272 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785082 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785082 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060717 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023503 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023503 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027211 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027211 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15960.141920 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15960.141920 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32823.629115 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32823.629115 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18971.460647 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18971.460647 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59132.575478 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59132.575478 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13738.505760 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13738.505760 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20820.307495 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20820.307495 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20560.198457 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20560.198457 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183984.911875 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.911875 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.084846 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.084846 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184220.019285 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184220.019285 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023502 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023502 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027209 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15966.200087 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15966.200087 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32839.707505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32839.707505 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18954.098790 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18954.098790 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59224.433485 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59224.433485 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13766.935863 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13766.935863 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81833.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81833.333333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20831.002673 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20831.002673 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20566.973180 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20566.973180 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183957.776987 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183957.776987 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.966180 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.966180 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184206.393710 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184206.393710 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13402148 # number of replacements +system.cpu.icache.tags.replacements 13398086 # number of replacements system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816007156 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13402660 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.883970 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 816025451 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13398598 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.903794 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 185 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 842812486 # Number of tag accesses -system.cpu.icache.tags.data_accesses 842812486 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 816007156 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 816007156 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 816007156 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 816007156 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 816007156 # number of overall hits -system.cpu.icache.overall_hits::total 816007156 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13402665 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13402665 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13402665 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13402665 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13402665 # number of overall misses -system.cpu.icache.overall_misses::total 13402665 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 183016744500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 183016744500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 183016744500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 183016744500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 183016744500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 183016744500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 829409821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 829409821 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 829409821 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 829409821 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 829409821 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 829409821 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016159 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016159 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016159 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016159 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016159 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016159 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13655.250243 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13655.250243 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13655.250243 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13655.250243 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13655.250243 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13655.250243 # average overall miss latency +system.cpu.icache.tags.tag_accesses 842822657 # Number of tag accesses +system.cpu.icache.tags.data_accesses 842822657 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 816025451 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 816025451 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 816025451 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 816025451 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 816025451 # number of overall hits +system.cpu.icache.overall_hits::total 816025451 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13398603 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13398603 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13398603 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13398603 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13398603 # number of overall misses +system.cpu.icache.overall_misses::total 13398603 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182979269500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182979269500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182979269500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182979269500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182979269500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182979269500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 829424054 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 829424054 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 829424054 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 829424054 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 829424054 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 829424054 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016154 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016154 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016154 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016154 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016154 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016154 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13656.593116 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13656.593116 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13656.593116 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13656.593116 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13656.593116 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13656.593116 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -851,230 +852,231 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 13402148 # number of writebacks -system.cpu.icache.writebacks::total 13402148 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13402665 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13402665 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13402665 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13402665 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13402665 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13402665 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 13398086 # number of writebacks +system.cpu.icache.writebacks::total 13398086 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13398603 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13398603 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13398603 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13398603 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13398603 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13398603 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169614079500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 169614079500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169614079500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 169614079500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169614079500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 169614079500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169580666500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 169580666500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169580666500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 169580666500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169580666500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 169580666500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016159 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016159 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016159 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016159 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016159 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016159 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12655.250243 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12655.250243 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12655.250243 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12655.250243 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12655.250243 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12655.250243 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016154 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016154 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016154 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016154 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016154 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016154 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12656.593116 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12656.593116 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12656.593116 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12656.593116 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12656.593116 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12656.593116 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1000398 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65223.179314 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 41597566 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1062477 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 39.151498 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1001888 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65194.742933 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 41566827 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1063831 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 39.072773 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 56076472500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37712.043475 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 216.479752 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 326.532168 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8422.895801 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 18545.228118 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575440 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003303 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128523 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.282978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995227 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 193 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61886 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 193 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 37699.189777 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 214.416551 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 325.189859 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8460.753962 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 18495.192784 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.575244 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003272 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129101 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.282214 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994793 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 190 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61753 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 189 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2453 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5516 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53472 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.002945 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944305 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 371574999 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 371574999 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 309727 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 241978 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 551705 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7254734 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7254734 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13400558 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13400558 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 8841 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 8841 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1588861 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1588861 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13332668 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 13332668 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5913249 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5913249 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 738936 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 738936 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 309727 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 241978 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787990 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787990 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166390 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166390 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005223 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.035964 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.035964 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.393538 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.393538 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006693 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009063 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066884 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.027822 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006693 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009063 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066884 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.027822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127216.395349 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70684.426230 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70684.426230 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120983.207732 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120983.207732 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122181.686358 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122181.686358 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123185.935765 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123185.935765 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120266.161559 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120266.161559 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122181.686358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121886.832734 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121957.998928 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122181.686358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121886.832734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121957.998928 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166475 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166475 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005230 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036001 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036001 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394312 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394312 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006703 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009052 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066947 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.027852 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006703 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009052 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066947 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.027852 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127189.157748 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70683.669725 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70683.669725 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70333.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70333.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121018.798556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121018.798556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122271.570055 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122271.570055 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123142.288005 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123142.288005 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120264.067026 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120264.067026 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122271.570055 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121889.851499 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121970.701984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122271.570055 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121889.851499 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121970.701984 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171461.070560 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138965.539459 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.758514 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.758514 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171433.935671 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138953.636091 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.639848 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.639848 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172207.981012 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149330.659972 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172194.355437 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149322.350387 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 45838189 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23177247 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2695 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2695 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 45828995 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23172776 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2709 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2709 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 972617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20509993 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 972528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20504109 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8211016 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13400558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2162503 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 41540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 41542 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1906001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1906001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13402665 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6142720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1325102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1218438 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40292138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27992932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598317 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 853478 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69736865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715578772 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 979098990 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1953528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2494512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2699125802 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1572119 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 24940276 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019256 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.137423 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8210793 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13396481 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2163559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 41501 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 41504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1906703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1906703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13398603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6140983 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1325475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1218811 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40279937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27990886 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 853214 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69722195 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715057876 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978932526 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1952280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2493088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2698435770 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1573850 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 24936909 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019271 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.137475 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24460029 98.07% 98.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 480247 1.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24456353 98.07% 98.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 480556 1.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 24940276 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 43858094500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 24936909 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 43847676000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1606889 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1611389 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20147122500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20141029500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12740327469 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12738944468 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 354126000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 354123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 541664000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 541578000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40324 # Transaction distribution -system.iobus.trans_dist::ReadResp 40324 # Transaction distribution +system.iobus.trans_dist::ReadReq 40323 # Transaction distribution +system.iobus.trans_dist::ReadResp 40323 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) @@ -1281,18 +1284,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353788 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1302,24 +1303,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42148000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42147000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) @@ -1332,79 +1332,73 @@ system.iobus.reqLayer16.occupancy 16500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25746500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25743500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 169000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 38603000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 565463411 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 122000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565448922 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.446943 # Cycle average of tags in use +system.iocache.tags.replacements 115483 # number of replacements +system.iocache.tags.tagsinuse 10.446937 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13183709784000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.511467 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935476 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935470 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.219467 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.433467 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039884 # Number of tag accesses -system.iocache.tags.data_accesses 1039884 # Number of data accesses +system.iocache.tags.tag_accesses 1039875 # Number of tag accesses +system.iocache.tags.data_accesses 1039875 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses -system.iocache.demand_misses::total 8879 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses +system.iocache.demand_misses::total 8878 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8839 # number of overall misses -system.iocache.overall_misses::total 8879 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1627645138 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1632715138 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8838 # number of overall misses +system.iocache.overall_misses::total 8878 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1645846130 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1650916630 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13865007784 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13865007784 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1627645138 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1633066138 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1627645138 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1633066138 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13863091781 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13863091781 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1645846130 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1651267630 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1645846130 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1651267630 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1418,55 +1412,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184143.583890 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183947.176431 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186223.821000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186018.775211 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.697667 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129987.697667 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 184143.583890 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183924.556594 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 184143.583890 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183924.556594 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33671 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129969.734690 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129969.734690 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186223.821000 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 185995.452805 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 186223.821000 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 185995.452805 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33963 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3509 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.631293 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.678826 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185695138 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1188915138 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1203946130 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1207166630 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8531807784 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8531807784 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1185695138 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1189116138 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1185695138 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1189116138 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8529891781 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8529891781 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1203946130 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1207367630 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1203946130 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1207367630 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1480,73 +1474,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134143.583890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133947.176431 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136223.821000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136018.775211 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79987.697667 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79987.697667 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 134143.583890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 133924.556594 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 134143.583890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133924.556594 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79969.734690 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79969.734690 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136223.821000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 135995.452805 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136223.821000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 135995.452805 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 380595 # Transaction distribution +system.membus.trans_dist::ReadResp 380834 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::WritebackDirty 956243 # Transaction distribution -system.membus.trans_dist::CleanEvict 155849 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33272 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33274 # Transaction distribution -system.membus.trans_dist::ReadExReq 796069 # Transaction distribution -system.membus.trans_dist::ReadExResp 796069 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 303768 # Transaction distribution +system.membus.trans_dist::WritebackDirty 957595 # Transaction distribution +system.membus.trans_dist::CleanEvict 155985 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33274 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 33277 # Transaction distribution +system.membus.trans_dist::ReadExReq 797439 # Transaction distribution +system.membus.trans_dist::ReadExResp 797439 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 304007 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3338566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3468258 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341194 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341194 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3809452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3343278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3472970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3814166 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124348000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124517826 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7226112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7226112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131743938 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3260 # Total snoops (count) -system.membus.snoop_fanout::samples 2465217 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124537568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124707394 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7226176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7226176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131933570 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3258 # Total snoops (count) +system.membus.snoop_fanout::samples 2468309 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2465217 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2468309 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2465217 # Request fanout histogram -system.membus.reqLayer0.occupancy 106924000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2468309 # Request fanout histogram +system.membus.reqLayer0.occupancy 106920500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5793500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5785500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6289776705 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6298398949 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6042674003 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6051404500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227496341 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227572547 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal index 282713d4d..dd5c13da3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal @@ -110,26 +110,26 @@ [ 3.145140] pci 0000:00:00.0: assigning IRQ 33
[ 3.145154] pci 0000:00:01.0: fixup irq: got 34
[ 3.145164] pci 0000:00:01.0: assigning IRQ 34
-[ 3.145179] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.145194] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.145178] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.145193] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.145208] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.145223] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.145222] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.145236] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.145249] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.145263] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.145262] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.145276] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.146194] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.146723] ata_piix 0000:00:01.0: version 2.13
+[ 3.146724] ata_piix 0000:00:01.0: version 2.13
[ 3.146736] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.146781] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.147382] scsi0 : ata_piix
-[ 3.147567] scsi1 : ata_piix
-[ 3.147621] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.147634] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.147838] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.147851] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.147874] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.147887] e1000 0000:00:00.0: enabling bus mastering
+[ 3.147384] scsi0 : ata_piix
+[ 3.147568] scsi1 : ata_piix
+[ 3.147622] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.147635] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.147840] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.147853] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.147876] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.147889] e1000 0000:00:00.0: enabling bus mastering
[ 3.301640] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.301651] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.301686] ata1.00: configured for UDMA/33
@@ -160,7 +160,7 @@ [ 3.470418] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.586550] random: dd urandom read with 21 bits of entropy available
+[ 3.586551] random: dd urandom read with 21 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.791839] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.791840] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|