diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing')
5 files changed, 2989 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini new file mode 100644 index 000000000..9587f8b73 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -0,0 +1,1229 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain +atags_addr=134217728 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=timing +mem_ranges=2147483648:2415919103 +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.cpu.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=1 +frontend_latency=2 +response_latency=2 +use_default_range=true +width=16 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=2147483648:2415919103 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr new file mode 100755 index 000000000..744db2c76 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr @@ -0,0 +1,11 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout new file mode 100644 index 000000000..86944f7db --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout @@ -0,0 +1,16 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 15:46:15 +gem5 started Oct 29 2014 16:01:52 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-simple-timing +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 + 0: system.cpu.isa: ISA system set to: 0x500ab00 0x500ab00 +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80080000 +info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 51781056074000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt new file mode 100644 index 000000000..d577712e0 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -0,0 +1,1550 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.824462 # Number of seconds simulated +sim_ticks 51824462100500 # Number of ticks simulated +final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 723017 # Simulator instruction rate (inst/s) +host_op_rate 849578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41937024652 # Simulator tick rate (ticks/s) +host_mem_usage 712044 # Number of bytes of host memory used +host_seconds 1235.77 # Real time elapsed on the host +sim_insts 893481288 # Number of instructions simulated +sim_ops 1049881338 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory +system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory +system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 923811 # Number of read requests accepted +system.physmem.writeReqs 1833124 # Number of write requests accepted +system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue +system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 57129 # Per bank write bursts +system.physmem.perBankRdBursts::1 60965 # Per bank write bursts +system.physmem.perBankRdBursts::2 52485 # Per bank write bursts +system.physmem.perBankRdBursts::3 50413 # Per bank write bursts +system.physmem.perBankRdBursts::4 54002 # Per bank write bursts +system.physmem.perBankRdBursts::5 59718 # Per bank write bursts +system.physmem.perBankRdBursts::6 51713 # Per bank write bursts +system.physmem.perBankRdBursts::7 51669 # Per bank write bursts +system.physmem.perBankRdBursts::8 50247 # Per bank write bursts +system.physmem.perBankRdBursts::9 101235 # Per bank write bursts +system.physmem.perBankRdBursts::10 59848 # Per bank write bursts +system.physmem.perBankRdBursts::11 58323 # Per bank write bursts +system.physmem.perBankRdBursts::12 55369 # Per bank write bursts +system.physmem.perBankRdBursts::13 55988 # Per bank write bursts +system.physmem.perBankRdBursts::14 51743 # Per bank write bursts +system.physmem.perBankRdBursts::15 52477 # Per bank write bursts +system.physmem.perBankWrBursts::0 110630 # Per bank write bursts +system.physmem.perBankWrBursts::1 112240 # Per bank write bursts +system.physmem.perBankWrBursts::2 108805 # Per bank write bursts +system.physmem.perBankWrBursts::3 108103 # Per bank write bursts +system.physmem.perBankWrBursts::4 111102 # Per bank write bursts +system.physmem.perBankWrBursts::5 113339 # Per bank write bursts +system.physmem.perBankWrBursts::6 105567 # Per bank write bursts +system.physmem.perBankWrBursts::7 107723 # Per bank write bursts +system.physmem.perBankWrBursts::8 108849 # Per bank write bursts +system.physmem.perBankWrBursts::9 115780 # Per bank write bursts +system.physmem.perBankWrBursts::10 115663 # Per bank write bursts +system.physmem.perBankWrBursts::11 113049 # Per bank write bursts +system.physmem.perBankWrBursts::12 112494 # Per bank write bursts +system.physmem.perBankWrBursts::13 116984 # Per bank write bursts +system.physmem.perBankWrBursts::14 111502 # Per bank write bursts +system.physmem.perBankWrBursts::15 110389 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 145 # Number of times write queue was full causing retry +system.physmem.totGap 51824459475500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 43101 # Read request sizes (log2) +system.physmem.readPktSize::3 13 # Read request sizes (log2) +system.physmem.readPktSize::4 2 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 880695 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 1 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1830551 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads +system.physmem.totQLat 12043609520 # Total ticks spent queuing +system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing +system.physmem.readRowHits 694872 # Number of row buffer hits during reads +system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes +system.physmem.avgGap 18797853.22 # Average gap between requests +system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.655841 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.672178 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 211321 # Table walker walks requested +system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 167775531 # DTB read hits +system.cpu.dtb.read_misses 155743 # DTB read misses +system.cpu.dtb.write_hits 152648275 # DTB write hits +system.cpu.dtb.write_misses 55578 # DTB write misses +system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 167931274 # DTB read accesses +system.cpu.dtb.write_accesses 152703853 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 320423806 # DTB hits +system.cpu.dtb.misses 211321 # DTB misses +system.cpu.dtb.accesses 320635127 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 122916 # Table walker walks requested +system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 894030670 # ITB inst hits +system.cpu.itb.inst_misses 122916 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 894153586 # ITB inst accesses +system.cpu.itb.hits 894030670 # DTB hits +system.cpu.itb.misses 122916 # DTB misses +system.cpu.itb.accesses 894153586 # DTB accesses +system.cpu.numCycles 103648924201 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 893481288 # Number of instructions committed +system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses +system.cpu.num_func_calls 52999943 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls +system.cpu.num_int_insts 963989017 # number of integer instructions +system.cpu.num_fp_insts 895873 # number of float instructions +system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read +system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written +system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read +system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written +system.cpu.num_mem_refs 320407593 # number of memory refs +system.cpu.num_load_insts 167768846 # Number of load instructions +system.cpu.num_store_insts 152638747 # Number of store instructions +system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles +system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969376 # Percentage of idle cycles +system.cpu.Branches 199584978 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1050473844 # Class of executed instruction +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 10213653 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits +system.cpu.dcache.overall_hits::total 301988446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses +system.cpu.dcache.overall_misses::total 8832117 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3211087000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 3211087000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015384 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 470306 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40333 # Transaction distribution +system.iobus.trans_dist::ReadResp 40333 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 115493 # number of replacements +system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1039965 # Number of tag accesses +system.iocache.tags.data_accesses 1039965 # Number of data accesses +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses +system.iocache.demand_misses::total 8888 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8848 # number of overall misses +system.iocache.overall_misses::total 8888 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 448489 # Transaction distribution +system.membus.trans_dist::ReadResp 448489 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::Writeback 1214153 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution +system.membus.trans_dist::ReadExReq 512353 # Transaction distribution +system.membus.trans_dist::ReadExResp 512353 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3324 # Total snoops (count) +system.membus.snoop_fanout::samples 2750930 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2750930 # Request fanout histogram +system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 13 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal new file mode 100644 index 000000000..5957040e9 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal @@ -0,0 +1,183 @@ +[ 0.000000] Initializing cgroup subsys cpu
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
+[ 0.000000] Memory limited to 256MB
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
+[ 0.000000] On node 0 totalpages: 65536
+[ 0.000000] DMA zone: 896 pages used for memmap
+[ 0.000000] DMA zone: 0 pages reserved
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
+[ 0.000000] Virtual kernel memory layout:
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] Preemptible hierarchical RCU implementation.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000039] Console: colour dummy device 80x25
+[ 0.000042] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000045] pid_max: default: 32768 minimum: 301
+[ 0.000065] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000068] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000254] hw perfevents: no hardware support available
+[ 1.060134] CPU1: failed to come online
+[ 2.080264] CPU2: failed to come online
+[ 3.100395] CPU3: failed to come online
+[ 3.100400] Brought up 1 CPUs
+[ 3.100402] SMP: Total of 1 processors activated.
+[ 3.100500] devtmpfs: initialized
+[ 3.101762] atomic64_test: passed
+[ 3.101843] regulator-dummy: no parameters
+[ 3.102644] NET: Registered protocol family 16
+[ 3.102917] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.102927] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.103581] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.103585] Serial: AMBA PL011 UART driver
+[ 3.103931] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.103997] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.104547] console [ttyAMA0] enabled
+[ 3.104647] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.104695] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.104744] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.104789] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130966] 3V3: 3300 mV
+[ 3.131042] vgaarb: loaded
+[ 3.131134] SCSI subsystem initialized
+[ 3.131205] libata version 3.00 loaded.
+[ 3.131293] usbcore: registered new interface driver usbfs
+[ 3.131321] usbcore: registered new interface driver hub
+[ 3.131375] usbcore: registered new device driver usb
+[ 3.131420] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131429] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131451] PTP clock support registered
+[ 3.131688] Switched to clocksource arch_sys_counter
+[ 3.133862] NET: Registered protocol family 2
+[ 3.134013] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.134040] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.134072] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.134099] TCP: reno registered
+[ 3.134107] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134124] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134187] NET: Registered protocol family 1
+[ 3.134256] RPC: Registered named UNIX socket transport module.
+[ 3.134266] RPC: Registered udp transport module.
+[ 3.134274] RPC: Registered tcp transport module.
+[ 3.134283] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.134296] PCI: CLS 0 bytes, default 64
+[ 3.134626] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.134832] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.138917] fuse init (API version 7.23)
+[ 3.139097] msgmni has been set to 469
+[ 3.143447] io scheduler noop registered
+[ 3.143560] io scheduler cfq registered (default)
+[ 3.144375] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.144389] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.144401] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.144415] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.144425] pci_bus 0000:00: scanning bus
+[ 3.144438] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.144452] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.144469] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.144534] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.144547] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.144560] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.144572] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.144584] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.144596] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.144609] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.144672] pci_bus 0000:00: fixups for bus
+[ 3.144681] pci_bus 0000:00: bus scan returning with max=00
+[ 3.144694] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.144718] pci 0000:00:00.0: fixup irq: got 33
+[ 3.144728] pci 0000:00:00.0: assigning IRQ 33
+[ 3.144741] pci 0000:00:01.0: fixup irq: got 34
+[ 3.144750] pci 0000:00:01.0: assigning IRQ 34
+[ 3.144764] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.144778] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.144792] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.144806] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.144818] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.144831] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.144844] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.144856] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.145803] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.146345] ata_piix 0000:00:01.0: version 2.13
+[ 3.146356] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.146386] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.146981] scsi0 : ata_piix
+[ 3.147177] scsi1 : ata_piix
+[ 3.147237] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.147249] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.147450] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.147462] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.147484] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.147496] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301720] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301730] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301764] ata1.00: configured for UDMA/33
+[ 3.301835] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.302052] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.302087] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.302146] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.302156] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.302186] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.302399] sda: sda1
+[ 3.302620] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.422060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.422074] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.422105] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.422115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.422148] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.422160] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.422304] usbcore: registered new interface driver usb-storage
+[ 3.422400] mousedev: PS/2 mouse device common for all mice
+[ 3.422718] usbcore: registered new interface driver usbhid
+[ 3.422728] usbhid: USB HID core driver
+[ 3.422776] TCP: cubic registered
+[ 3.422785] NET: Registered protocol family 17
+ +[ 3.423415] devtmpfs: mounted
+[ 3.423469] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+ + +[ 3.470498] udevd[607]: starting version 182
+Starting Bootlog daemon: bootlogd.
+[ 3.596627] random: dd urandom read with 22 bits of entropy available
+Populating dev cache
+net.ipv4.conf.default.rp_filter = 1
+net.ipv4.conf.all.rp_filter = 1
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+Mon Jan 27 08:00:00 UTC 2014
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+
INIT: Entering runlevel: 5
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 3.801922] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Sending discover...
+Sending discover...
+Sending discover...
+No lease, forking to background
+done.
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6
+rpcbind: cannot create socket for tcp6
+done.
+rpcbind: cannot get uid of '': Success
+creating NFS state directory: done
+starting statd: done
|