diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 2c9d73210..505f419d1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111166 # Nu sim_ticks 51111166190000 # Number of ticks simulated final_tick 51111166190000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1663860 # Simulator instruction rate (inst/s) -host_op_rate 1955365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 86501229007 # Simulator tick rate (ticks/s) -host_mem_usage 721112 # Number of bytes of host memory used -host_seconds 590.87 # Real time elapsed on the host +host_inst_rate 942692 # Simulator instruction rate (inst/s) +host_op_rate 1107850 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49008962729 # Simulator tick rate (ticks/s) +host_mem_usage 679656 # Number of bytes of host memory used +host_seconds 1042.89 # Real time elapsed on the host sim_insts 983128290 # Number of instructions simulated sim_ops 1155370468 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -156,7 +156,7 @@ system.cpu0.dtb.flush_tlb 51122 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56806 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 56742 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -226,7 +226,7 @@ system.cpu0.itb.flush_tlb 51122 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40500 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 40436 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -560,7 +560,7 @@ system.cpu1.dtb.flush_tlb 51111 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56691 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 56630 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 4731 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -630,7 +630,7 @@ system.cpu1.itb.flush_tlb 51111 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 41078 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 41017 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |