diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic')
5 files changed, 1116 insertions, 830 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini index 43d12537e..80aff2637 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -122,6 +136,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -168,8 +190,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -192,9 +219,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -208,9 +240,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[3] @@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -246,8 +287,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -305,9 +351,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -321,9 +372,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.toL2Bus.slave[2] @@ -338,6 +394,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -356,6 +413,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -387,9 +448,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -403,9 +469,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.isa] @@ -458,9 +529,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -474,9 +550,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.tracer] @@ -507,9 +588,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -523,13 +609,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -548,8 +638,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -560,13 +655,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -585,20 +684,31 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -610,11 +720,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -625,16 +740,28 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=2147483648:2415919103 port=system.membus.master[5] @@ -649,10 +776,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -733,14 +865,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -749,13 +886,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -765,6 +907,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -835,10 +978,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -918,17 +1066,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -954,12 +1107,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -967,14 +1126,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -1060,14 +1224,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1076,13 +1245,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1091,13 +1265,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1105,11 +1284,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1123,11 +1307,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1141,19 +1330,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1199,14 +1394,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1215,11 +1425,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1229,21 +1444,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1253,12 +1478,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1267,10 +1497,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1280,12 +1515,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1295,26 +1535,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1323,10 +1573,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1334,10 +1589,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1345,21 +1605,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1373,11 +1643,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1388,11 +1663,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1400,10 +1680,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -1419,9 +1704,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr index 4c76ae25b..273d7bcba 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr @@ -2,8 +2,11 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 +warn: ClockedObject: Already in the requested power state, request ignored warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist warn: Tried to read RealView I/O at offset 0x8 that doesn't exist @@ -592,15 +595,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout index 9f2f9de0b..65569f1e5 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 12:10:26 -gem5 executing on e104799-lin, pid 2423 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:38:22 +gem5 executing on e108600-lin, pid 23081 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 505f419d1..233e6de0a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111166 # Number of seconds simulated -sim_ticks 51111166190000 # Number of ticks simulated -final_tick 51111166190000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111167 # Number of seconds simulated +sim_ticks 51111167268500 # Number of ticks simulated +final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 942692 # Simulator instruction rate (inst/s) -host_op_rate 1107850 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49008962729 # Simulator tick rate (ticks/s) -host_mem_usage 679656 # Number of bytes of host memory used -host_seconds 1042.89 # Real time elapsed on the host -sim_insts 983128290 # Number of instructions simulated -sim_ops 1155370468 # Number of ops (including micro ops) simulated +host_inst_rate 810187 # Simulator instruction rate (inst/s) +host_op_rate 952145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42160127212 # Simulator tick rate (ticks/s) +host_mem_usage 675168 # Number of bytes of host memory used +host_seconds 1212.31 # Real time elapsed on the host +sim_insts 982198023 # Number of instructions simulated +sim_ops 1154295627 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 206080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 186880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3298228 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38035976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 206656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 186304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2187520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 36841280 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 435200 # Number of bytes read from this memory -system.physmem.bytes_read::total 81584124 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3298228 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2187520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5485748 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103274624 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 206336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 188224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3277940 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38030472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 207616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 185152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2205440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36882176 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory +system.physmem.bytes_read::total 81620156 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3277940 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2205440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5483380 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103277952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103295204 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2920 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 91942 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 594325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 34180 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 575645 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6800 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315172 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613666 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103298532 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 594239 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3244 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2893 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 576284 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315735 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613718 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616239 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 64530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 744181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 720807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 64530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42799 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020588 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1616291 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 64134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 744074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 721607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 64134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020653 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2020991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 64530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 744584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 720807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3617200 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.physmem.bw_write::total 2021056 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 64134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 744476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 721607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3617970 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -87,9 +87,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -97,7 +97,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -127,47 +127,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 145178 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 145178 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 145178 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 145178 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 145178 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 145515 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 145515 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 145515 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 145515 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 145515 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 108127 85.58% 85.58% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 18215 14.42% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 126342 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 145178 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 108307 85.67% 85.67% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18122 14.33% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126429 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 145515 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 145178 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126342 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 145515 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126429 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126342 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 271520 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126429 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 271944 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91916513 # DTB read hits -system.cpu0.dtb.read_misses 107962 # DTB read misses -system.cpu0.dtb.write_hits 84123596 # DTB write hits -system.cpu0.dtb.write_misses 37216 # DTB write misses +system.cpu0.dtb.read_hits 91812952 # DTB read hits +system.cpu0.dtb.read_misses 108269 # DTB read misses +system.cpu0.dtb.write_hits 84016904 # DTB write hits +system.cpu0.dtb.write_misses 37246 # DTB write misses system.cpu0.dtb.flush_tlb 51122 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56742 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 25430 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56668 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4782 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10952 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92024475 # DTB read accesses -system.cpu0.dtb.write_accesses 84160812 # DTB write accesses +system.cpu0.dtb.perms_faults 10953 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91921221 # DTB read accesses +system.cpu0.dtb.write_accesses 84054150 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176040109 # DTB hits -system.cpu0.dtb.misses 145178 # DTB misses -system.cpu0.dtb.accesses 176185287 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 175829856 # DTB hits +system.cpu0.dtb.misses 145515 # DTB misses +system.cpu0.dtb.accesses 175975371 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -197,311 +197,311 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 70488 # Table walker walks requested -system.cpu0.itb.walker.walksLong 70488 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 70488 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 70488 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 70488 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 70816 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70816 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70816 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70816 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70816 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61740 96.00% 96.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2570 4.00% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64310 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 62041 96.03% 96.03% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2564 3.97% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64605 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70488 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70488 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70816 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70816 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64310 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64310 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 134798 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 493160707 # ITB inst hits -system.cpu0.itb.inst_misses 70488 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64605 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64605 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135421 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 492374883 # ITB inst hits +system.cpu0.itb.inst_misses 70816 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51122 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 25185 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 570 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40436 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 25430 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40442 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 493231195 # ITB inst accesses -system.cpu0.itb.hits 493160707 # DTB hits -system.cpu0.itb.misses 70488 # DTB misses -system.cpu0.itb.accesses 493231195 # DTB accesses -system.cpu0.numPwrStateTransitions 16910 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 8455 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 5871638061.761680 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 113702139546.283386 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3675 43.47% 43.47% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4716 55.78% 99.24% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.25% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 492445699 # ITB inst accesses +system.cpu0.itb.hits 492374883 # DTB hits +system.cpu0.itb.misses 70816 # DTB misses +system.cpu0.itb.accesses 492445699 # DTB accesses +system.cpu0.numPwrStateTransitions 16972 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8486 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 5850237301.708461 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 113494821184.972778 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3706 43.67% 43.67% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4716 55.57% 99.25% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.26% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.53% 99.79% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 5 0.06% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 12 0.14% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 3977575082060 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 8455 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1466466377805 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 49644699812195 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 98036837820 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 3977575161560 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8486 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1466053526202 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 49645113742298 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 98039867564 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu0.committedInsts 492942676 # Number of instructions committed -system.cpu0.committedOps 578945163 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 530362809 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 453024 # Number of float alu accesses -system.cpu0.num_func_calls 28530371 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76157318 # number of instructions that are conditional controls -system.cpu0.num_int_insts 530362809 # number of integer instructions -system.cpu0.num_fp_insts 453024 # number of float instructions -system.cpu0.num_int_register_reads 784322084 # number of times the integer registers were read -system.cpu0.num_int_register_writes 421327896 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 740492 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 361708 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 133053105 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132724899 # number of times the CC registers were written -system.cpu0.num_mem_refs 176163553 # number of memory refs -system.cpu0.num_load_insts 92011132 # Number of load instructions -system.cpu0.num_store_insts 84152421 # Number of store instructions -system.cpu0.num_idle_cycles 96928545322.027405 # Number of idle cycles -system.cpu0.num_busy_cycles 1108292497.972592 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011305 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988695 # Percentage of idle cycles -system.cpu0.Branches 110262676 # Number of branches fetched +system.cpu0.committedInsts 492156218 # Number of instructions committed +system.cpu0.committedOps 578106768 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 529626923 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 450865 # Number of float alu accesses +system.cpu0.num_func_calls 28493046 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76041586 # number of instructions that are conditional controls +system.cpu0.num_int_insts 529626923 # number of integer instructions +system.cpu0.num_fp_insts 450865 # number of float instructions +system.cpu0.num_int_register_reads 782885196 # number of times the integer registers were read +system.cpu0.num_int_register_writes 420741799 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 732662 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 369512 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 132705210 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132383544 # number of times the CC registers were written +system.cpu0.num_mem_refs 175953589 # number of memory refs +system.cpu0.num_load_insts 91907608 # Number of load instructions +system.cpu0.num_store_insts 84045981 # Number of store instructions +system.cpu0.num_idle_cycles 96932341935.251450 # Number of idle cycles +system.cpu0.num_busy_cycles 1107525628.748547 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011297 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988703 # Percentage of idle cycles +system.cpu0.Branches 110098917 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 401826971 69.37% 69.37% # Class of executed instruction -system.cpu0.op_class::IntMult 1176436 0.20% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 51169 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 52500 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 92011132 15.88% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 84152421 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 401201785 69.36% 69.36% # Class of executed instruction +system.cpu0.op_class::IntMult 1174308 0.20% 69.56% # Class of executed instruction +system.cpu0.op_class::IntDiv 49945 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 53536 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::MemRead 91907608 15.89% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 84045981 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 579270629 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 11609443 # number of replacements +system.cpu0.op_class::total 578433163 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 11606055 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 340216355 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11609955 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.303848 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 339854312 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11606567 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.281209 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 262.381327 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 249.618393 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.512464 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.487536 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 263.642169 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 248.357550 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.514926 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.485073 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1418915240 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1418915240 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 85703422 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 85585649 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 171289071 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79649076 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 79602210 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 159251286 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209671 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214329 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 424000 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 145368 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 191474 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 336842 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2140895 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2164816 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4305711 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2265304 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2292996 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4558300 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165497866 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165379333 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 330877199 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165707537 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 165593662 # number of overall hits -system.cpu0.dcache.overall_hits::total 331301199 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3022640 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2983261 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6005901 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1299985 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1269181 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2569166 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 790936 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 794497 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1585433 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 765655 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 480562 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1246217 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 125328 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 129063 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 254391 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1417450148 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1417450148 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 85600060 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 85509890 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 171109950 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79543301 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 79530135 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 159073436 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209327 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214988 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 424315 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 144230 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 192053 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2149020 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2154529 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 4303549 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2274909 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2280735 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4555644 # 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number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 797714 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1585882 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 761557 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 485215 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 126793 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 127105 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 253898 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5088280 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 4733004 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 9821284 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5879216 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 5527501 # number of overall misses -system.cpu0.dcache.overall_misses::total 11406717 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88726062 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 88568910 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 177294972 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 80949061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 80871391 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 161820452 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1000607 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1008826 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 2009433 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 911023 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 672036 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1583059 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2266223 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2293879 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4560102 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2265304 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2292997 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4558301 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 170586146 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 170112337 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 340698483 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 171586753 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 171121163 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 342707916 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034067 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033683 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033875 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016059 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015694 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015877 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790456 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787546 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788995 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.840434 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.715084 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787221 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055303 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056264 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055786 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2274909 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2280736 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 170360850 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 169976753 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 171358345 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 170989455 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 342347800 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034038 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033750 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033894 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016024 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015751 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790147 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787709 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788919 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.840768 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.716430 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055713 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055708 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055711 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029828 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027823 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028827 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034264 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032302 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.033284 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029779 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027914 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028848 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034206 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032414 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 8920157 # number of writebacks -system.cpu0.dcache.writebacks::total 8920157 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 14275419 # number of replacements +system.cpu0.dcache.writebacks::writebacks 8916863 # number of writebacks +system.cpu0.dcache.writebacks::total 8916863 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 14265255 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 969443892 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14275931 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.907578 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.598488 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.386111 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.524606 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.475363 # Average percentage of cache occupancy +system.cpu0.icache.tags.total_refs 968523793 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.597080 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.387519 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.524604 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.475366 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 997995764 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 997995764 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 486058611 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 483385281 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 969443892 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 486058611 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 483385281 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 969443892 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 486058611 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 483385281 # number of overall hits -system.cpu0.icache.overall_hits::total 969443892 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7166406 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 7109530 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14275936 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7166406 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 7109530 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14275936 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7166406 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 7109530 # number of overall misses -system.cpu0.icache.overall_misses::total 14275936 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 493225017 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 490494811 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 983719828 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 493225017 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 490494811 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 983719828 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 493225017 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 490494811 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 983719828 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014530 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014495 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014512 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014530 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014495 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014512 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014530 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014495 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014512 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 997055337 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 997055337 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 485300804 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 483222989 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 968523793 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 485300804 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 483222989 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 968523793 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 485300804 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 483222989 # number of overall hits +system.cpu0.icache.overall_hits::total 968523793 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7138684 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7127088 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14265772 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7138684 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7127088 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14265772 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7138684 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7127088 # number of overall misses +system.cpu0.icache.overall_misses::total 14265772 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 492439488 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 490350077 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 492439488 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 490350077 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 492439488 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 490350077 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014497 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014535 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014497 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014535 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014497 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014535 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 14275419 # number of writebacks -system.cpu0.icache.writebacks::total 14275419 # number of writebacks -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 14265255 # number of writebacks +system.cpu0.icache.writebacks::total 14265255 # number of writebacks +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -531,47 +531,47 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 143940 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 143940 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 143940 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 143940 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 143940 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 143141 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143141 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143141 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143141 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143141 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 107031 85.37% 85.37% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 18349 14.63% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 125380 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143940 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 106696 85.47% 85.47% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18135 14.53% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124831 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143141 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143940 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125380 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143141 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124831 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125380 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 269320 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124831 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 267972 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91791346 # DTB read hits -system.cpu1.dtb.read_misses 106897 # DTB read misses -system.cpu1.dtb.write_hits 83829592 # DTB write hits -system.cpu1.dtb.write_misses 37043 # DTB write misses +system.cpu1.dtb.read_hits 91711544 # DTB read hits +system.cpu1.dtb.read_misses 106091 # DTB read misses +system.cpu1.dtb.write_hits 83754683 # DTB write hits +system.cpu1.dtb.write_misses 37050 # DTB write misses system.cpu1.dtb.flush_tlb 51111 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56630 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 24341 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56242 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4731 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4763 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10699 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91898243 # DTB read accesses -system.cpu1.dtb.write_accesses 83866635 # DTB write accesses +system.cpu1.dtb.perms_faults 10698 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91817635 # DTB read accesses +system.cpu1.dtb.write_accesses 83791733 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175620938 # DTB hits -system.cpu1.dtb.misses 143940 # DTB misses -system.cpu1.dtb.accesses 175764878 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 175466227 # DTB hits +system.cpu1.dtb.misses 143141 # DTB misses +system.cpu1.dtb.accesses 175609368 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -601,128 +601,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 69853 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69853 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 69853 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69853 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69853 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 69344 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69344 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69344 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69344 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69344 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61351 96.02% 96.02% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2542 3.98% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63893 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 60893 96.02% 96.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2524 3.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63417 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69853 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69853 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69344 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69344 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63893 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63893 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 133746 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 490430918 # ITB inst hits -system.cpu1.itb.inst_misses 69853 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63417 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63417 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 132761 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 490286660 # ITB inst hits +system.cpu1.itb.inst_misses 69344 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51111 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 24586 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 569 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 41017 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 24341 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40468 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 490500771 # ITB inst accesses -system.cpu1.itb.hits 490430918 # DTB hits -system.cpu1.itb.misses 69853 # DTB misses -system.cpu1.itb.accesses 490500771 # DTB accesses -system.cpu1.numPwrStateTransitions 16606 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8303 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 6010299946.497049 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 129216116342.205185 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3765 45.35% 45.35% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4474 53.88% 99.23% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 490356004 # ITB inst accesses +system.cpu1.itb.hits 490286660 # DTB hits +system.cpu1.itb.misses 69344 # DTB misses +system.cpu1.itb.accesses 490356004 # DTB accesses +system.cpu1.numPwrStateTransitions 16542 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8271 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 6033690194.397533 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 129465330065.337860 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3733 45.13% 45.13% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4474 54.09% 99.23% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.02% 99.25% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 4 0.05% 99.30% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 44 0.53% 99.83% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 3 0.04% 99.88% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 5966367262704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8303 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 1207645734235 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 49903520455765 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 97462088232 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 5966367222968 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8271 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 1206515670638 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 49904651597862 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 97462078889 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 490185614 # Number of instructions committed -system.cpu1.committedOps 576425305 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 528528005 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 428357 # Number of float alu accesses -system.cpu1.num_func_calls 28391089 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 75589435 # number of instructions that are conditional controls -system.cpu1.num_int_insts 528528005 # number of integer instructions -system.cpu1.num_fp_insts 428357 # number of float instructions -system.cpu1.num_int_register_reads 777707533 # number of times the integer registers were read -system.cpu1.num_int_register_writes 419943205 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 679275 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 386980 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 131115369 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 130866277 # number of times the CC registers were written -system.cpu1.num_mem_refs 175739961 # number of memory refs -system.cpu1.num_load_insts 91884045 # Number of load instructions -system.cpu1.num_store_insts 83855916 # Number of store instructions -system.cpu1.num_idle_cycles 96357307601.045395 # Number of idle cycles -system.cpu1.num_busy_cycles 1104780630.954602 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011335 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988665 # Percentage of idle cycles -system.cpu1.Branches 109487364 # Number of branches fetched +system.cpu1.committedInsts 490041805 # Number of instructions committed +system.cpu1.committedOps 576188859 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 528250212 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 430484 # Number of float alu accesses +system.cpu1.num_func_calls 28340797 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75581054 # number of instructions that are conditional controls +system.cpu1.num_int_insts 528250212 # number of integer instructions +system.cpu1.num_fp_insts 430484 # number of float instructions +system.cpu1.num_int_register_reads 777868472 # number of times the integer registers were read +system.cpu1.num_int_register_writes 419771352 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 687105 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 379048 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131312247 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 131056135 # number of times the CC registers were written +system.cpu1.num_mem_refs 175584466 # number of memory refs +system.cpu1.num_load_insts 91803674 # Number of load instructions +system.cpu1.num_store_insts 83780792 # Number of store instructions +system.cpu1.num_idle_cycles 96359431608.339264 # Number of idle cycles +system.cpu1.num_busy_cycles 1102647280.660740 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011314 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988686 # Percentage of idle cycles +system.cpu1.Branches 109433272 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 399711275 69.31% 69.31% # Class of executed instruction -system.cpu1.op_class::IntMult 1178043 0.20% 69.51% # Class of executed instruction -system.cpu1.op_class::IntDiv 49858 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 55322 0.01% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::MemRead 91884045 15.93% 85.46% # Class of executed instruction -system.cpu1.op_class::MemWrite 83855916 14.54% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 399627658 69.32% 69.32% # Class of executed instruction +system.cpu1.op_class::IntMult 1180080 0.20% 69.52% # Class of executed instruction +system.cpu1.op_class::IntDiv 50598 0.01% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 54286 0.01% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::MemRead 91803674 15.92% 85.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 83780792 14.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 576734502 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40249 # Transaction distribution -system.iobus.trans_dist::ReadResp 40249 # Transaction distribution +system.cpu1.op_class::total 576497131 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40242 # Transaction distribution +system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) @@ -739,11 +739,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353528 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -758,55 +758,55 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492000 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115466 # number of replacements +system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113303009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852512 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115484 # number of demand (read+write) misses -system.iocache.demand_misses::total 115524 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses +system.iocache.demand_misses::total 115517 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115484 # number of overall misses -system.iocache.overall_misses::total 115524 # number of overall misses +system.iocache.overall_misses::realview.ide 115477 # number of overall misses +system.iocache.overall_misses::total 115517 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115484 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115524 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115484 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115524 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -828,283 +828,284 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # 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Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1788801 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 26.261828 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37152.914726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.952834 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.226181 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3473.573916 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9619.511696 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.800333 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 210.267974 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2624.848804 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11683.493403 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.566908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002395 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37198.027902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 157.533597 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.219072 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3426.787378 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9571.465720 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.009111 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 207.682961 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2648.640796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11713.200303 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.567597 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002404 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.003711 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.053003 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146782 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002347 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003208 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040052 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.178276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996683 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 268 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62505 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 604 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2729 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4885 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54176 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.953751 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 426507397 # Number of tag accesses -system.l2c.tags.data_accesses 426507397 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 281107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 145752 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 278085 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 143361 # number of ReadReq hits -system.l2c.ReadReq_hits::total 848305 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8920157 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8920157 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 14273844 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 14273844 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5706 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5507 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11213 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 857396 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 833383 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4618367 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 278085 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 143361 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7075337 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4574228 # number of demand (read+write) hits -system.l2c.demand_hits::total 24233802 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 281107 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 145752 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7117565 # number of overall hits -system.l2c.overall_hits::cpu0.data 4618367 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 278085 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 143361 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7075337 # number of overall hits -system.l2c.overall_hits::cpu1.data 4574228 # number of overall hits -system.l2c.overall_hits::total 24233802 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3220 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2920 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3229 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2911 # number of ReadReq misses -system.l2c.ReadReq_misses::total 12280 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 20037 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19894 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 39931 # number of UpgradeReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.052289 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146049 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002335 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003169 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.178729 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996697 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 315 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62701 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 315 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54255 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004807 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.956741 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 426273955 # Number of tag accesses +system.l2c.tags.data_accesses 426273955 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 280712 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 145885 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 277418 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 142199 # number of ReadReq hits +system.l2c.ReadReq_hits::total 846214 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8916863 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8916863 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 14263678 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 5752 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5452 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11204 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 852175 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 837197 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1689372 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 7090160 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 7092615 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 14182775 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3753750 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3744981 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 7498731 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 340284 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 354276 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 694560 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 280712 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 145885 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7090160 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4605925 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 277418 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 142199 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7092615 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4582178 # number of demand (read+write) hits +system.l2c.demand_hits::total 24217092 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 280712 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 145885 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7090160 # number of overall hits +system.l2c.overall_hits::cpu0.data 4605925 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 277418 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 142199 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7092615 # number of overall hits +system.l2c.overall_hits::cpu1.data 4582178 # number of overall hits +system.l2c.overall_hits::total 24217092 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3224 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2941 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3244 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2893 # number of ReadReq misses +system.l2c.ReadReq_misses::total 12302 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 20291 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19639 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 39930 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # 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number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 14273844 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 14273844 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25743 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 25401 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 51144 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 417161 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 410444 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 827605 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 48524 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 34473 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 82997 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 177534 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 166566 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 344100 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 421273 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 130939 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 552212 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3224 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2941 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 48524 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 594695 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3244 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2893 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34473 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 577010 # number of demand (read+write) misses +system.l2c.demand_misses::total 1267004 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3224 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2941 # number of overall misses +system.l2c.overall_misses::cpu0.inst 48524 # number of overall misses +system.l2c.overall_misses::cpu0.data 594695 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3244 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2893 # number of overall misses +system.l2c.overall_misses::cpu1.inst 34473 # number of overall misses +system.l2c.overall_misses::cpu1.data 577010 # number of overall misses +system.l2c.overall_misses::total 1267004 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 283936 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 148826 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 280662 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 145092 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 858516 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 8916863 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 8916863 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 26043 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 25091 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 51134 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1274242 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1243780 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2518022 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 7166406 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 7109530 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 14275936 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 3938904 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 3906821 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 7845725 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 765655 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 480562 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 1246217 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 284327 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 148672 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 7166406 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 5213146 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 281314 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 146272 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 7109530 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 5150601 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 25500268 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 284327 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 148672 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 7166406 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 5213146 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 281314 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 146272 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 7109530 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 5150601 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 25500268 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019641 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011478 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019901 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.014269 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.778348 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783198 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.780756 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 1269336 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1247641 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 7138684 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 7127088 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 3931284 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 3911547 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 7842831 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 761557 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 485215 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 283936 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 148826 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 7138684 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 5200620 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 280662 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 145092 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 7127088 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 5159188 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 25484096 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 283936 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 148826 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 7138684 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 5200620 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 280662 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 145092 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 7127088 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 5159188 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 25484096 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019761 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019939 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.014329 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.779135 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782711 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.780889 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.327133 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.329959 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.328529 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006815 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004809 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.005816 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045173 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042484 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.043834 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.551670 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.270795 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.443360 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011325 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.019641 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006815 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.114092 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011478 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019901 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004809 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.111904 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049665 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011325 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.019641 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006815 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.114092 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011478 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019901 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004809 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.111904 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049665 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.328645 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.328976 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328809 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006797 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004837 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045159 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042583 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.043874 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.553173 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.269858 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019761 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006797 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.114351 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.019939 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004837 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.111841 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049717 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019761 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006797 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.114351 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.019939 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004837 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.111841 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049717 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1507035 # number of writebacks -system.l2c.writebacks::total 1507035 # number of writebacks -system.membus.snoop_filter.tot_requests 3814231 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1911351 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2893 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 1507087 # number of writebacks +system.l2c.writebacks::total 1507087 # number of writebacks +system.membus.snoop_filter.tot_requests 3814674 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1911370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524759 # Transaction distribution +system.membus.trans_dist::ReadResp 524928 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613666 # Transaction distribution -system.membus.trans_dist::CleanEvict 226120 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40498 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613718 # Transaction distribution +system.membus.trans_dist::CleanEvict 226292 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40499 # Transaction distribution -system.membus.trans_dist::ReadExReq 826686 # Transaction distribution -system.membus.trans_dist::ReadExResp 826686 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448080 # Transaction distribution -system.membus.trans_dist::InvalidateReq 659180 # Transaction distribution -system.membus.trans_dist::InvalidateResp 659180 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40498 # Transaction distribution +system.membus.trans_dist::ReadExReq 827048 # Transaction distribution +system.membus.trans_dist::ReadExResp 827048 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448249 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5533540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5662732 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6009246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5534223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5663415 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6009908 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177661536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 177830586 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7391232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185221818 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177699296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 177868346 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185259130 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3924516 # Request fanout histogram -system.membus.snoop_fanout::mean 0.009389 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.096443 # Request fanout histogram +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 3924959 # Request fanout histogram +system.membus.snoop_fanout::mean 0.009320 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.096090 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3887667 99.06% 99.06% # Request fanout histogram -system.membus.snoop_fanout::1 36849 0.94% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3888378 99.07% 99.07% # Request fanout histogram +system.membus.snoop_fanout::1 36581 0.93% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3924516 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 3924959 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1147,73 +1148,74 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 52432480 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26546586 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1741 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 52404582 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26532237 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 1321968 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23443629 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 1320370 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23428973 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8920157 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 14275419 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2689286 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51144 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8916863 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2689192 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51134 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51145 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2518022 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2518022 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 14275936 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7845725 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1246217 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1246217 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42913541 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35065981 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 831270 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1659308 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 80470100 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1827459220 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234359526 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3325080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6637232 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3071781058 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1762525 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 54939201 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.011226 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105357 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 51135 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7842831 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42883049 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35055805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 830232 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1657150 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 80426236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1233896614 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3320928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6628600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3070004370 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1762480 # Total snoops (count) +system.toL2Bus.snoopTraffic 96494080 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 54910458 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.011218 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105318 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 54322443 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 616758 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 54294485 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 615973 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 54939201 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 54910458 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal index 7a2b5d086..e00102254 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal @@ -77,7 +77,7 @@ [ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.131281] NET: Registered protocol family 1
-[ 3.131310] RPC: Registered named UNIX socket transport module.
+[ 3.131311] RPC: Registered named UNIX socket transport module.
[ 3.131311] RPC: Registered udp transport module.
[ 3.131312] RPC: Registered tcp transport module.
[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
@@ -87,7 +87,7 @@ [ 3.132687] fuse init (API version 7.23)
[ 3.132738] msgmni has been set to 469
[ 3.133992] io scheduler noop registered
-[ 3.134024] io scheduler cfq registered (default)
+[ 3.134025] io scheduler cfq registered (default)
[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
@@ -98,24 +98,24 @@ [ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.134354] pci_bus 0000:00: fixups for bus
[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
+[ 3.134362] pci 0000:00:00.0: fixup irq: got 33
[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
-[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
+[ 3.134366] pci 0000:00:01.0: fixup irq: got 34
[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
@@ -158,9 +158,9 @@ [ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.446951] udevd[607]: starting version 182
+[ 3.446950] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.532266] random: dd urandom read with 19 bits of entropy available
+[ 3.532262] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
|