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Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic')
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini23
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout8
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt30
3 files changed, 35 insertions, 26 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
index 140fedafe..01d4a8b81 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
@@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -28,7 +28,7 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -38,11 +38,12 @@ mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -85,7 +86,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
@@ -341,7 +342,7 @@ eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
-interrupts=Null
+interrupts=
isa=system.cpu1.isa
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
@@ -1402,12 +1403,13 @@ port=3456
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -1415,6 +1417,13 @@ width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
index 6c6535e7f..77c812f3a 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 7 2015 10:13:08
-gem5 started Aug 7 2015 11:28:27
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 06:00:18
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index 4162ec223..2bef0a385 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1150787 # Simulator instruction rate (inst/s)
-host_op_rate 1352364 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59739798990 # Simulator tick rate (ticks/s)
-host_mem_usage 722184 # Number of bytes of host memory used
-host_seconds 855.56 # Real time elapsed on the host
+host_inst_rate 564761 # Simulator instruction rate (inst/s)
+host_op_rate 663687 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29317960092 # Simulator tick rate (ticks/s)
+host_mem_usage 669948 # Number of bytes of host memory used
+host_seconds 1743.34 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -228,9 +228,11 @@ system.cpu0.itb.inst_accesses 493628912 # IT
system.cpu0.itb.hits 493558289 # DTB hits
system.cpu0.itb.misses 70623 # DTB misses
system.cpu0.itb.accesses 493628912 # DTB accesses
-system.cpu0.numCycles 98036734134 # number of cpu cycles simulated
+system.cpu0.numCycles 98036732821 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed
system.cpu0.committedInsts 493343054 # Number of instructions committed
system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses
@@ -248,8 +250,8 @@ system.cpu0.num_cc_register_writes 132723498 # nu
system.cpu0.num_mem_refs 176296730 # number of memory refs
system.cpu0.num_load_insts 91967123 # Number of load instructions
system.cpu0.num_store_insts 84329607 # Number of store instructions
-system.cpu0.num_idle_cycles 96926192639.173721 # Number of idle cycles
-system.cpu0.num_busy_cycles 1110541494.826277 # Number of busy cycles
+system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles
+system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles
system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles
system.cpu0.Branches 110281342 # Number of branches fetched
@@ -288,8 +290,6 @@ system.cpu0.op_class::MemWrite 84329607 14.55% 100.00% # Cl
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 579643698 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 19653 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 11612141 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks.
@@ -612,9 +612,11 @@ system.cpu1.itb.inst_accesses 491545246 # IT
system.cpu1.itb.hits 491475383 # DTB hits
system.cpu1.itb.misses 69863 # DTB misses
system.cpu1.itb.accesses 491545246 # DTB accesses
-system.cpu1.numCycles 97463066094 # number of cpu cycles simulated
+system.cpu1.numCycles 97463064529 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.committedInsts 491227465 # Number of instructions committed
system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses
@@ -632,8 +634,8 @@ system.cpu1.num_cc_register_writes 131105905 # nu
system.cpu1.num_mem_refs 176168876 # number of memory refs
system.cpu1.num_load_insts 92213308 # Number of load instructions
system.cpu1.num_store_insts 83955568 # Number of store instructions
-system.cpu1.num_idle_cycles 96357045557.909821 # Number of idle cycles
-system.cpu1.num_busy_cycles 1106020536.090176 # Number of busy cycles
+system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles
+system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles
system.cpu1.Branches 109807220 # Number of branches fetched
@@ -672,8 +674,6 @@ system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Cl
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 578022895 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution