diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic')
5 files changed, 3195 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini new file mode 100644 index 000000000..7b6dda94d --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini @@ -0,0 +1,1320 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=134217728 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=469827632 +gic_cpu_addr=738205696 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 +kernel_addr_check=true +load_addr_mask=268435455 +load_offset=2147483648 +machine_type=VExpress_EMM64 +mem_mode=atomic +mem_ranges=2147483648:2415919103 +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +width=1 +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=AtomicSimpleCPU +children=dstage2_mmu dtb isa istage2_mmu itb tracer +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=Null +isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=true +system=system +tracer=system.cpu1.tracer +width=1 +workload= + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=1 +frontend_latency=2 +response_latency=2 +use_default_range=true +width=16 +default=system.realview.pciconfig.pio +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=2147483648:2415919103 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[27] +mem_side=system.membus.slave[3] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentXBar +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=2147483648:2415919103 +port=system.membus.master[5] + +[system.realview] +type=RealView +children=aaci_fake cf_ctrl clcd energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +pci_cfg_base=805306368 +pci_cfg_gen_offsets=true +pci_io_base=788529152 +system=system + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470024192 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=471465984 +BAR0LegacyIO=true +BAR0Size=256 +BAR1=471466240 +BAR1LegacyIO=true +BAR1Size=4096 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks= +eventq_index=0 +io_shift=2 +pci_bus=2 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[9] +dma=system.iobus.slave[2] +pio=system.iobus.master[8] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=46 +pio_addr=471793664 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=470286336 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.ethernet] +type=IGbE +BAR0=0 +BAR0LegacyIO=false +BAR0Size=131072 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=0 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=4213 +ExpansionROM=0 +HeaderType=0 +InterruptLine=1 +InterruptPin=1 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=255 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=0 +Revision=0 +Status=0 +SubClassCode=0 +SubsystemID=4104 +SubsystemVendorID=32902 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +eventq_index=0 +fetch_comp_delay=10000 +fetch_delay=10000 +hardware_address=00:90:00:00:00:01 +pci_bus=0 +pci_dev=0 +pci_func=0 +phy_epid=896 +phy_pid=680 +pio_latency=30000 +platform=system.realview +rx_desc_cache_size=64 +rx_fifo_size=393216 +rx_write_delay=0 +system=system +tx_desc_cache_size=64 +tx_fifo_size=393216 +tx_read_delay=0 +wb_comp_delay=10000 +wb_delay=10000 +config=system.iobus.master[26] +dma=system.iobus.slave[4] +pio=system.iobus.master[25] + +[system.realview.generic_timer] +type=GenericTimer +eventq_index=0 +gic=system.realview.gic +int_num=29 +system=system + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=738205696 +cpu_pio_delay=10000 +dist_addr=738201600 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.hdlcd] +type=HDLcd +amba_id=1314816 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=117 +pio_addr=721420288 +pio_latency=10000 +pixel_clock=7299 +system=system +vnc=system.vncserver +dma=system.membus.slave[0] +pio=system.iobus.master[5] + +[system.realview.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=2 +InterruptPin=2 +LatencyTimer=0 +LegacyIOBase=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=0 +disks=system.cf0 +eventq_index=0 +io_shift=0 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[24] +dma=system.iobus.slave[3] +pio=system.iobus.master[23] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=44 +is_mouse=false +pio_addr=470155264 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=45 +is_mouse=true +pio_addr=470220800 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[7] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=739246080 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.realview.lan_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=436207616 +pio_latency=100000 +pio_size=65535 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=738721792 +pio_latency=100000 +system=system +pio=system.membus.master[3] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470089728 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:67108863 +port=system.membus.master[1] + +[system.realview.pciconfig] +type=PciConfigAll +bus=0 +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=0 +pio_latency=30000 +platform=system.realview +size=268435456 +system=system +pio=system.iobus.default + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=35979264 +pio_addr=469827584 +pio_latency=100000 +proc_id0=335544320 +proc_id1=335544320 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=36 +pio_addr=471269376 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[10] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=469893120 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=34 +int_num1=34 +pio_addr=470876160 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=35 +int_num1=35 +pio_addr=470941696 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=37 +pio_addr=470351872 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470417408 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470482944 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470548480 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.realview.usb_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=452984832 +pio_latency=100000 +pio_size=131071 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.realview.vgic] +type=VGic +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +hv_addr=738213888 +pio_delay=10000 +platform=system.realview +ppint=25 +system=system +vcpu_addr=738222080 +pio=system.membus.master[4] + +[system.realview.vram] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=402653184:436207615 +port=system.iobus.master[11] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=470745088 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr new file mode 100644 index 000000000..3137dc2c1 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr @@ -0,0 +1,570 @@ +warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 +warn: Tried to read RealView I/O at offset 0x60 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout new file mode 100644 index 000000000..3cdd0b0b9 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 29 2014 15:46:15 +gem5 started Oct 29 2014 16:13:02 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic +Selected 64-bit ARM architecture, updating default disk image... +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0.isa: ISA system set to: 0x5318b00 0x5318b00 + 0: system.cpu1.isa: ISA system set to: 0x5318b00 0x5318b00 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt new file mode 100644 index 000000000..f36b7859c --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -0,0 +1,1111 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.111153 # Number of seconds simulated +sim_ticks 51111152682000 # Number of ticks simulated +final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1095499 # Simulator instruction rate (inst/s) +host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56869697369 # Simulator tick rate (ticks/s) +host_mem_usage 728040 # Number of bytes of host memory used +host_seconds 898.74 # Real time elapsed on the host +sim_insts 984570519 # Number of instructions simulated +sim_ops 1157031967 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory +system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 144734 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 91873100 # DTB read hits +system.cpu0.dtb.read_misses 107254 # DTB read misses +system.cpu0.dtb.write_hits 84300346 # DTB write hits +system.cpu0.dtb.write_misses 37480 # DTB write misses +system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91980354 # DTB read accesses +system.cpu0.dtb.write_accesses 84337826 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 176173446 # DTB hits +system.cpu0.dtb.misses 144734 # DTB misses +system.cpu0.dtb.accesses 176318180 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 70623 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 493558289 # ITB inst hits +system.cpu0.itb.inst_misses 70623 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses +system.cpu0.itb.hits 493558289 # DTB hits +system.cpu0.itb.misses 70623 # DTB misses +system.cpu0.itb.accesses 493628912 # DTB accesses +system.cpu0.numCycles 98036732821 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 493343054 # Number of instructions committed +system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses +system.cpu0.num_func_calls 28504103 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls +system.cpu0.num_int_insts 530703417 # number of integer instructions +system.cpu0.num_fp_insts 453665 # number of float instructions +system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read +system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written +system.cpu0.num_mem_refs 176296730 # number of memory refs +system.cpu0.num_load_insts 91967123 # Number of load instructions +system.cpu0.num_store_insts 84329607 # Number of store instructions +system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles +system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles +system.cpu0.Branches 110281342 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 402074699 69.37% 69.37% # Class of executed instruction +system.cpu0.op_class::IntMult 1168928 0.20% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 50558 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52783 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::MemRead 91967123 15.87% 85.45% # Class of executed instruction +system.cpu0.op_class::MemWrite 84329607 14.55% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 579643698 # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 11612141 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.345192 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 264.268132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 247.731587 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.516149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.483851 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 1421165468 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1421165468 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 85681160 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 85885886 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 171567046 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79835128 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 79687740 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 159522868 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208530 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215328 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 423858 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146037 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191672 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2127418 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2183031 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 4310449 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2250403 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2312061 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165516288 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 165573626 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 331089914 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165724818 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 165788954 # number of overall hits +system.cpu0.dcache.overall_hits::total 331513772 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3015225 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2995068 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6010293 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1305618 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1264641 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2570259 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 792908 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 791180 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1584088 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 765143 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 480206 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 123898 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 129919 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 253817 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4320843 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 4259709 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 8580552 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5113751 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 5050889 # number of overall misses +system.cpu0.dcache.overall_misses::total 10164640 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88696385 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 88880954 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81140746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 80952381 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1001438 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1006508 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 2007946 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 911180 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 671878 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2251316 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2312950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2250403 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2312062 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169837131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 169833335 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170838569 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 170839843 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 341678412 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033995 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033698 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033846 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016091 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015622 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791769 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786064 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788910 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055034 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056170 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055610 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025441 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025082 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029933 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029565 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 8921315 # number of writebacks +system.cpu0.dcache.writebacks::total 8921315 # number of writebacks +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 14295641 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 970865862 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.250565 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.734034 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523927 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476043 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 999458178 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 999458178 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 486466334 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 484399528 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 970865862 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 486466334 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 484399528 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 970865862 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 486466334 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 484399528 # number of overall hits +system.cpu0.icache.overall_hits::total 970865862 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7156510 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7139648 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14296158 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7156510 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7139648 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14296158 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7156510 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7139648 # number of overall misses +system.cpu0.icache.overall_misses::total 14296158 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 493622844 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 491539176 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 493622844 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 491539176 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 493622844 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 491539176 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014498 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014525 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014498 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014525 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014498 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014525 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 143589 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 92120843 # DTB read hits +system.cpu1.dtb.read_misses 106565 # DTB read misses +system.cpu1.dtb.write_hits 83929435 # DTB write hits +system.cpu1.dtb.write_misses 37024 # DTB write misses +system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 4753 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92227408 # DTB read accesses +system.cpu1.dtb.write_accesses 83966459 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 176050278 # DTB hits +system.cpu1.dtb.misses 143589 # DTB misses +system.cpu1.dtb.accesses 176193867 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 69863 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 491475383 # ITB inst hits +system.cpu1.itb.inst_misses 69863 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses +system.cpu1.itb.hits 491475383 # DTB hits +system.cpu1.itb.misses 69863 # DTB misses +system.cpu1.itb.accesses 491545246 # DTB accesses +system.cpu1.numCycles 97463064529 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 491227465 # Number of instructions committed +system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses +system.cpu1.num_func_calls 28552264 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls +system.cpu1.num_int_insts 529752049 # number of integer instructions +system.cpu1.num_fp_insts 427140 # number of float instructions +system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read +system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written +system.cpu1.num_mem_refs 176168876 # number of memory refs +system.cpu1.num_load_insts 92213308 # Number of load instructions +system.cpu1.num_store_insts 83955568 # Number of store instructions +system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles +system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles +system.cpu1.Branches 109807220 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction +system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction +system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 578022895 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iobus.trans_dist::ReadReq 40246 # Transaction distribution +system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.iobus.trans_dist::WriteReq 136515 # Transaction distribution +system.iobus.trans_dist::WriteResp 29851 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115463 # number of replacements +system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1039686 # Number of tag accesses +system.iocache.tags.data_accesses 1039686 # Number of data accesses +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses +system.iocache.demand_misses::total 8857 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8817 # number of overall misses +system.iocache.overall_misses::total 8857 # number of overall misses +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 1722682 # number of replacements +system.l2c.tags.tagsinuse 65341.862498 # Cycle average of tags in use +system.l2c.tags.total_refs 30065488 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1785979 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 16.834178 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37141.097811 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.495240 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3601.604762 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9619.799415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.654107 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240500 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2659.657984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11566.852019 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.566728 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002387 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003715 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.054956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002314 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003071 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.176496 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 63021 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 276 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54671 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.961624 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 290964090 # Number of tag accesses +system.l2c.tags.data_accesses 290964090 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7107195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3754972 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 142760 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 7104726 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3749259 # number of ReadReq hits +system.l2c.ReadReq_hits::total 22560458 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8921315 # number of Writeback hits +system.l2c.Writeback_hits::total 8921315 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 345123 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 349209 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 694332 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 5687 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5536 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11223 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 864873 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 827736 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1692609 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 279435 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 145257 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7107195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4619845 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 276854 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 142760 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7104726 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4576995 # number of demand (read+write) hits +system.l2c.demand_hits::total 24253067 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 279435 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 145257 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7107195 # number of overall hits +system.l2c.overall_hits::cpu0.data 4619845 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 276854 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 142760 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7104726 # number of overall hits +system.l2c.overall_hits::cpu1.data 4576995 # number of overall hits +system.l2c.overall_hits::total 24253067 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3178 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2937 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 49315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 177059 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3256 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2942 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 34922 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 166908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 440517 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 420020 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 130997 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 551017 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 19994 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19925 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 39919 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 415064 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 411444 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 826508 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3178 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2937 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 49315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 592123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3256 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2942 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34922 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 578352 # number of demand (read+write) misses +system.l2c.demand_misses::total 1267025 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3178 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2937 # number of overall misses +system.l2c.overall_misses::cpu0.inst 49315 # number of overall misses +system.l2c.overall_misses::cpu0.data 592123 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3256 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2942 # number of overall misses +system.l2c.overall_misses::cpu1.inst 34922 # number of overall misses +system.l2c.overall_misses::cpu1.data 578352 # number of overall misses +system.l2c.overall_misses::total 1267025 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 282613 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 148194 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 7156510 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 3932031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 280110 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 145702 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 7139648 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 3916167 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 23000975 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 765143 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 480206 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25681 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 25461 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 51142 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1279937 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1239180 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 282613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 148194 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 7156510 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 5211968 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 280110 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 145702 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 7139648 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 5155347 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 25520092 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 282613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 148194 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 7156510 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 5211968 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 280110 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 145702 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 7139648 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 5155347 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 25520092 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019819 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.006891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045030 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020192 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.042620 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.548943 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.272793 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.442460 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.778552 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.324285 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.332029 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.113608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.020192 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112185 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049648 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.113608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.020192 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112185 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049648 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 1503417 # number of writebacks +system.l2c.writebacks::total 1503417 # number of writebacks +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 526050 # Transaction distribution +system.membus.trans_dist::ReadResp 526050 # Transaction distribution +system.membus.trans_dist::WriteReq 33606 # Transaction distribution +system.membus.trans_dist::WriteResp 33606 # Transaction distribution +system.membus.trans_dist::Writeback 1610048 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 657676 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 657676 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution +system.membus.trans_dist::ReadExReq 825949 # Transaction distribution +system.membus.trans_dist::ReadExResp 825949 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5310719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5439911 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5777584 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212730400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 212899450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3583531 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3583531 # Request fanout histogram +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 116338 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal new file mode 100644 index 000000000..a8a62831d --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal @@ -0,0 +1,183 @@ +[ 0.000000] Initializing cgroup subsys cpu
+[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
+[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
+[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
+[ 0.000000] Memory limited to 256MB
+[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
+[ 0.000000] On node 0 totalpages: 65536
+[ 0.000000] DMA zone: 896 pages used for memmap
+[ 0.000000] DMA zone: 0 pages reserved
+[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
+[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
+[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
+[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
+[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
+[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
+[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
+[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
+[ 0.000000] Virtual kernel memory layout:
+[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
+[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
+[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
+[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
+[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
+[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
+[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] Preemptible hierarchical RCU implementation.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+[ 0.000000] NR_IRQS:64 nr_irqs:64 0
+[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
+[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
+[ 0.000013] Console: colour dummy device 80x25
+[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000015] pid_max: default: 32768 minimum: 301
+[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000066] hw perfevents: no hardware support available
+[ 1.060049] CPU1: failed to come online
+[ 2.080098] CPU2: failed to come online
+[ 3.100148] CPU3: failed to come online
+[ 3.100150] Brought up 1 CPUs
+[ 3.100151] SMP: Total of 1 processors activated.
+[ 3.100177] devtmpfs: initialized
+[ 3.100579] atomic64_test: passed
+[ 3.100603] regulator-dummy: no parameters
+[ 3.100844] NET: Registered protocol family 16
+[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.100981] Serial: AMBA PL011 UART driver
+[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.101160] console [ttyAMA0] enabled
+[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130356] 3V3: 3300 mV
+[ 3.130377] vgaarb: loaded
+[ 3.130406] SCSI subsystem initialized
+[ 3.130425] libata version 3.00 loaded.
+[ 3.130450] usbcore: registered new interface driver usbfs
+[ 3.130457] usbcore: registered new interface driver hub
+[ 3.130471] usbcore: registered new device driver usb
+[ 3.130482] pps_core: LinuxPPS API ver. 1 registered
+[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.130487] PTP clock support registered
+[ 3.130559] Switched to clocksource arch_sys_counter
+[ 3.131204] NET: Registered protocol family 2
+[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.131263] TCP: reno registered
+[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.131281] NET: Registered protocol family 1
+[ 3.131310] RPC: Registered named UNIX socket transport module.
+[ 3.131311] RPC: Registered udp transport module.
+[ 3.131312] RPC: Registered tcp transport module.
+[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.131315] PCI: CLS 0 bytes, default 64
+[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.132687] fuse init (API version 7.23)
+[ 3.132738] msgmni has been set to 469
+[ 3.133992] io scheduler noop registered
+[ 3.134024] io scheduler cfq registered (default)
+[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.134302] pci_bus 0000:00: scanning bus
+[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.134354] pci_bus 0000:00: fixups for bus
+[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
+[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
+[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
+[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
+[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
+[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.134813] ata_piix 0000:00:01.0: version 2.13
+[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.135009] scsi0 : ata_piix
+[ 3.135063] scsi1 : ata_piix
+[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.135150] e1000 0000:00:00.0: enabling bus mastering
+[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.290572] ata1.00: configured for UDMA/33
+[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.290733] sda: sda1
+[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.410886] usbcore: registered new interface driver usb-storage
+[ 3.410912] mousedev: PS/2 mouse device common for all mice
+[ 3.411009] usbcore: registered new interface driver usbhid
+[ 3.411010] usbhid: USB HID core driver
+[ 3.411025] TCP: cubic registered
+[ 3.411026] NET: Registered protocol family 17
+ +[ 3.411214] devtmpfs: mounted
+[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+ + +[ 3.446950] udevd[607]: starting version 182
+Starting Bootlog daemon: bootlogd.
+[ 3.532262] random: dd urandom read with 19 bits of entropy available
+Populating dev cache
+net.ipv4.conf.default.rp_filter = 1
+net.ipv4.conf.all.rp_filter = 1
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+Mon Jan 27 08:00:00 UTC 2014
+hwclock: can't open '/dev/misc/rtc': No such file or directory
+
INIT: Entering runlevel: 5
+Configuring network interfaces... udhcpc (v1.21.1) started
+[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Sending discover...
+Sending discover...
+Sending discover...
+No lease, forking to background
+done.
+Starting rpcbind daemon...rpcbind: cannot create socket for udp6
+rpcbind: cannot create socket for tcp6
+done.
+rpcbind: cannot get uid of '': Success
+creating NFS state directory: done
+starting statd: done
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