diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt | 5305 |
1 files changed, 2648 insertions, 2657 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index 1b1aa2e1b..d8c58ee0c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,194 +1,194 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.278333 # Number of seconds simulated -sim_ticks 51278333141000 # Number of ticks simulated -final_tick 51278333141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.316243 # Number of seconds simulated +sim_ticks 51316242679000 # Number of ticks simulated +final_tick 51316242679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 300545 # Simulator instruction rate (inst/s) -host_op_rate 353177 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18121485754 # Simulator tick rate (ticks/s) -host_mem_usage 688280 # Number of bytes of host memory used -host_seconds 2829.70 # Real time elapsed on the host -sim_insts 850450745 # Number of instructions simulated -sim_ops 999383448 # Number of ops (including micro ops) simulated +host_inst_rate 361668 # Simulator instruction rate (inst/s) +host_op_rate 424976 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21619129427 # Simulator tick rate (ticks/s) +host_mem_usage 686216 # Number of bytes of host memory used +host_seconds 2373.65 # Real time elapsed on the host +sim_insts 858473131 # Number of instructions simulated +sim_ops 1008744567 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 82048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 86080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2553908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 18749896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 26560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 25408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 451200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4994624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 34432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 29952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1461952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 6681856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 70784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 53120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1684864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 11657408 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 398592 # Number of bytes read from this memory -system.physmem.bytes_read::total 49042684 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2553908 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 451200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1461952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1684864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6151924 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68500992 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 84032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 93120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2529588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19493128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 22656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 23808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 606400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5209600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 35264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 30848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1545600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 6997952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 75392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 63744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1527168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 11329792 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 446016 # Number of bytes read from this memory +system.physmem.bytes_read::total 50114108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2529588 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 606400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1545600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1527168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6208756 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69736384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68521572 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1282 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1345 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 80312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 292980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 415 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 78041 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 22843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 104404 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 830 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 26326 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 182147 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6228 # Number of read requests responded to by this memory -system.physmem.num_reads::total 806712 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1070328 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69756964 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 79932 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 304593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 354 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 551 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 482 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 24150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 109343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1178 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 996 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 23862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 177028 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 823453 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1089631 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1072901 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 49805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 365649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 97402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 28510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 130306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 32857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 227336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 956402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 49805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8799 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 28510 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 32857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 119971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1335866 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1092204 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 49294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 379863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 101520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 30119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 136369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 29760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 220784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 976574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 49294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 30119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 29760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 120990 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1358953 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1336268 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1335866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 49805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 366051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 97402 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 28510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 130306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 32857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 227336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2292669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 428538 # Number of read requests accepted -system.physmem.writeReqs 456847 # Number of write requests accepted -system.physmem.readBursts 428538 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 456847 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27408320 # Total number of bytes read from DRAM +system.physmem.bw_write::total 1359354 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1358953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 49294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 380264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 101520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 30119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 136369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 29760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 220784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2335928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 433905 # Number of read requests accepted +system.physmem.writeReqs 477158 # Number of write requests accepted +system.physmem.readBursts 433905 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 477158 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27751808 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue -system.physmem.bytesWritten 29236416 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27426432 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 29238208 # Total written bytes from the system interface side +system.physmem.bytesWritten 30536384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27769920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 30538112 # Total written bytes from the system interface side system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26649 # Per bank write bursts -system.physmem.perBankRdBursts::1 30049 # Per bank write bursts -system.physmem.perBankRdBursts::2 26532 # Per bank write bursts -system.physmem.perBankRdBursts::3 25500 # Per bank write bursts -system.physmem.perBankRdBursts::4 26079 # Per bank write bursts -system.physmem.perBankRdBursts::5 32966 # Per bank write bursts -system.physmem.perBankRdBursts::6 25199 # Per bank write bursts -system.physmem.perBankRdBursts::7 25237 # Per bank write bursts -system.physmem.perBankRdBursts::8 24838 # Per bank write bursts -system.physmem.perBankRdBursts::9 28373 # Per bank write bursts -system.physmem.perBankRdBursts::10 26870 # Per bank write bursts -system.physmem.perBankRdBursts::11 27983 # Per bank write bursts -system.physmem.perBankRdBursts::12 26309 # Per bank write bursts -system.physmem.perBankRdBursts::13 25787 # Per bank write bursts -system.physmem.perBankRdBursts::14 24479 # Per bank write bursts -system.physmem.perBankRdBursts::15 25405 # Per bank write bursts -system.physmem.perBankWrBursts::0 27847 # Per bank write bursts -system.physmem.perBankWrBursts::1 29934 # Per bank write bursts -system.physmem.perBankWrBursts::2 27360 # Per bank write bursts -system.physmem.perBankWrBursts::3 28363 # Per bank write bursts -system.physmem.perBankWrBursts::4 28817 # Per bank write bursts -system.physmem.perBankWrBursts::5 32577 # Per bank write bursts -system.physmem.perBankWrBursts::6 27869 # Per bank write bursts -system.physmem.perBankWrBursts::7 28879 # Per bank write bursts -system.physmem.perBankWrBursts::8 27745 # Per bank write bursts -system.physmem.perBankWrBursts::9 30902 # Per bank write bursts -system.physmem.perBankWrBursts::10 28100 # Per bank write bursts -system.physmem.perBankWrBursts::11 29746 # Per bank write bursts -system.physmem.perBankWrBursts::12 27536 # Per bank write bursts -system.physmem.perBankWrBursts::13 27471 # Per bank write bursts -system.physmem.perBankWrBursts::14 26272 # Per bank write bursts -system.physmem.perBankWrBursts::15 27401 # Per bank write bursts +system.physmem.perBankRdBursts::0 27002 # Per bank write bursts +system.physmem.perBankRdBursts::1 28908 # Per bank write bursts +system.physmem.perBankRdBursts::2 27684 # Per bank write bursts +system.physmem.perBankRdBursts::3 26367 # Per bank write bursts +system.physmem.perBankRdBursts::4 27601 # Per bank write bursts +system.physmem.perBankRdBursts::5 30822 # Per bank write bursts +system.physmem.perBankRdBursts::6 24976 # Per bank write bursts +system.physmem.perBankRdBursts::7 26194 # Per bank write bursts +system.physmem.perBankRdBursts::8 25034 # Per bank write bursts +system.physmem.perBankRdBursts::9 29693 # Per bank write bursts +system.physmem.perBankRdBursts::10 29082 # Per bank write bursts +system.physmem.perBankRdBursts::11 28850 # Per bank write bursts +system.physmem.perBankRdBursts::12 25459 # Per bank write bursts +system.physmem.perBankRdBursts::13 26397 # Per bank write bursts +system.physmem.perBankRdBursts::14 23675 # Per bank write bursts +system.physmem.perBankRdBursts::15 25878 # Per bank write bursts +system.physmem.perBankWrBursts::0 28116 # Per bank write bursts +system.physmem.perBankWrBursts::1 30181 # Per bank write bursts +system.physmem.perBankWrBursts::2 29513 # Per bank write bursts +system.physmem.perBankWrBursts::3 29673 # Per bank write bursts +system.physmem.perBankWrBursts::4 30639 # Per bank write bursts +system.physmem.perBankWrBursts::5 33377 # Per bank write bursts +system.physmem.perBankWrBursts::6 28958 # Per bank write bursts +system.physmem.perBankWrBursts::7 30258 # Per bank write bursts +system.physmem.perBankWrBursts::8 28970 # Per bank write bursts +system.physmem.perBankWrBursts::9 32487 # Per bank write bursts +system.physmem.perBankWrBursts::10 30224 # Per bank write bursts +system.physmem.perBankWrBursts::11 30351 # Per bank write bursts +system.physmem.perBankWrBursts::12 28039 # Per bank write bursts +system.physmem.perBankWrBursts::13 29604 # Per bank write bursts +system.physmem.perBankWrBursts::14 27578 # Per bank write bursts +system.physmem.perBankWrBursts::15 29163 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 51277332920000 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 51315242398500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 428538 # Read request sizes (log2) +system.physmem.readPktSize::6 433905 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 456847 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 325583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20024 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 101 # 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What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -198,219 +198,205 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 10375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 21178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 22558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 25424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 25687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 25579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 25980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 26739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 26656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 28436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 27753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 28091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 29858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 26497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 25503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 60 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 267354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 211.869985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.094359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 252.014491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 129551 48.46% 48.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 69661 26.06% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 23971 8.97% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11874 4.44% 87.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7889 2.95% 90.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4786 1.79% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3806 1.42% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2811 1.05% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13005 4.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 267354 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 24743 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.307279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 12.628838 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-31 23085 93.30% 93.30% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-63 1534 6.20% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-95 94 0.38% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-127 12 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-159 6 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::160-191 2 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::192-223 2 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::224-255 1 0.00% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-287 2 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::288-319 1 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::320-351 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-415 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-543 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-671 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 24743 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 24743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.462555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.679981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.466510 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 17 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 18 0.07% 0.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 7 0.03% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 50 0.20% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 22406 90.55% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1021 4.13% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 245 0.99% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 205 0.83% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 59 0.24% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 45 0.18% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 91 0.37% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.08% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 158 0.64% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 47 0.19% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 11 0.04% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 29 0.12% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 119 0.48% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.07% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 15 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 48 0.19% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 83 0.34% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 24743 # Writes before turning the bus around for reads -system.physmem.totQLat 8299247161 # Total ticks spent queuing -system.physmem.totMemAccLat 16329028411 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2141275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19379.22 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 10672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 21143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 23364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 25817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 26681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 27418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 27969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 29149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 29101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 30529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 31266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 29270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 28851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 29534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 26977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 26434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 25831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 269447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216.323596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.007957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.795343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 129144 47.93% 47.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 70137 26.03% 73.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24147 8.96% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12093 4.49% 87.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8137 3.02% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4947 1.84% 92.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4006 1.49% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2935 1.09% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13901 5.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 269447 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 25551 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.968847 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 13.943536 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-31 23836 93.29% 93.29% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-63 1606 6.29% 99.57% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-95 93 0.36% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-127 3 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-159 4 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::192-223 1 0.00% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-287 1 0.00% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::352-383 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-415 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::416-447 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::448-479 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::704-735 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::928-959 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 25551 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 25551 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.673672 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.805610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.967409 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 31 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 43 0.17% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 23775 93.05% 93.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 652 2.55% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 518 2.03% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 117 0.46% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 66 0.26% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 48 0.19% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 173 0.68% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 30 0.12% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 11 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 7 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 8 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 9 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 10 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 6 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 4 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-359 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 25551 # Writes before turning the bus around for reads +system.physmem.totQLat 8250184127 # Total ticks spent queuing +system.physmem.totMemAccLat 16380596627 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2168110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19026.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38129.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.53 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37776.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 5.79 # Average write queue length when enqueuing -system.physmem.readRowHits 313353 # Number of row buffer hits during reads -system.physmem.writeRowHits 304365 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.62 # Row buffer hit rate for writes -system.physmem.avgGap 57915294.39 # Average gap between requests -system.physmem.pageHitRate 69.79 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1033164720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 562076625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1701999000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1501066080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3310356385440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1179927426690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30447593029500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34942675148055 # Total energy per rank (pJ) -system.physmem_0.averagePower 665.942257 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48866965519857 # Time in different power states -system.physmem_0.memoryStateTime::REF 1692411240000 # Time in different power states +system.physmem.avgWrQLen 7.94 # Average write queue length when enqueuing +system.physmem.readRowHits 319229 # Number of row buffer hits during reads +system.physmem.writeRowHits 322075 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.50 # Row buffer hit rate for writes +system.physmem.avgGap 56324581.72 # Average gap between requests +system.physmem.pageHitRate 70.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1046092320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 569142750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1712513400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1559833200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3312965298240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1175245195320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29690777078250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34183875153480 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.616999 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48913778839190 # Time in different power states +system.physmem_0.memoryStateTime::REF 1693745040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 123966214393 # Time in different power states +system.physmem_0.memoryStateTime::ACT 115773933810 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 988031520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 537520500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1638335400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1459121040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3310356385440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1177251222825 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29686423716000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34178654332725 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.571395 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48870902891583 # Time in different power states -system.physmem_1.memoryStateTime::REF 1692411240000 # Time in different power states +system.physmem_1.actEnergy 990927000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 539141625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1669683600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1531975680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3312965298240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1172482833105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29689600432500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34179780291750 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.615252 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48917806002648 # Time in different power states +system.physmem_1.memoryStateTime::REF 1693745040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120022768167 # Time in different power states +system.physmem_1.memoryStateTime::ACT 111730336352 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -447,47 +433,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 90231 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 90231 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 90231 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 90231 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 90231 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 388941119992 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.527073 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -205000507008 -52.71% -52.71% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 593941627000 152.71% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 388941119992 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 65649 84.67% 84.67% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11889 15.33% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 77538 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90231 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 91119 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 91119 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 91119 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 91119 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 91119 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 392500671624 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.508107 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -199432260126 -50.81% -50.81% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 591932931750 150.81% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 392500671624 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66569 84.97% 84.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11779 15.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 78348 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91119 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90231 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77538 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91119 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78348 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77538 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 167769 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78348 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 169467 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64940650 # DTB read hits -system.cpu0.dtb.read_misses 68234 # DTB read misses -system.cpu0.dtb.write_hits 59349095 # DTB write hits -system.cpu0.dtb.write_misses 21997 # DTB write misses -system.cpu0.dtb.flush_tlb 1197 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 64520896 # DTB read hits +system.cpu0.dtb.read_misses 69076 # DTB read misses +system.cpu0.dtb.write_hits 58341415 # DTB write hits +system.cpu0.dtb.write_misses 22043 # DTB write misses +system.cpu0.dtb.flush_tlb 1192 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16324 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40980 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41149 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2794 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2806 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7599 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 65008884 # DTB read accesses -system.cpu0.dtb.write_accesses 59371092 # DTB write accesses +system.cpu0.dtb.perms_faults 7502 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64589972 # DTB read accesses +system.cpu0.dtb.write_accesses 58363458 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 124289745 # DTB hits -system.cpu0.dtb.misses 90231 # DTB misses -system.cpu0.dtb.accesses 124379976 # DTB accesses +system.cpu0.dtb.hits 122862311 # DTB hits +system.cpu0.dtb.misses 91119 # DTB misses +system.cpu0.dtb.accesses 122953430 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -517,686 +503,684 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 52885 # Table walker walks requested -system.cpu0.itb.walker.walksLong 52885 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 52885 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 52885 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 52885 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 388941119992 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.527164 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -205035740008 -52.72% -52.72% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 593976860000 152.72% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 388941119992 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 45865 94.85% 94.85% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2491 5.15% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 48356 # Table walker page sizes translated +system.cpu0.itb.walker.walks 53727 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53727 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 53727 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53727 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53727 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 392500671624 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.508219 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -199476179626 -50.82% -50.82% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 591976851250 150.82% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 392500671624 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46661 94.95% 94.95% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2481 5.05% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 49142 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52885 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52885 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53727 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53727 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48356 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48356 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 101241 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 347148099 # ITB inst hits -system.cpu0.itb.inst_misses 52885 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49142 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49142 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 102869 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 342517055 # ITB inst hits +system.cpu0.itb.inst_misses 53727 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1197 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1192 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16324 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28527 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16238 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 399 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28999 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 347200984 # ITB inst accesses -system.cpu0.itb.hits 347148099 # DTB hits -system.cpu0.itb.misses 52885 # DTB misses -system.cpu0.itb.accesses 347200984 # DTB accesses -system.cpu0.numCycles 418851699 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 342570782 # ITB inst accesses +system.cpu0.itb.hits 342517055 # DTB hits +system.cpu0.itb.misses 53727 # DTB misses +system.cpu0.itb.accesses 342570782 # DTB accesses +system.cpu0.numCycles 413468946 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16522 # number of quiesce instructions executed -system.cpu0.committedInsts 347002044 # Number of instructions committed -system.cpu0.committedOps 408295196 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 375110913 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 357489 # Number of float alu accesses -system.cpu0.num_func_calls 20952666 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 52632755 # number of instructions that are conditional controls -system.cpu0.num_int_insts 375110913 # number of integer instructions -system.cpu0.num_fp_insts 357489 # number of float instructions -system.cpu0.num_int_register_reads 548276980 # number of times the integer registers were read -system.cpu0.num_int_register_writes 297820090 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 571479 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 314936 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 90391371 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 90175878 # number of times the CC registers were written -system.cpu0.num_mem_refs 124362861 # number of memory refs -system.cpu0.num_load_insts 64997668 # Number of load instructions -system.cpu0.num_store_insts 59365193 # Number of store instructions -system.cpu0.num_idle_cycles 408653989.262248 # Number of idle cycles -system.cpu0.num_busy_cycles 10197709.737752 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024347 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975653 # Percentage of idle cycles -system.cpu0.Branches 77385391 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16570 # number of quiesce instructions executed +system.cpu0.committedInsts 342362794 # Number of instructions committed +system.cpu0.committedOps 402636690 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 369953687 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 353210 # Number of float alu accesses +system.cpu0.num_func_calls 20646613 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 51970284 # number of instructions that are conditional controls +system.cpu0.num_int_insts 369953687 # number of integer instructions +system.cpu0.num_fp_insts 353210 # number of float instructions +system.cpu0.num_int_register_reads 539846960 # number of times the integer registers were read +system.cpu0.num_int_register_writes 293703337 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 568892 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 300360 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 89273277 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89056803 # number of times the CC registers were written +system.cpu0.num_mem_refs 122937235 # number of memory refs +system.cpu0.num_load_insts 64579480 # Number of load instructions +system.cpu0.num_store_insts 58357755 # Number of store instructions +system.cpu0.num_idle_cycles 403595961.081611 # Number of idle cycles +system.cpu0.num_busy_cycles 9872984.918389 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023878 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976122 # Percentage of idle cycles +system.cpu0.Branches 76352356 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 283178336 69.32% 69.32% # Class of executed instruction -system.cpu0.op_class::IntMult 901174 0.22% 69.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 41440 0.01% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 48921 0.01% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::MemRead 64997668 15.91% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 59365193 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 278960942 69.24% 69.24% # Class of executed instruction +system.cpu0.op_class::IntMult 898467 0.22% 69.46% # Class of executed instruction +system.cpu0.op_class::IntDiv 41470 0.01% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 45104 0.01% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::MemRead 64579480 16.03% 85.51% # Class of executed instruction +system.cpu0.op_class::MemWrite 58357755 14.49% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 408532732 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9687552 # number of replacements +system.cpu0.op_class::total 402883218 # Class of executed instruction +system.cpu0.dcache.tags.replacements 9811129 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 293952506 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9688064 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.341718 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 296592840 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9811641 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.228668 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.138446 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.125391 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.691064 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.044815 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970974 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010011 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009162 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.009853 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.870770 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.381737 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.192700 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 6.554509 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968498 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008558 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010142 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.012802 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1245495121 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1245495121 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 60779853 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 18961352 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26111596 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 45441324 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 151294125 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 56143457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17475743 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 23187165 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 37961445 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134767810 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 158913 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47173 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 75137 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 114608 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395831 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 129155 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44895 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 57683 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 97740 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 329473 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1454318 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 433667 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 579314 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 933829 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3401128 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1544855 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 472149 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 627026 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1076109 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3720139 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 117052465 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 36481990 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 49356444 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 83500509 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 286391408 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 117211378 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 36529163 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 49431581 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 83615117 # number of overall hits -system.cpu0.dcache.overall_hits::total 286787239 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2029256 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 653198 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 985570 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3497352 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7165376 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 851964 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 257580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 600165 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 3409601 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5119310 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 471821 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 150396 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 207281 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 345345 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1174843 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 677444 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 112505 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 152358 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 284476 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1226783 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 91274 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38716 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47958 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 178987 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 356935 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1076112 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3720144 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 120611129 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 37505273 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 51094537 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 90691938 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 299902877 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 121241863 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 37702842 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 51376955 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 91151891 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 301473551 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032308 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033302 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036372 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071464 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.045219 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014948 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014525 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.025230 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.082415 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.036596 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.748051 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.761233 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.733951 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.750827 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.747987 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839877 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714771 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.725373 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.744281 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788291 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059054 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081959 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076455 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.160842 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094978 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029505 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027284 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.034017 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.079295 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.045053 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033243 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.031130 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.037865 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.082684 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048715 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16780.375170 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17365.542275 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17492.261860 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12456.075159 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37558.061573 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37869.803304 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34877.977076 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29559.124475 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24692.155904 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 25016.704079 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 27541.131596 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 11757.806354 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14687.855150 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14893.928020 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13374.800963 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10301.185090 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 36333.333333 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21800 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22880.380110 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25116.367766 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26132.688436 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18872.785814 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19948.473134 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22440.200702 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24935.253925 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17363.042571 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 13201195 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 42765 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 880108 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 406 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.999517 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 105.332512 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 7502187 # number of writebacks -system.cpu0.dcache.writebacks::total 7502187 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3304 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 129070 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1937801 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2070175 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4910 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 266090 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2829152 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3100152 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 34 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2050 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2084 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8564 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10548 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 110240 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 129352 # 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number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 252670 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 334075 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 580449 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1167194 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 150015 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 204632 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 338269 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 692916 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 112505 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 152324 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 282426 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 547255 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 30152 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 37410 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 68747 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136309 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 1015069 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 1342899 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 2422426 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4780394 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1165084 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 1547531 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 2760695 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5473310 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6276 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6461 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 6522 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19259 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5881 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5970 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6236 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18087 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 12157 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12431 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 12758 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 37346 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10091751000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 13620756000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 26803792500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50516299500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9207058000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 12098027000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 21802435152 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 43107520152 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 3089558000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 4271039000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6719235000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14079832000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2665486000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 3657832500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 7405729452 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 13729047952 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 402292000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 498531000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 981967500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1882790500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 106000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 106000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 21964295000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 29376615500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 56011957104 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 107352867604 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 25053853000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 33647654500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 62731192104 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 121432699604 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1244510500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1253007000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1222915500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3720433000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1244510500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1253007000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1222915500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3720433000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033133 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031608 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031867 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019348 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014248 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014044 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014030 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008344 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759304 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.724571 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.735443 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.441158 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714771 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.725211 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.738917 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.351648 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063830 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.059639 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061778 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036271 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026283 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026710 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015940 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.030902 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030121 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.030287 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018155 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15528.303077 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15902.809107 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17186.865002 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16476.583729 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36439.062809 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36213.505949 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37561.327786 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36932.609448 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20594.993834 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20871.804019 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19863.584898 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20319.680885 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23692.155904 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 24013.500827 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 26221.840241 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 25087.112867 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13342.133192 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13326.142743 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14283.786929 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.664608 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 35333.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35333.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21638.228534 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21875.521167 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 23122.257235 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22456.907862 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21503.902723 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21742.798367 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22722.970884 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22186.336897 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198296.765456 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 193933.911159 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 187506.209752 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193178.929332 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 102369.869211 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 100796.959215 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95854.796990 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 99620.655492 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 15833780 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.971388 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 559992507 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15834292 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.365807 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 11768020500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.662838 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.739189 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 21.951060 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 6.618302 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934888 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.009256 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.042873 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.012926 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy +system.cpu0.dcache.tags.tag_accesses 1256795104 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1256795104 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 60226997 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 19487622 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 26552483 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 46438516 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 152705618 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 55178222 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 17776476 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 23635965 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 39304314 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 135894977 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 162747 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47920 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 80030 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 112762 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 403459 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 128939 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 43352 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu2.data 57616 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu3.data 100015 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 329922 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1452193 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 455982 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 583951 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 952022 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3444148 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1544925 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 494526 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 631378 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1099805 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3770634 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 115534158 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 37307450 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 50246064 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu3.data 85842845 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 288930517 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 115696905 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 37355370 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 50326094 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 85955607 # number of overall hits +system.cpu0.dcache.overall_hits::total 289333976 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2119141 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 646622 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 956573 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 3413419 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7135755 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 824381 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 254255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 649910 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 3547380 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 5275926 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 507242 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 136623 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 211405 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu3.data 339128 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1194398 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 658327 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 110099 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu2.data 158553 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu3.data 301342 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1228321 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 93463 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38738 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47683 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 182809 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 362693 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu3.data 9 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3601849 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1010976 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1765036 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu3.data 7262141 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13640002 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4109091 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 27685813500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 51054345551 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 98797663051 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 895533000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 849199000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 903591500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2648323500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 895533000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 849199000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 903591500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2648323500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032017 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030937 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031078 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019050 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014100 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014986 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014068 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008649 # 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mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061859 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035934 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026408 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026330 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015976 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029754 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030301 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12491.012251 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.669511 # average overall mshr miss latency system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1226,70 +1210,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 32812 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 32812 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4690 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 24112 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 32807 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 1.066845 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 193.234552 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 32806 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 32807 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 28807 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25324.695387 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21900.388938 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15981.091084 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 18461 64.09% 64.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 10165 35.29% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 148 0.51% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 1 0.00% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 7 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 28807 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2784865428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.637616 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.480689 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1009190500 36.24% 36.24% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1775674928 63.76% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2784865428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 24112 83.72% 83.72% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4690 16.28% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 28802 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32812 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 32054 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 32054 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4620 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23591 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 32052 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 32052 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 32052 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 28213 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24818.452486 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21684.712498 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13220.953832 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 18569 65.82% 65.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9436 33.45% 99.26% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 123 0.44% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 57 0.20% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 28213 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2332813120 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.567212 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.495462 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1009613500 43.28% 43.28% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1323199620 56.72% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2332813120 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 23591 83.62% 83.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4620 16.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 28211 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32054 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32812 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28802 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 32054 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 28211 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28802 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 61614 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 60265 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20290778 # DTB read hits -system.cpu1.dtb.read_misses 25288 # DTB read misses -system.cpu1.dtb.write_hits 18371397 # DTB write hits -system.cpu1.dtb.write_misses 7524 # DTB write misses -system.cpu1.dtb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 20818389 # DTB read hits +system.cpu1.dtb.read_misses 24417 # DTB read misses +system.cpu1.dtb.write_hits 18685767 # DTB write hits +system.cpu1.dtb.write_misses 7637 # DTB write misses +system.cpu1.dtb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5447 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 18352 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 18131 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 972 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2632 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20316066 # DTB read accesses -system.cpu1.dtb.write_accesses 18378921 # DTB write accesses +system.cpu1.dtb.perms_faults 2619 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20842806 # DTB read accesses +system.cpu1.dtb.write_accesses 18693404 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 38662175 # DTB hits -system.cpu1.dtb.misses 32812 # DTB misses -system.cpu1.dtb.accesses 38694987 # DTB accesses +system.cpu1.dtb.hits 39504156 # DTB hits +system.cpu1.dtb.misses 32054 # DTB misses +system.cpu1.dtb.accesses 39536210 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1319,139 +1300,138 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 20715 # Table walker walks requested -system.cpu1.itb.walker.walksLong 20715 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 943 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18376 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 20715 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 20715 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 20715 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 19319 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28783.140949 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25411.076231 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19382.499659 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 9731 50.37% 50.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 9374 48.52% 98.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 1 0.01% 98.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 168 0.87% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 22 0.11% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 19319 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 20183 # Table walker walks requested +system.cpu1.itb.walker.walksLong 20183 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 931 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17873 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 20183 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 20183 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 20183 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18804 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27697.085726 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24882.952231 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14267.961573 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 10321 54.89% 54.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 8257 43.91% 98.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 85 0.45% 99.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 115 0.61% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 9 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18804 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 18376 95.12% 95.12% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 943 4.88% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 19319 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17873 95.05% 95.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 931 4.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18804 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20715 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20715 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20183 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20183 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 19319 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 19319 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 40034 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 108288078 # ITB inst hits -system.cpu1.itb.inst_misses 20715 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18804 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18804 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 38987 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 110361810 # ITB inst hits +system.cpu1.itb.inst_misses 20183 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5447 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13933 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5343 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13509 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 108308793 # ITB inst accesses -system.cpu1.itb.hits 108288078 # DTB hits -system.cpu1.itb.misses 20715 # DTB misses -system.cpu1.itb.accesses 108308793 # DTB accesses -system.cpu1.numCycles 1188105502 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 110381993 # ITB inst accesses +system.cpu1.itb.hits 110361810 # DTB hits +system.cpu1.itb.misses 20183 # DTB misses +system.cpu1.itb.accesses 110381993 # DTB accesses +system.cpu1.numCycles 1184092485 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 108209898 # Number of instructions committed -system.cpu1.committedOps 126974949 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 116708707 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 113927 # Number of float alu accesses -system.cpu1.num_func_calls 6429899 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16402371 # number of instructions that are conditional controls -system.cpu1.num_int_insts 116708707 # number of integer instructions -system.cpu1.num_fp_insts 113927 # number of float instructions -system.cpu1.num_int_register_reads 168563743 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92548799 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 187994 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 86044 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 27990654 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27915757 # number of times the CC registers were written -system.cpu1.num_mem_refs 38659204 # number of memory refs -system.cpu1.num_load_insts 20289811 # Number of load instructions -system.cpu1.num_store_insts 18369393 # Number of store instructions -system.cpu1.num_idle_cycles 1163060687.092743 # Number of idle cycles -system.cpu1.num_busy_cycles 25044814.907257 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021080 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978920 # Percentage of idle cycles -system.cpu1.Branches 24096387 # Number of branches fetched +system.cpu1.committedInsts 110287651 # Number of instructions committed +system.cpu1.committedOps 129462738 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 119015901 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 118522 # Number of float alu accesses +system.cpu1.num_func_calls 6563146 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16773404 # number of instructions that are conditional controls +system.cpu1.num_int_insts 119015901 # number of integer instructions +system.cpu1.num_fp_insts 118522 # number of float instructions +system.cpu1.num_int_register_reads 171436551 # number of times the integer registers were read +system.cpu1.num_int_register_writes 94361756 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 191512 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 99140 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 28456563 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 28368844 # number of times the CC registers were written +system.cpu1.num_mem_refs 39501087 # number of memory refs +system.cpu1.num_load_insts 20816799 # Number of load instructions +system.cpu1.num_store_insts 18684288 # Number of store instructions +system.cpu1.num_idle_cycles 1157765533.383607 # Number of idle cycles +system.cpu1.num_busy_cycles 26326951.616393 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022234 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977766 # Percentage of idle cycles +system.cpu1.Branches 24650673 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 88104313 69.34% 69.34% # Class of executed instruction -system.cpu1.op_class::IntMult 267805 0.21% 69.56% # Class of executed instruction -system.cpu1.op_class::IntDiv 10742 0.01% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 11023 0.01% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::MemRead 20289811 15.97% 85.54% # Class of executed instruction -system.cpu1.op_class::MemWrite 18369393 14.46% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 89732955 69.27% 69.27% # Class of executed instruction +system.cpu1.op_class::IntMult 279120 0.22% 69.49% # Class of executed instruction +system.cpu1.op_class::IntDiv 11472 0.01% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 12221 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::MemRead 20816799 16.07% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 18684288 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 127053129 # Class of executed instruction -system.cpu2.branchPred.lookups 39776917 # Number of BP lookups -system.cpu2.branchPred.condPredicted 27483460 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2037436 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 28756518 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 19292729 # Number of BTB hits +system.cpu1.op_class::total 129536897 # Class of executed instruction +system.cpu2.branchPred.lookups 40914061 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28392312 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2019755 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 29835012 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20286508 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 67.089934 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4859404 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 317380 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1168446 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 802318 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 366128 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 149530 # Number of mispredicted indirect branches. +system.cpu2.branchPred.BTBHitPct 67.995642 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4999749 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 330951 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1158254 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 808792 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 349462 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 143811 # Number of mispredicted indirect branches. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1481,66 +1461,59 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 93967 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 93967 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6944 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29768 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 93967 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 93967 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 93967 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 36712 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 25539.442144 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 22201.127196 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 16823.219049 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-32767 24012 65.41% 65.41% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12449 33.91% 99.32% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-163839 190 0.52% 99.83% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::163840-196607 24 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-229375 5 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-294911 13 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::360448-393215 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::393216-425983 6 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::425984-458751 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 36712 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 29768 81.09% 81.09% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 6944 18.91% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 36712 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93967 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 93613 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93613 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7056 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30134 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93613 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93613 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93613 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 37190 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 24826.364614 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 21866.546445 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 12685.900174 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 36979 99.43% 99.43% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-131071 182 0.49% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 14 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 37190 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000359500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000359500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000359500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 30134 81.03% 81.03% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 7056 18.97% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 37190 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93613 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93967 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36712 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93613 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37190 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36712 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 130679 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37190 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 130803 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 28283757 # DTB read hits -system.cpu2.dtb.read_misses 78317 # DTB read misses -system.cpu2.dtb.write_hits 24727017 # DTB write hits -system.cpu2.dtb.write_misses 15650 # DTB write misses -system.cpu2.dtb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28720728 # DTB read hits +system.cpu2.dtb.read_misses 78135 # DTB read misses +system.cpu2.dtb.write_hits 25235469 # DTB write hits +system.cpu2.dtb.write_misses 15478 # DTB write misses +system.cpu2.dtb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 6736 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 178 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22142 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 90 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2053 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 22306 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 2280 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3761 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 28362074 # DTB read accesses -system.cpu2.dtb.write_accesses 24742667 # DTB write accesses +system.cpu2.dtb.perms_faults 3881 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28798863 # DTB read accesses +system.cpu2.dtb.write_accesses 25250947 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 53010774 # DTB hits -system.cpu2.dtb.misses 93967 # DTB misses -system.cpu2.dtb.accesses 53104741 # DTB accesses +system.cpu2.dtb.hits 53956197 # DTB hits +system.cpu2.dtb.misses 93613 # DTB misses +system.cpu2.dtb.accesses 54049810 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1570,125 +1543,126 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 27720 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27720 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1832 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 23079 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27720 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27720 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27720 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 24911 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 29141.122396 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25972.278022 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 17945.677356 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 12737 51.13% 51.13% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 11873 47.66% 98.79% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.80% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 235 0.94% 99.74% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 44 0.18% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 11 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 26529 # Table walker walks requested +system.cpu2.itb.walker.walksLong 26529 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1840 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22126 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 26529 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 26529 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 26529 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 23966 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 28028.290078 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 25290.360104 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 14051.232329 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 12906 53.85% 53.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 10781 44.98% 98.84% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 94 0.39% 99.23% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 160 0.67% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 9 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 3 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 2 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 24911 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 23079 92.65% 92.65% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1832 7.35% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 24911 # Table walker page sizes translated +system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 23966 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000327500 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000327500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000327500 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 22126 92.32% 92.32% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1840 7.68% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 23966 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27720 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27720 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 26529 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 26529 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24911 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24911 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 52631 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 67934299 # ITB inst hits -system.cpu2.itb.inst_misses 27720 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 23966 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 23966 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 50495 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70694439 # ITB inst hits +system.cpu2.itb.inst_misses 26529 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 6736 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 178 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 16373 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 6949 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 16608 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 46985 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 49134 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 67962019 # ITB inst accesses -system.cpu2.itb.hits 67934299 # DTB hits -system.cpu2.itb.misses 27720 # DTB misses -system.cpu2.itb.accesses 67962019 # DTB accesses -system.cpu2.numCycles 6665035719 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70720968 # ITB inst accesses +system.cpu2.itb.hits 70694439 # DTB hits +system.cpu2.itb.misses 26529 # DTB misses +system.cpu2.itb.accesses 70720968 # DTB accesses +system.cpu2.numCycles 1178523145 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 145016271 # Number of instructions committed -system.cpu2.committedOps 170167286 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 13691437 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1431 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 95890552078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 45.960606 # CPI: cycles per instruction -system.cpu2.ipc 0.021758 # IPC: instructions per cycle +system.cpu2.committedInsts 148428479 # Number of instructions committed +system.cpu2.committedOps 174146855 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 14845041 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1527 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 5665146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.940007 # CPI: cycles per instruction +system.cpu2.ipc 0.125944 # IPC: instructions per cycle system.cpu2.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 117737819 69.19% 69.19% # Class of committed instruction -system.cpu2.op_class_0::IntMult 373156 0.22% 69.41% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 14991 0.01% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 14732 0.01% 69.43% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu2.op_class_0::MemRead 27395173 16.10% 85.53% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 24631415 14.47% 100.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 120785530 69.36% 69.36% # Class of committed instruction +system.cpu2.op_class_0::IntMult 363959 0.21% 69.57% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 15220 0.01% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 16120 0.01% 69.59% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction +system.cpu2.op_class_0::MemRead 27827190 15.98% 85.56% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 25138836 14.44% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 170167286 # Class of committed instruction +system.cpu2.op_class_0::total 174146855 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 269996715 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 6395039004 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 74192352 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49437452 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3347278 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50136785 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 33881997 # Number of BTB hits +system.cpu2.tickCycles 278422703 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 900100442 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 75872804 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50609506 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3388105 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 51366888 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 34595075 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 67.579118 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9625210 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 106045 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2919697 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1497835 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 1421862 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 235981 # Number of mispredicted indirect branches. +system.cpu3.branchPred.BTBHitPct 67.348980 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9780520 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 107006 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 3035481 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1551109 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 1484372 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 245540 # Number of mispredicted indirect branches. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1718,88 +1692,97 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 504531 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 504531 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8579 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49642 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 315573 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 188958 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2466.701595 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 15451.703294 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-65535 187621 99.29% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-131071 761 0.40% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-196607 388 0.21% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-262143 66 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-327679 68 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-393215 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::458752-524287 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::720896-786431 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 188958 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 235670 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 22726.150974 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18499.548679 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 17978.117081 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 231036 98.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3674 1.56% 99.59% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 687 0.29% 99.88% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 78 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 114 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 37 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 12 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 235670 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -29346850516 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.109432 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -29931174016 101.99% 101.99% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 321600000 -1.10% 100.90% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 109899000 -0.37% 100.52% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 66660000 -0.23% 100.29% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 26916000 -0.09% 100.20% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 15037500 -0.05% 100.15% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 15685000 -0.05% 100.10% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 23345000 -0.08% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 4979000 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 163000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 37500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 1500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -29346850516 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 49642 85.26% 85.26% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8579 14.74% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 58221 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 504531 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 515601 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 515601 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8515 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50947 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 323770 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 191831 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2186.536587 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 12259.515456 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-32767 187758 97.88% 97.88% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-65535 2920 1.52% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-98303 506 0.26% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::98304-131071 334 0.17% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-163839 139 0.07% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::163840-196607 61 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-229375 40 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::229376-262143 20 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-294911 20 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::294912-327679 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-360447 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::360448-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-425983 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::425984-458751 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 191831 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 241555 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 22389.801494 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 18267.883118 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 16107.200178 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-32767 187656 77.69% 77.69% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-65535 48957 20.27% 97.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-98303 3861 1.60% 99.55% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::98304-131071 637 0.26% 99.82% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-163839 131 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::163840-196607 99 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-229375 72 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::229376-262143 72 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-294911 24 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::294912-327679 10 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-360447 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::425984-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 241555 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -21501827588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean -0.278457 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -22090252588 102.74% 102.74% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 330768000 -1.54% 101.20% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 106533500 -0.50% 100.70% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 66241000 -0.31% 100.39% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 26933500 -0.13% 100.27% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 15179500 -0.07% 100.20% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 14407500 -0.07% 100.13% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 23051000 -0.11% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 5101000 -0.02% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 177500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 28500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 4000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -21501827588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 50947 85.68% 85.68% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8515 14.32% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 59462 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 515601 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 504531 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58221 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 515601 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59462 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58221 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 562752 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59462 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 575063 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 58858607 # DTB read hits -system.cpu3.dtb.read_misses 345619 # DTB read misses -system.cpu3.dtb.write_hits 45337458 # DTB write hits -system.cpu3.dtb.write_misses 158912 # DTB write misses -system.cpu3.dtb.flush_tlb 1187 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 59668425 # DTB read hits +system.cpu3.dtb.read_misses 351201 # DTB read misses +system.cpu3.dtb.write_hits 46869082 # DTB write hits +system.cpu3.dtb.write_misses 164400 # DTB write misses +system.cpu3.dtb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11014 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 317 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 30161 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 96 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 4984 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 29776 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 81 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 5087 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 31824 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 59204226 # DTB read accesses -system.cpu3.dtb.write_accesses 45496370 # DTB write accesses +system.cpu3.dtb.perms_faults 32866 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 60019626 # DTB read accesses +system.cpu3.dtb.write_accesses 47033482 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 104196065 # DTB hits -system.cpu3.dtb.misses 504531 # DTB misses -system.cpu3.dtb.accesses 104700596 # DTB accesses +system.cpu3.dtb.hits 106537507 # DTB hits +system.cpu3.dtb.misses 515601 # DTB misses +system.cpu3.dtb.accesses 107053108 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1829,388 +1812,386 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 57749 # Table walker walks requested -system.cpu3.itb.walker.walksLong 57749 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1869 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 39849 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8061 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 49688 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1392.157060 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 9705.040089 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 49238 99.09% 99.09% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 280 0.56% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 20 0.04% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 53 0.11% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 71 0.14% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 11 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 8 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 49688 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 49779 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 28899.797103 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 24686.192128 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 20239.281965 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-32767 26767 53.77% 53.77% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-65535 22147 44.49% 98.26% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-98303 258 0.52% 98.78% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::98304-131071 22 0.04% 98.82% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-163839 390 0.78% 99.61% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::163840-196607 115 0.23% 99.84% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-229375 17 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.89% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-294911 35 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::393216-425983 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 49779 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -29349528016 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.914056 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.275786 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -2489826708 8.48% 8.48% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -26888510808 91.61% 100.10% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 25356500 -0.09% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 3132000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 321000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -29349528016 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 39849 95.52% 95.52% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 1869 4.48% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 41718 # Table walker page sizes translated +system.cpu3.itb.walker.walks 59193 # Table walker walks requested +system.cpu3.itb.walker.walksLong 59193 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2031 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40773 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8103 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 51090 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1228.772754 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 7780.748037 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 50655 99.15% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 286 0.56% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 82 0.16% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 46 0.09% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 10 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 51090 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 50907 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 28166.146110 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 24191.673448 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 17123.817204 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-32767 28249 55.49% 55.49% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-65535 21614 42.46% 97.95% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-98303 468 0.92% 98.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::98304-131071 440 0.86% 99.73% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-163839 42 0.08% 99.82% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::163840-196607 46 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::229376-262143 5 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-294911 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-360447 8 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 50907 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -25799318884 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.966437 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.171998 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -833253492 3.23% 3.23% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -24994847892 96.88% 100.11% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 25196000 -0.10% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 3318000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 257000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 11500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -25799318884 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 40773 95.26% 95.26% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 2031 4.74% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 42804 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 57749 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 57749 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59193 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59193 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 41718 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 41718 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 99467 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 52942414 # ITB inst hits -system.cpu3.itb.inst_misses 57749 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42804 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42804 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 101997 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 54025408 # ITB inst hits +system.cpu3.itb.inst_misses 59193 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1187 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1184 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11014 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 317 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 23395 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11562 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 307 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 22881 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 105407 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 108557 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 53000163 # ITB inst accesses -system.cpu3.itb.hits 52942414 # DTB hits -system.cpu3.itb.misses 57749 # DTB misses -system.cpu3.itb.accesses 53000163 # DTB accesses -system.cpu3.numCycles 367393110 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 54084601 # ITB inst accesses +system.cpu3.itb.hits 54025408 # DTB hits +system.cpu3.itb.misses 59193 # DTB misses +system.cpu3.itb.accesses 54084601 # DTB accesses +system.cpu3.numCycles 361836520 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 140035473 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 329019087 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 74192352 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45005042 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 204823343 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7558478 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1392210 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 11060 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 2040 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 2559054 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 98792 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 5855 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 52820449 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2085044 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 22116 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 352706869 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.090104 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.342261 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 142346168 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 336897254 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 75872804 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45926704 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 198396992 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7651750 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1405577 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 5653 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 1383 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2613876 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 96442 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 3584 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 53899852 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2112674 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 22747 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 348695424 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.129497 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.376512 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 272076000 77.14% 77.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 10117728 2.87% 80.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10161980 2.88% 82.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7427862 2.11% 85.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15229127 4.32% 89.31% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5034181 1.43% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5424859 1.54% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4755580 1.35% 93.63% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 22479552 6.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 266239908 76.35% 76.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10306563 2.96% 79.31% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10284239 2.95% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7691718 2.21% 84.46% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15615273 4.48% 88.94% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5057857 1.45% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5501918 1.58% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4845338 1.39% 93.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 23152610 6.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 352706869 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.201943 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.895551 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 114206040 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 168667111 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 59684206 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7159093 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2988451 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 11027683 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 801920 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 358900429 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2465138 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 2988451 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 118341583 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14120881 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 134077735 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 62618980 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 20557172 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 350288919 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 64776 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1233598 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 933453 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 10294556 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2108 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 333834444 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 533414830 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 412704173 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 534789 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 279088781 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 54745658 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 7872437 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 6763416 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 39440187 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 56882383 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 47659648 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7390317 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 8048428 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 332440192 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7866599 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 331640119 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 487315 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 46360769 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 29124307 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 191271 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 352706869 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.940271 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.666990 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 348695424 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.209688 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.931076 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 116362710 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 160827903 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 61169614 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7306733 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 3026861 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 11256055 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 810097 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 368055040 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2493002 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 3026861 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 120564311 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 11200780 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 131699731 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 64193761 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 18008282 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 359339338 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 52499 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 958756 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 756701 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 7766170 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2268 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 342255199 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 547447054 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 423264500 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 516863 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 287051688 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 55203506 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 8135865 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 7007620 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 40276067 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 57867192 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 49204017 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7450996 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 7967631 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 341094082 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8138044 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 340373041 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 493634 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 46733837 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 29214718 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 196934 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 348695424 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.976133 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.690131 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 224298657 63.59% 63.59% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 52689618 14.94% 78.53% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24223023 6.87% 85.40% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17391351 4.93% 90.33% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 12809979 3.63% 93.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9108183 2.58% 96.54% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6180606 1.75% 98.30% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3577681 1.01% 99.31% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2427771 0.69% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 216968703 62.22% 62.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 54146545 15.53% 77.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24769246 7.10% 84.85% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17826986 5.11% 89.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 13092392 3.75% 93.72% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9312814 2.67% 96.39% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6328109 1.81% 98.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3700278 1.06% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2550351 0.73% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 352706869 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 348695424 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1672825 25.77% 25.77% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 16469 0.25% 26.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1475 0.02% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2639879 40.67% 66.72% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2160482 33.28% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1713777 25.74% 25.74% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 17699 0.27% 26.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1135 0.02% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2657686 39.92% 65.94% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2267999 34.06% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 224723694 67.76% 67.76% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 782210 0.24% 68.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 40081 0.01% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 289 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.01% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 42689 0.01% 68.02% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.02% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.02% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.02% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 60119649 18.13% 86.15% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 45931480 13.85% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 231084475 67.89% 67.89% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 790161 0.23% 68.12% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 39649 0.01% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 230 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 2 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 1 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.14% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 44022 0.01% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 60938583 17.90% 86.05% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 47475914 13.95% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 331640119 # Type of FU issued -system.cpu3.iq.rate 0.902685 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6491130 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019573 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1022298212 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 386704326 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 319186755 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 667340 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 341320 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 298656 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 337775175 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 356047 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2654997 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 340373041 # Type of FU issued +system.cpu3.iq.rate 0.940682 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6658296 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019562 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1035940060 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 396014860 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 328005954 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 653376 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 333988 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 291600 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 346682688 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 348645 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2712348 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9481961 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 11664 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 384451 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4830568 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 9520955 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 12048 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 389231 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4853610 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2150262 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 4167936 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2139160 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 4030631 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2988451 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8896535 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 3943315 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 340388861 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1005407 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 56882383 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 47659648 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6617026 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 121260 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 3776054 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 384451 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1420846 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1561965 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2982811 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 327664673 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 58849807 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3477335 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 3026861 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 7711218 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 2621141 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 349315178 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1020364 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 57867192 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 49204017 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6861602 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 115452 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 2462398 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 389231 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1435072 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1591104 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3026176 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 336329886 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 59659129 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3533928 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 82070 # number of nop insts executed -system.cpu3.iew.exec_refs 104185879 # number of memory reference insts executed -system.cpu3.iew.exec_branches 60732264 # Number of branches executed -system.cpu3.iew.exec_stores 45336072 # Number of stores executed -system.cpu3.iew.exec_rate 0.891864 # Inst execution rate -system.cpu3.iew.wb_sent 320275931 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 319485411 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 157730975 # num instructions producing a value -system.cpu3.iew.wb_consumers 273958307 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.869601 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.575748 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 46394137 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7675328 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2556293 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 344852948 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.852381 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.849144 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 83052 # number of nop insts executed +system.cpu3.iew.exec_refs 106526406 # number of memory reference insts executed +system.cpu3.iew.exec_branches 62299744 # Number of branches executed +system.cpu3.iew.exec_stores 46867277 # Number of stores executed +system.cpu3.iew.exec_rate 0.929508 # Inst execution rate +system.cpu3.iew.wb_sent 329094434 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 328297554 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 161959018 # num instructions producing a value +system.cpu3.iew.wb_consumers 281119845 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.907309 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.576121 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 46762853 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7941110 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2588965 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 340775286 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.887677 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.879536 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 238109143 69.05% 69.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 51559449 14.95% 84.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 18667514 5.41% 89.41% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8519895 2.47% 91.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6096374 1.77% 93.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3704494 1.07% 94.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3440464 1.00% 95.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2103815 0.61% 96.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12651800 3.67% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 231011602 67.79% 67.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 53095779 15.58% 83.37% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18991936 5.57% 88.94% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8794245 2.58% 91.52% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6362030 1.87% 93.39% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3754940 1.10% 94.49% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3557662 1.04% 95.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2189630 0.64% 96.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 13017462 3.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 344852948 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 250222532 # Number of instructions committed -system.cpu3.commit.committedOps 293946017 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 340775286 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 257394207 # Number of instructions committed +system.cpu3.commit.committedOps 302498284 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 90229501 # Number of memory references committed -system.cpu3.commit.loads 47400421 # Number of loads committed -system.cpu3.commit.membars 1979442 # Number of memory barriers committed -system.cpu3.commit.branches 55926403 # Number of branches committed -system.cpu3.commit.fp_insts 287180 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 270155076 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7460078 # Number of function calls committed. +system.cpu3.commit.refs 92696643 # Number of memory references committed +system.cpu3.commit.loads 48346236 # Number of loads committed +system.cpu3.commit.membars 2024611 # Number of memory barriers committed +system.cpu3.commit.branches 57446863 # Number of branches committed +system.cpu3.commit.fp_insts 280508 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 277937546 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7603985 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 203036725 69.07% 69.07% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 612324 0.21% 69.28% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 30368 0.01% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 37099 0.01% 69.30% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 47400421 16.13% 85.43% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 42829080 14.57% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 209109353 69.13% 69.13% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 624464 0.21% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 29794 0.01% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 38030 0.01% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 48346236 15.98% 85.34% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 44350407 14.66% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 293946017 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12651800 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 670506126 # The number of ROB reads -system.cpu3.rob.rob_writes 688548433 # The number of ROB writes -system.cpu3.timesIdled 2399435 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 14686241 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98624955783 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 250222532 # Number of Instructions Simulated -system.cpu3.committedOps 293946017 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.468265 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.468265 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.681076 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.681076 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 385596565 # number of integer regfile reads -system.cpu3.int_regfile_writes 228796101 # number of integer regfile writes -system.cpu3.fp_regfile_reads 580685 # number of floating regfile reads -system.cpu3.fp_regfile_writes 358952 # number of floating regfile writes -system.cpu3.cc_regfile_reads 69302556 # number of cc regfile reads -system.cpu3.cc_regfile_writes 69940425 # number of cc regfile writes -system.cpu3.misc_regfile_reads 654940348 # number of misc regfile reads -system.cpu3.misc_regfile_writes 7733963 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40259 # Transaction distribution -system.iobus.trans_dist::ReadResp 40259 # Transaction distribution +system.cpu3.commit.op_class_0::total 302498284 # Class of committed instruction +system.cpu3.commit.bw_lim_events 13017462 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 674966133 # The number of ROB reads +system.cpu3.rob.rob_writes 706454494 # The number of ROB writes +system.cpu3.timesIdled 2436524 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 13141096 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98718347024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 257394207 # Number of Instructions Simulated +system.cpu3.committedOps 302498284 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.405768 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.405768 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.711355 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.711355 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 395796018 # number of integer regfile reads +system.cpu3.int_regfile_writes 234887439 # number of integer regfile writes +system.cpu3.fp_regfile_reads 565351 # number of floating regfile reads +system.cpu3.fp_regfile_writes 361110 # number of floating regfile writes +system.cpu3.cc_regfile_reads 71210349 # number of cc regfile reads +system.cpu3.cc_regfile_writes 71874336 # number of cc regfile writes +system.cpu3.misc_regfile_reads 658260097 # number of misc regfile reads +system.cpu3.misc_regfile_writes 8003769 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40273 # Transaction distribution +system.iobus.trans_dist::ReadResp 40273 # Transaction distribution system.iobus.trans_dist::WriteReq 136539 # Transaction distribution system.iobus.trans_dist::WriteResp 136539 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) @@ -2227,11 +2208,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353624 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -2246,91 +2227,93 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491984 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 28447500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13621500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 82500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 18500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 12315500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 11667500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 21455000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 21479000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 262449133 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 236022564 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 54866000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 41037000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 76206000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 70810000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.420631 # Cycle average of tags in use +system.iocache.tags.replacements 115466 # number of replacements +system.iocache.tags.tagsinuse 10.425431 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089104998009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.909087 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.511544 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.369318 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.281971 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13087288267509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544657 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.880774 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221541 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430048 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651589 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039587 # Number of tag accesses -system.iocache.tags.data_accesses 1039587 # Number of data accesses +system.iocache.tags.tag_accesses 1039713 # Number of tag accesses +system.iocache.tags.data_accesses 1039713 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8843 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115470 # number of demand (read+write) misses -system.iocache.demand_misses::total 115510 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115484 # number of demand (read+write) misses +system.iocache.demand_misses::total 115524 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115470 # number of overall misses -system.iocache.overall_misses::total 115510 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 1073978422 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1073978422 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 6143621711 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6143621711 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 7217600133 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7217600133 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 7217600133 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7217600133 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 115484 # number of overall misses +system.iocache.overall_misses::total 115524 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 1088192723 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1088192723 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 5155830841 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5155830841 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 6244023564 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6244023564 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 6244023564 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6244023564 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8806 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8843 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115470 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115510 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115484 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115524 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115470 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115510 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115484 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115524 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2344,830 +2327,838 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 121959.848058 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121449.555807 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 57597.893488 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 57597.893488 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 62506.279839 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 62484.634516 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 62506.279839 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 62484.634516 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 21262 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123377.859751 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122862.450378 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48337.122562 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48337.122562 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 54068.300059 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54049.578997 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 54068.300059 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54049.578997 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22542 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2148 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2372 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.898510 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.503373 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 5707 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 5707 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 48856 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 48856 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 54563 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 54563 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 54563 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 54563 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 788628422 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 788628422 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3698645601 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3698645601 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 4487274023 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4487274023 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 4487274023 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4487274023 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.648081 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.645369 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.458036 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.458036 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.472530 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.472366 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.472530 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.472366 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138186.161206 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 138186.161206 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75705.043413 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75705.043413 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 82240.236479 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82240.236479 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 82240.236479 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82240.236479 # average overall mshr miss latency -system.l2c.tags.replacements 1158394 # number of replacements -system.l2c.tags.tagsinuse 65318.411237 # Cycle average of tags in use -system.l2c.tags.total_refs 47534578 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1221500 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 38.914923 # Average number of references to valid blocks. +system.iocache.ReadReq_mshr_misses::realview.ide 5693 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 5693 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 43488 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 43488 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 49181 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 49181 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 49181 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 49181 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 803542723 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 803542723 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2978631735 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2978631735 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 3782174458 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3782174458 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 3782174458 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3782174458 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.645465 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.642768 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.407710 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.407710 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.425869 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.425721 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.425869 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.425721 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141145.744423 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 141145.744423 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68493.187431 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68493.187431 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.162969 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.162969 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency +system.l2c.tags.replacements 1175380 # number of replacements +system.l2c.tags.tagsinuse 65273.508044 # Cycle average of tags in use +system.l2c.tags.total_refs 47870421 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1238537 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 38.650780 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36632.144769 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 146.246189 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 202.168712 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4157.667973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8742.110148 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 28.831722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 47.900932 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 347.749800 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2205.430231 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 32.408854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 51.307546 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1406.712197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3461.981272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 83.334747 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 114.561611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2502.338392 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 5155.516141 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.558962 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002232 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063441 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.133394 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005306 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.033652 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000495 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000783 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.021465 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.052826 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.001748 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.038183 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.078667 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996680 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 263 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62843 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 36522.594911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 124.677817 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 187.809125 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3696.971873 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11236.224149 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 38.223238 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 48.365437 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 755.794708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1969.239780 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 46.667563 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 65.236270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2038.056565 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2946.228048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 100.667016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 147.723446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1700.524086 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 3648.504014 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.557291 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002866 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056411 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.171451 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000738 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011533 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.030048 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000712 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000995 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.031098 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.044956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001536 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.itb.walker 0.002254 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.025948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.055672 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995995 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 287 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62870 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 261 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 560 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2808 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5049 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54318 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.958908 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 420535401 # Number of tag accesses -system.l2c.tags.data_accesses 420535401 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 157367 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 107004 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 58638 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 43521 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 153028 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 59170 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 293557 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 105792 # number of ReadReq hits -system.l2c.ReadReq_hits::total 978077 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7502187 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7502187 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15831215 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15831215 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3881 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1299 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1589 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2641 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9410 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 649967 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 198078 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 1805331500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 7992585005 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 93598501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 78350001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 1819221514 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 15188680063 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 33734612095 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 834447000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 789828000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 841649000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2465924000 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 834447000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 789828000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 841649000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2465924000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.006211 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.008928 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003644 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.008707 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003993 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.009296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.004019 # mshr miss rate for ReadReq accesses +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790023 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.779716 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.780928 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.461165 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.222222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.222222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.217550 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.199771 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.185759 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117461 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003615 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033886 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.034832 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.034369 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020182 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.170574 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.189576 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.241330 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.098725 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.006211 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.008928 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.076961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003644 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008707 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.075228 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.009296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.069659 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.016871 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.006211 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.008928 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.076961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003644 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008707 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006188 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.075228 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.009296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004988 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.069659 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.016871 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77766.845156 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18911.221122 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19008.516862 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18993.052738 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18979.101746 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45750 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72201.028544 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72024.542634 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89442.929077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80214.990210 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74958.556091 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74062.168365 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74773.572716 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79572.242152 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77048.923506 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18727.928647 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19459.291299 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20267.105791 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19827.788654 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72828.309288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 72985.645061 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 85708.127253 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 78510.647630 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74557.909605 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73963.709677 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72252.189974 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72828.309288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 76368.421053 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 78675.311203 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74754.927536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 72985.645061 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 79455.433786 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78664.659639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76239.272232 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 85708.127253 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 78510.647630 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170923.187218 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 166314.592546 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169927.114880 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169084.201865 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89696.549500 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 87787.929310 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 85489.994921 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 87614.993782 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2708332 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1355057 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2739 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 76738 # Transaction distribution -system.membus.trans_dist::ReadResp 445217 # Transaction distribution +system.membus.trans_dist::ReadResp 443894 # Transaction distribution system.membus.trans_dist::WriteReq 33648 # Transaction distribution system.membus.trans_dist::WriteResp 33648 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1070328 # Transaction distribution -system.membus.trans_dist::CleanEvict 202542 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34555 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1089631 # Transaction distribution +system.membus.trans_dist::CleanEvict 200219 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35037 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14337 # Transaction distribution -system.membus.trans_dist::ReadExReq 398389 # Transaction distribution -system.membus.trans_dist::ReadExResp 398389 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 368479 # Transaction distribution -system.membus.trans_dist::InvalidateReq 599634 # Transaction distribution -system.membus.trans_dist::InvalidateResp 450461 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14486 # Transaction distribution +system.membus.trans_dist::ReadExReq 415725 # Transaction distribution +system.membus.trans_dist::ReadExResp 415725 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 367156 # Transaction distribution +system.membus.trans_dist::InvalidateReq 600547 # Transaction distribution +system.membus.trans_dist::InvalidateResp 436040 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6760 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3699064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3828461 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 295887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 295887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4124348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3729876 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3859270 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302047 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 302047 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4161317 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 110365024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 110534446 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7279360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7279360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 117813806 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2019 # Total snoops (count) -system.membus.snoop_fanout::samples 2784335 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 112629920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 112799278 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7328576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7328576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 120127854 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1179 # Total snoops (count) +system.membus.snoop_fanout::samples 2232317 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015391 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.123101 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2784335 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2197960 98.46% 98.46% # Request fanout histogram +system.membus.snoop_fanout::1 34357 1.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2784335 # Request fanout histogram -system.membus.reqLayer0.occupancy 62370000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2232317 # Request fanout histogram +system.membus.reqLayer0.occupancy 46873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1751500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1706000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3098674718 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3219472355 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2309468641 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2319703830 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 28779324 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 28713899 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3221,61 +3212,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 51706899 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26184435 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3148 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2316 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2316 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 52099554 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26383185 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3169 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2082 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2082 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1482882 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23802645 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1490866 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23977004 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 7959053 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15833779 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2295611 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43290 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43295 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1978465 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1978465 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15834389 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6490632 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1273555 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1224699 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47588616 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29285291 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 809621 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1728313 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 79411841 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2026923028 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1022015642 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2929800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6124520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3057992990 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1664727 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 38155391 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.016407 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.127033 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 8032732 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 15904025 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2315696 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43839 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43848 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2004412 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2004412 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15904657 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6582020 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1233125 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1226250 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47799339 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29657154 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 806902 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1734280 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 79997675 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2035912148 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1036024666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2901928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6114504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3080953246 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1497196 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 38183781 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.016504 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.127404 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 37529389 98.36% 98.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 626002 1.64% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 37553594 98.35% 98.35% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 630187 1.65% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 38155391 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 30930822494 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 38183781 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 31295495912 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 835176 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 884168 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15386050433 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15602902016 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7871932216 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7909503562 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 287489224 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 285711732 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 705270825 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 709709811 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |