diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt | 5175 |
1 files changed, 2589 insertions, 2586 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index 100a686ad..e8e31dd45 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,192 +1,192 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.357853 # Number of seconds simulated -sim_ticks 51357853367000 # Number of ticks simulated -final_tick 51357853367000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.397579 # Number of seconds simulated +sim_ticks 51397578885000 # Number of ticks simulated +final_tick 51397578885000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 254475 # Simulator instruction rate (inst/s) -host_op_rate 295745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14267482520 # Simulator tick rate (ticks/s) -host_mem_usage 733332 # Number of bytes of host memory used -host_seconds 3599.64 # Real time elapsed on the host -sim_insts 916019679 # Number of instructions simulated -sim_ops 1064576900 # Number of ops (including micro ops) simulated +host_inst_rate 213094 # Simulator instruction rate (inst/s) +host_op_rate 250423 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11187167929 # Simulator tick rate (ticks/s) +host_mem_usage 682236 # Number of bytes of host memory used +host_seconds 4594.33 # Real time elapsed on the host +sim_insts 979026656 # Number of instructions simulated +sim_ops 1150528336 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 86272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 95168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2358260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 43599240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 19200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 20160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 451648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5774336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 28864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 24640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1511104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 8165824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 62272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 59136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1907392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 14522560 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 410688 # Number of bytes read from this memory -system.physmem.bytes_read::total 79096764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2358260 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 451648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1511104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1907392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6228404 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67268864 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 187840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 177856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2851188 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 60331016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 46336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 44800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 415360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9688384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 76288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 60224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1747072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 13459648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 113856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 106880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1985280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 25411584 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 412224 # Number of bytes read from this memory +system.physmem.bytes_read::total 117115836 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2851188 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 415360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1747072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1985280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6998900 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 101778880 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 67289444 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1487 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 77255 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 681251 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 315 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7057 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 90224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 385 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 23611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 127591 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 924 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 29803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 226915 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6417 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1276307 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1051076 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 101799460 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 84957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 942685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 724 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 700 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6490 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 151381 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 1192 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 27298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 210307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 1670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 31020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 397056 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6441 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1870355 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1590295 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1053649 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1853 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 45918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 848930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 112433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 29423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 158999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 37139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 282772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1540110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 45918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 29423 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 37139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 121275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1309807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1310207 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1309807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 45918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 849331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 112433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 29423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 158999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 37139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 282772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2850318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 512711 # Number of read requests accepted -system.physmem.writeReqs 445331 # Number of write requests accepted -system.physmem.readBursts 512711 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 445331 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32795328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue -system.physmem.bytesWritten 28499456 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32813504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 28501184 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 1592868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 55473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1173810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 8081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 188499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 1484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 1172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 33991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 261873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 2215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 2079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 38626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 494412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2278626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 55473 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 8081 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 33991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 38626 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 136172 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1980227 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 400 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1980628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1980227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 55473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1174211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 8081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 188499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 1484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 1172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 33991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 261873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 2215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 2079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 38626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 494412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4259253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 833134 # Number of read requests accepted +system.physmem.writeReqs 737289 # Number of write requests accepted +system.physmem.readBursts 833134 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 737289 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 53302080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue +system.physmem.bytesWritten 47184896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 53320576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 47186496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 68360 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 31469 # Per bank write bursts -system.physmem.perBankRdBursts::1 33714 # Per bank write bursts -system.physmem.perBankRdBursts::2 32400 # Per bank write bursts -system.physmem.perBankRdBursts::3 32794 # Per bank write bursts -system.physmem.perBankRdBursts::4 31510 # Per bank write bursts -system.physmem.perBankRdBursts::5 36975 # Per bank write bursts -system.physmem.perBankRdBursts::6 32126 # Per bank write bursts -system.physmem.perBankRdBursts::7 32020 # Per bank write bursts -system.physmem.perBankRdBursts::8 29401 # Per bank write bursts -system.physmem.perBankRdBursts::9 33672 # Per bank write bursts -system.physmem.perBankRdBursts::10 31630 # Per bank write bursts -system.physmem.perBankRdBursts::11 33204 # Per bank write bursts -system.physmem.perBankRdBursts::12 32821 # Per bank write bursts -system.physmem.perBankRdBursts::13 30845 # Per bank write bursts -system.physmem.perBankRdBursts::14 28756 # Per bank write bursts -system.physmem.perBankRdBursts::15 29090 # Per bank write bursts -system.physmem.perBankWrBursts::0 26343 # Per bank write bursts -system.physmem.perBankWrBursts::1 28031 # Per bank write bursts -system.physmem.perBankWrBursts::2 27542 # Per bank write bursts -system.physmem.perBankWrBursts::3 28584 # Per bank write bursts -system.physmem.perBankWrBursts::4 28467 # Per bank write bursts -system.physmem.perBankWrBursts::5 30964 # Per bank write bursts -system.physmem.perBankWrBursts::6 28168 # Per bank write bursts -system.physmem.perBankWrBursts::7 28820 # Per bank write bursts -system.physmem.perBankWrBursts::8 26688 # Per bank write bursts -system.physmem.perBankWrBursts::9 29870 # Per bank write bursts -system.physmem.perBankWrBursts::10 27026 # Per bank write bursts -system.physmem.perBankWrBursts::11 28792 # Per bank write bursts -system.physmem.perBankWrBursts::12 28018 # Per bank write bursts -system.physmem.perBankWrBursts::13 26681 # Per bank write bursts -system.physmem.perBankWrBursts::14 25511 # Per bank write bursts -system.physmem.perBankWrBursts::15 25799 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 72650 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 50780 # Per bank write bursts +system.physmem.perBankRdBursts::1 53589 # Per bank write bursts +system.physmem.perBankRdBursts::2 52846 # Per bank write bursts +system.physmem.perBankRdBursts::3 50887 # Per bank write bursts +system.physmem.perBankRdBursts::4 54092 # Per bank write bursts +system.physmem.perBankRdBursts::5 57010 # Per bank write bursts +system.physmem.perBankRdBursts::6 51070 # Per bank write bursts +system.physmem.perBankRdBursts::7 50979 # Per bank write bursts +system.physmem.perBankRdBursts::8 47072 # Per bank write bursts +system.physmem.perBankRdBursts::9 53421 # Per bank write bursts +system.physmem.perBankRdBursts::10 50826 # Per bank write bursts +system.physmem.perBankRdBursts::11 55035 # Per bank write bursts +system.physmem.perBankRdBursts::12 52027 # Per bank write bursts +system.physmem.perBankRdBursts::13 53888 # Per bank write bursts +system.physmem.perBankRdBursts::14 49567 # Per bank write bursts +system.physmem.perBankRdBursts::15 49756 # Per bank write bursts +system.physmem.perBankWrBursts::0 44616 # Per bank write bursts +system.physmem.perBankWrBursts::1 46679 # Per bank write bursts +system.physmem.perBankWrBursts::2 46441 # Per bank write bursts +system.physmem.perBankWrBursts::3 46533 # Per bank write bursts +system.physmem.perBankWrBursts::4 48478 # Per bank write bursts +system.physmem.perBankWrBursts::5 49819 # Per bank write bursts +system.physmem.perBankWrBursts::6 45666 # Per bank write bursts +system.physmem.perBankWrBursts::7 46728 # Per bank write bursts +system.physmem.perBankWrBursts::8 42759 # Per bank write bursts +system.physmem.perBankWrBursts::9 46487 # Per bank write bursts +system.physmem.perBankWrBursts::10 43753 # Per bank write bursts +system.physmem.perBankWrBursts::11 47850 # Per bank write bursts +system.physmem.perBankWrBursts::12 45610 # Per bank write bursts +system.physmem.perBankWrBursts::13 46767 # Per bank write bursts +system.physmem.perBankWrBursts::14 44243 # Per bank write bursts +system.physmem.perBankWrBursts::15 44835 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 51356853146000 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 51396578546000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 512711 # Read request sizes (log2) +system.physmem.readPktSize::6 833134 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 445331 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 362263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 95120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 330 # 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What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 737289 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 571213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 169334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 140 # 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What read queue length does an incoming req see @@ -198,184 +198,186 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 8015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 18279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 21711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 24541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 25822 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 259364 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.325041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.327680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.441771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 119855 46.21% 46.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 64854 25.01% 71.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 23816 9.18% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11723 4.52% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8762 3.38% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5465 2.11% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4497 1.73% 92.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3594 1.39% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16798 6.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 259364 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 24808 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.654708 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 12.973882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-31 22443 90.47% 90.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-63 2162 8.71% 99.18% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-95 162 0.65% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-127 16 0.06% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-159 10 0.04% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::160-191 3 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::192-223 3 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::224-255 3 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-287 2 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-415 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::544-575 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::608-639 2 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 24808 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 24808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.950016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.268943 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.650949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 27 0.11% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 16 0.06% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 10 0.04% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 35 0.14% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 23050 92.91% 93.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 468 1.89% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 156 0.63% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 288 1.16% 96.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 65 0.26% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 175 0.71% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 65 0.26% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 18 0.07% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 53 0.21% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 60 0.24% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 15 0.06% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.05% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 191 0.77% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 12 0.05% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 13 0.05% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 46 0.19% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 24808 # Writes before turning the bus around for reads -system.physmem.totQLat 10667534010 # Total ticks spent queuing -system.physmem.totMemAccLat 20275540260 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2562135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20817.67 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 667 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 393907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 255.102976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.689482 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.846029 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 173695 44.10% 44.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 94994 24.12% 68.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 37135 9.43% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19371 4.92% 82.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15343 3.90% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9742 2.47% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8567 2.17% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6531 1.66% 92.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 28529 7.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 393907 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 42633 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 19.534281 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 9.731161 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-31 39808 93.37% 93.37% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-63 2621 6.15% 99.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-95 170 0.40% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-127 21 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-159 5 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::224-255 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-287 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::352-383 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::544-575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::608-639 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 42633 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 42633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.293270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.880471 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.837851 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 31 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.02% 0.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 18 0.04% 0.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 54 0.13% 0.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 40522 95.05% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 728 1.71% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 202 0.47% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 312 0.73% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 57 0.13% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 185 0.43% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 71 0.17% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.04% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 39 0.09% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 54 0.13% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 19 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 210 0.49% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 11 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 44 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 42633 # Writes before turning the bus around for reads +system.physmem.totQLat 19475290366 # Total ticks spent queuing +system.physmem.totMemAccLat 35091134116 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4164225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23384.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39567.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42134.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.01 # Data bus utilization in percentage -system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing -system.physmem.readRowHits 389460 # Number of row buffer hits during reads -system.physmem.writeRowHits 308905 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.37 # Row buffer hit rate for writes -system.physmem.avgGap 53606056.05 # Average gap between requests -system.physmem.pageHitRate 72.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1011233160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 550085250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2051392200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1470435120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3314894774880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1181011387995 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30447742538250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34948731846855 # Total energy per rank (pJ) -system.physmem_0.averagePower 666.034408 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48934758214122 # Time in different power states -system.physmem_0.memoryStateTime::REF 1694731480000 # Time in different power states +system.physmem.avgWrQLen 13.53 # Average write queue length when enqueuing +system.physmem.readRowHits 652462 # Number of row buffer hits during reads +system.physmem.writeRowHits 523738 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.04 # Row buffer hit rate for writes +system.physmem.avgGap 32727856.47 # Average gap between requests +system.physmem.pageHitRate 74.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1529501400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 832833375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3285765600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2429740800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3315984618960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1212289072380 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29739570673500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34275922206015 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.648127 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48905170971226 # Time in different power states +system.physmem_0.memoryStateTime::REF 1695288660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 123339078628 # Time in different power states +system.physmem_0.memoryStateTime::ACT 169075280274 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 949558680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 516544875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1945468200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1415134800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3314894774880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1177770817440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29706179302500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34203671601375 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.620773 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48939527598915 # Time in different power states -system.physmem_1.memoryStateTime::REF 1694731480000 # Time in different power states +system.physmem_1.actEnergy 1448412840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 788411250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3210347400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2347729920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3315984618960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1209778712865 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29729309949000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34262868182235 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.663987 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48908958102968 # Time in different power states +system.physmem_1.memoryStateTime::REF 1695288660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 118558226835 # Time in different power states +system.physmem_1.memoryStateTime::ACT 165299992532 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -435,47 +437,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 89680 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 89680 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 89680 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 89680 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 89680 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 382558723572 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.578670 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -221375171178 -57.87% -57.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 603933894750 157.87% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 382558723572 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 65458 84.89% 84.89% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11653 15.11% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 77111 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 89680 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 119866 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 119866 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 119866 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 119866 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 119866 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 379345082112 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.652647 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -247578241138 -65.26% -65.26% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 626923323250 165.26% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 379345082112 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 88729 84.84% 84.84% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 15861 15.16% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 104590 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 119866 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 89680 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77111 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 119866 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104590 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77111 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 166791 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104590 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 224456 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 70228403 # DTB read hits -system.cpu0.dtb.read_misses 67978 # DTB read misses -system.cpu0.dtb.write_hits 59109334 # DTB write hits -system.cpu0.dtb.write_misses 21702 # DTB write misses -system.cpu0.dtb.flush_tlb 1217 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 75642766 # DTB read hits +system.cpu0.dtb.read_misses 89640 # DTB read misses +system.cpu0.dtb.write_hits 69609144 # DTB write hits +system.cpu0.dtb.write_misses 30226 # DTB write misses +system.cpu0.dtb.flush_tlb 1263 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16331 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 386 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40606 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 20153 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 452 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 47006 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2912 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3911 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7556 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 70296381 # DTB read accesses -system.cpu0.dtb.write_accesses 59131036 # DTB write accesses +system.cpu0.dtb.perms_faults 8593 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 75732406 # DTB read accesses +system.cpu0.dtb.write_accesses 69639370 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 129337737 # DTB hits -system.cpu0.dtb.misses 89680 # DTB misses -system.cpu0.dtb.accesses 129427417 # DTB accesses +system.cpu0.dtb.hits 145251910 # DTB hits +system.cpu0.dtb.misses 119866 # DTB misses +system.cpu0.dtb.accesses 145371776 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -505,697 +507,697 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 52945 # Table walker walks requested -system.cpu0.itb.walker.walksLong 52945 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 52945 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 52945 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 52945 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 382558723572 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.578782 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -221418129178 -57.88% -57.88% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 603976852750 157.88% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 382558723572 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 46017 94.83% 94.83% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2511 5.17% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 48528 # Table walker page sizes translated +system.cpu0.itb.walker.walks 57950 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57950 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 57950 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57950 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57950 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 379345082112 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.652788 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -247631753638 -65.28% -65.28% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 626976835750 165.28% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 379345082112 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 50452 94.94% 94.94% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2688 5.06% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 53140 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52945 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52945 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57950 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57950 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48528 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48528 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 101473 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 364915659 # ITB inst hits -system.cpu0.itb.inst_misses 52945 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53140 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53140 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 111090 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 405381622 # ITB inst hits +system.cpu0.itb.inst_misses 57950 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1217 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1263 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16331 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 386 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28384 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 20153 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 452 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 33228 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 364968604 # ITB inst accesses -system.cpu0.itb.hits 364915659 # DTB hits -system.cpu0.itb.misses 52945 # DTB misses -system.cpu0.itb.accesses 364968604 # DTB accesses -system.cpu0.numCycles 436289438 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 405439572 # ITB inst accesses +system.cpu0.itb.hits 405381622 # DTB hits +system.cpu0.itb.misses 57950 # DTB misses +system.cpu0.itb.accesses 405439572 # DTB accesses +system.cpu0.numCycles 487302102 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 364774665 # Number of instructions committed -system.cpu0.committedOps 425727567 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 388492427 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 355504 # Number of float alu accesses -system.cpu0.num_func_calls 20838410 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 59397900 # number of instructions that are conditional controls -system.cpu0.num_int_insts 388492427 # number of integer instructions -system.cpu0.num_fp_insts 355504 # number of float instructions -system.cpu0.num_int_register_reads 563346906 # number of times the integer registers were read -system.cpu0.num_int_register_writes 307286794 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 569525 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 310180 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 98350677 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 98136627 # number of times the CC registers were written -system.cpu0.num_mem_refs 129410259 # number of memory refs -system.cpu0.num_load_insts 70285041 # Number of load instructions -system.cpu0.num_store_insts 59125218 # Number of store instructions -system.cpu0.num_idle_cycles 425895176.866435 # Number of idle cycles -system.cpu0.num_busy_cycles 10394261.133565 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023824 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976176 # Percentage of idle cycles -system.cpu0.Branches 85458268 # Number of branches fetched +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 17144 # number of quiesce instructions executed +system.cpu0.committedInsts 405220560 # Number of instructions committed +system.cpu0.committedOps 476699664 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 436776878 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 371179 # Number of float alu accesses +system.cpu0.num_func_calls 23615839 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 62442452 # number of instructions that are conditional controls +system.cpu0.num_int_insts 436776878 # number of integer instructions +system.cpu0.num_fp_insts 371179 # number of float instructions +system.cpu0.num_int_register_reads 647764481 # number of times the integer registers were read +system.cpu0.num_int_register_writes 347118708 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 591811 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 329388 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 109017876 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 108807189 # number of times the CC registers were written +system.cpu0.num_mem_refs 145355316 # number of memory refs +system.cpu0.num_load_insts 75721514 # Number of load instructions +system.cpu0.num_store_insts 69633802 # Number of store instructions +system.cpu0.num_idle_cycles 473916691.596574 # Number of idle cycles +system.cpu0.num_busy_cycles 13385410.403426 # Number of busy cycles +system.cpu0.not_idle_fraction 0.027468 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.972532 # Percentage of idle cycles +system.cpu0.Branches 90584626 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 295583613 69.39% 69.39% # Class of executed instruction -system.cpu0.op_class::IntMult 876793 0.21% 69.60% # Class of executed instruction -system.cpu0.op_class::IntDiv 40797 0.01% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 48752 0.01% 69.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.62% # Class of executed instruction -system.cpu0.op_class::MemRead 70285041 16.50% 86.12% # Class of executed instruction -system.cpu0.op_class::MemWrite 59125218 13.88% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 330567149 69.31% 69.31% # Class of executed instruction +system.cpu0.op_class::IntMult 941893 0.20% 69.51% # Class of executed instruction +system.cpu0.op_class::IntDiv 42225 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 50408 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::MemRead 75721514 15.88% 85.40% # Class of executed instruction +system.cpu0.op_class::MemWrite 69633802 14.60% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 425960214 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 19395 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 9657229 # number of replacements +system.cpu0.op_class::total 476956991 # Class of executed instruction +system.cpu0.dcache.tags.replacements 11638567 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 312286694 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9657741 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 32.335377 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 335736078 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11639079 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.845588 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.836076 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.401672 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.084857 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.677113 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970383 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008597 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009931 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.011088 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.702275 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.106923 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.404077 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.786443 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964262 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.013881 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010555 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.011302 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1318802850 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1318802850 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 66114410 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 21101681 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 29024806 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 53770773 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 170011670 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 55935115 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17375745 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 22998325 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 38100786 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134409971 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 159119 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 46931 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 76549 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113298 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395897 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125533 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44387 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 60913 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 98030 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 328863 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1432077 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 445625 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 574107 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 937674 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3389483 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1521761 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 483660 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 621712 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1080020 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3707153 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 122049525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 38477426 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 52023131 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 91871559 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 304421641 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 122208644 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 38524357 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 52099680 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 91984857 # number of overall hits -system.cpu0.dcache.overall_hits::total 304817538 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2010257 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 646801 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 1011664 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3491455 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7160177 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 846558 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 254963 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 597011 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 3430913 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5129445 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 467844 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 148258 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 206108 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 346909 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1169119 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 678893 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 111170 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 148628 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 287890 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1226581 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 90398 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 38264 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 47866 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 181381 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 357909 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2856815 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 901764 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1608675 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 6922368 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 12289622 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3324659 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1050022 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1814783 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 7269277 # number of overall misses -system.cpu0.dcache.overall_misses::total 13458741 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 10543203000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 17532852000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 61974045500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 90050100500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9377516000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22074229500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 115413229590 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 146864975090 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 3621904000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 5139897000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 11619226144 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 20381027144 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 545937500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 715302000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2408045500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3669285000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 124500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 124500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 19920719000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 39607081500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 177387275090 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 236915075590 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 19920719000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 39607081500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 177387275090 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 236915075590 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 68124667 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 21748482 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 30036470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 57262228 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 177171847 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 56781673 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 17630708 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 23595336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 41531699 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 139539416 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 626963 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 195189 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 282657 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 460207 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1565016 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 804426 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 155557 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 209541 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 385920 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1555444 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1522475 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 483889 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 621973 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1119055 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3747392 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1521762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 483660 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 621712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1080024 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3707158 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 124906340 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 39379190 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 53631806 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 98793927 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 316711263 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 125533303 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 39574379 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 53914463 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 99254134 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 318276279 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029509 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.029740 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.033681 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.060973 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040414 # 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miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714658 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.709303 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.745984 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788573 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059376 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.079076 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076958 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.162084 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095509 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.tags.tag_accesses 1427343443 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1427343443 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 70546993 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 21833087 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 29621653 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 49726137 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 171727870 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 65848513 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 20323574 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 26400594 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 41881288 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 154453969 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178125 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 52842 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 85285 # 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miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.046902 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016038 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015533 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.027279 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.095800 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.040811 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782749 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.788197 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.756902 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.787970 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780438 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843336 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714593 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.716404 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.740545 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788192 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055945 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.071383 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.071971 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.147061 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087954 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.022872 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.022900 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.029995 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.070069 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.038804 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026484 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026533 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.033660 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.073239 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.042286 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16300.536023 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17330.706638 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17750.206003 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12576.518779 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36779.909242 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36974.577520 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33639.217780 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 28631.747702 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32579.868670 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34582.292704 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 40359.950481 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16616.128200 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14267.653669 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14943.843229 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13276.172808 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10252.005398 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 31125 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24900 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22090.834187 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24620.934309 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25625.230425 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19277.653584 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18971.715831 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21824.692815 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24402.327094 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17603.063733 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 14691366 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 44925 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 885387 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 409 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.593158 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 109.841076 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025360 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025016 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.034392 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.083962 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.044028 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029771 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029394 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.038734 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.088076 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.048336 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17265.192601 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17786.020508 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18276.467758 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12758.470978 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 49170.637161 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 50924.840287 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 56484.083178 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46275.845140 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40087.215016 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 43167.282524 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 48710.517042 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20067.551409 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15458.708638 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16287.950226 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14422.309353 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11049.200029 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 48750 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24375 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26723.738855 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30082.656915 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 38468.087690 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 27420.865503 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22612.696749 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26549.401222 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 36456.891349 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24830.491802 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 26241707 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 45127 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1118476 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 412 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.462021 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 109.531553 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7514109 # number of writebacks -system.cpu0.dcache.writebacks::total 7514109 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2771 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 136848 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1941751 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2081370 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4940 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 264787 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 41807541203 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2949361000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 4314932000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6455391500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13719684500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 3510734000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4990147500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 11205262644 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 19706144144 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 391502000 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1145187000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1151844463 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3582179963 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2639930500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2344251500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2356461463 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7340643463 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029613 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029125 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.027063 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017320 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014181 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014080 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014030 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008348 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.757563 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.719437 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.737707 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.441350 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714658 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.709188 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.740438 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.350719 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061911 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060250 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.062253 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036585 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # 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average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17237.685390 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16413.383683 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35640.681057 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35369.008560 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36290.946712 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35888.457850 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19945.904455 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 21218.820382 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19014.519968 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19862.874247 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31579.868670 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33580.169444 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 39213.517564 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36123.331226 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13068.362374 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13329.108182 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14182.975669 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13706.018367 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1132115000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1164905963 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3578449963 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2628803000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2311656000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2361415963 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7301874963 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033545 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.034905 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.033387 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015293 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015147 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.015678 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009023 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.786633 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.749104 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.773740 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.455115 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714593 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.716273 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.735027 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.347253 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056390 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.056797 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.056239 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.033474 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024830 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025662 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.025185 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.014892 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029201 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030010 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029559 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.017467 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16067.320087 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16496.319661 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17991.717311 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17145.486754 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48252.196622 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48289.929141 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 58904.363645 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53586.650203 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17853.480693 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20002.905196 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 18288.134922 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18687.903355 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39087.215016 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 42167.395301 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 47636.162682 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 44322.971709 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13960.272452 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14615.262060 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15144.563018 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14740.519021 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 47750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 47750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25531.695077 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25275.074202 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 29787.964467 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27566.256738 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24345.058372 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 24484.078495 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28028.862201 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26212.802280 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187083.310192 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 185287.621740 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 181978.707224 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184849.575535 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191229.517982 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 189538.757743 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 184876.362958 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188587.613333 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189081.708984 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 187345.489910 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 183396.704178 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186662.788563 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 15725711 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.971450 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 600346119 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15726223 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 38.174845 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 16734603 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.971494 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 650477960 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16735115 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 38.869046 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 11779377500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.711386 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 2.924757 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 22.726644 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.608663 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934983 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.005712 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.044388 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.014861 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 475.687206 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.486973 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 23.054415 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.742900 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.929077 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.010717 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.045028 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.015123 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 632161102 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 632161102 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 359405675 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 113856976 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 70527941 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 56555527 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 600346119 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 359405675 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 113856976 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 70527941 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 56555527 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 600346119 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 359405675 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 113856976 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 70527941 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 56555527 # number of overall hits -system.cpu0.icache.overall_hits::total 600346119 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5558512 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1673429 # 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number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu3.inst 67287512311 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 143159898311 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 364964187 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 115530405 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 74399493 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 61540717 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 616434802 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 364964187 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 115530405 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 74399493 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 61540717 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 616434802 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 364964187 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 115530405 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 74399493 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 61540717 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 616434802 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015230 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014485 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.052037 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.081006 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015230 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014485 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.052037 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu3.inst 0.081006 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015230 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014485 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.052037 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu3.inst 0.081006 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.724728 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13757.137706 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13497.482004 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8898.173847 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13511.724728 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13757.137706 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13497.482004 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8898.173847 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13511.724728 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13757.137706 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13497.482004 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8898.173847 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 66094 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 684306607 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 684306607 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 399406332 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 123839702 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 74645872 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu3.inst 52586054 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 650477960 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 399406332 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 123839702 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 74645872 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu3.inst 52586054 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 650477960 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 399406332 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12812.047851 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12845.948102 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12763.688775 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1226,69 +1228,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 31829 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 31829 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4517 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23366 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 31825 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 1.131186 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 163.233809 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 31823 99.99% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 42213 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 42213 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6241 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 31075 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 42204 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.853000 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 141.748477 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 42202 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 31825 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 27887 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24957.507082 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21503.440195 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16346.397027 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 27726 99.42% 99.42% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3 0.01% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 135 0.48% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 2 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 12 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 4 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::total 42204 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 37325 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 26882.732753 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 23412.636165 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 18338.779624 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 37004 99.14% 99.14% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.01% 99.15% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 275 0.74% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 7 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 19 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 6 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 27887 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2390831336 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.421124 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1006835500 -42.11% -42.11% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -3397666836 142.11% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2390831336 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 23366 83.80% 83.80% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4517 16.20% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 27883 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31829 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 37325 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2908388356 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.649897 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.477002 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1018236500 35.01% 35.01% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1890151856 64.99% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2908388356 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 31075 83.28% 83.28% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6241 16.72% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 37316 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 42213 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31829 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27883 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 42213 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 37316 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27883 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 59712 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 37316 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 79529 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 22434815 # DTB read hits -system.cpu1.dtb.read_misses 24397 # DTB read misses -system.cpu1.dtb.write_hits 18279230 # DTB write hits -system.cpu1.dtb.write_misses 7432 # DTB write misses -system.cpu1.dtb.flush_tlb 1208 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 23441762 # DTB read hits +system.cpu1.dtb.read_misses 32033 # DTB read misses +system.cpu1.dtb.write_hits 21401339 # DTB write hits +system.cpu1.dtb.write_misses 10180 # DTB write misses +system.cpu1.dtb.flush_tlb 1255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5264 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 133 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 18079 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 6610 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 20769 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 971 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1303 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2561 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 22459212 # DTB read accesses -system.cpu1.dtb.write_accesses 18286662 # DTB write accesses +system.cpu1.dtb.perms_faults 2968 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 23473795 # DTB read accesses +system.cpu1.dtb.write_accesses 21411519 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 40714045 # DTB hits -system.cpu1.dtb.misses 31829 # DTB misses -system.cpu1.dtb.accesses 40745874 # DTB accesses +system.cpu1.dtb.hits 44843101 # DTB hits +system.cpu1.dtb.misses 42213 # DTB misses +system.cpu1.dtb.accesses 44885314 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1318,131 +1320,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 20237 # Table walker walks requested -system.cpu1.itb.walker.walksLong 20237 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 921 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17876 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 20237 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 20237 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 20237 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 18797 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28270.362292 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25022.223556 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18368.247187 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 18619 99.05% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 2 0.01% 99.06% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 152 0.81% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 5 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 18797 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 21791 # Table walker walks requested +system.cpu1.itb.walker.walksLong 21791 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1072 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 19067 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 21791 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 21791 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 21791 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 20139 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 29400.094344 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25404.974001 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 23277.059653 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 19797 98.30% 98.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 293 1.45% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 9 0.04% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.10% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 20139 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 17876 95.10% 95.10% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 921 4.90% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 18797 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 19067 94.68% 94.68% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1072 5.32% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 20139 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20237 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20237 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 21791 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 21791 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18797 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18797 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 39034 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 115530405 # ITB inst hits -system.cpu1.itb.inst_misses 20237 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 20139 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 20139 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 41930 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 125648425 # ITB inst hits +system.cpu1.itb.inst_misses 21791 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1208 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5264 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 133 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13570 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 6610 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 15047 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 115550642 # ITB inst accesses -system.cpu1.itb.hits 115530405 # DTB hits -system.cpu1.itb.misses 20237 # DTB misses -system.cpu1.itb.accesses 115550642 # DTB accesses -system.cpu1.numCycles 1208095250 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 125670216 # ITB inst accesses +system.cpu1.itb.hits 125648425 # DTB hits +system.cpu1.itb.misses 21791 # DTB misses +system.cpu1.itb.accesses 125670216 # DTB accesses +system.cpu1.numCycles 1254117353 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 115450057 # Number of instructions committed -system.cpu1.committedOps 134166441 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 122283306 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 117326 # Number of float alu accesses -system.cpu1.num_func_calls 6388598 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 19121650 # number of instructions that are conditional controls -system.cpu1.num_int_insts 122283306 # number of integer instructions -system.cpu1.num_fp_insts 117326 # number of float instructions -system.cpu1.num_int_register_reads 174904532 # number of times the integer registers were read -system.cpu1.num_int_register_writes 96587788 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 193112 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 90280 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 31170492 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 31100176 # number of times the CC registers were written -system.cpu1.num_mem_refs 40711221 # number of memory refs -system.cpu1.num_load_insts 22433949 # Number of load instructions -system.cpu1.num_store_insts 18277272 # Number of store instructions -system.cpu1.num_idle_cycles 1181365230.793780 # Number of idle cycles -system.cpu1.num_busy_cycles 26730019.206220 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022126 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977874 # Percentage of idle cycles -system.cpu1.Branches 27316623 # Number of branches fetched +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 125557631 # Number of instructions committed +system.cpu1.committedOps 147479999 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 135255426 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 113335 # Number of float alu accesses +system.cpu1.num_func_calls 7243553 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 19326205 # number of instructions that are conditional controls +system.cpu1.num_int_insts 135255426 # number of integer instructions +system.cpu1.num_fp_insts 113335 # number of float instructions +system.cpu1.num_int_register_reads 197658337 # number of times the integer registers were read +system.cpu1.num_int_register_writes 107430286 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 186014 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 88856 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 33354822 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 33290251 # number of times the CC registers were written +system.cpu1.num_mem_refs 44840861 # number of memory refs +system.cpu1.num_load_insts 23441337 # Number of load instructions +system.cpu1.num_store_insts 21399524 # Number of store instructions +system.cpu1.num_idle_cycles 1222996834.683689 # Number of idle cycles +system.cpu1.num_busy_cycles 31120518.316311 # Number of busy cycles +system.cpu1.not_idle_fraction 0.024815 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.975185 # Percentage of idle cycles +system.cpu1.Branches 28029112 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 93240195 69.45% 69.45% # Class of executed instruction -system.cpu1.op_class::IntMult 272528 0.20% 69.66% # Class of executed instruction -system.cpu1.op_class::IntDiv 10833 0.01% 69.67% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 11970 0.01% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction -system.cpu1.op_class::MemRead 22433949 16.71% 86.39% # Class of executed instruction -system.cpu1.op_class::MemWrite 18277272 13.61% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 102409853 69.40% 69.40% # Class of executed instruction +system.cpu1.op_class::IntMult 296498 0.20% 69.60% # Class of executed instruction +system.cpu1.op_class::IntDiv 11247 0.01% 69.61% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 12292 0.01% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::MemRead 23441337 15.88% 85.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 21399524 14.50% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 134246789 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 43822181 # Number of BP lookups -system.cpu2.branchPred.condPredicted 31010848 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2006659 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 32869256 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 23105809 # Number of BTB hits +system.cpu1.op_class::total 147570793 # Class of executed instruction +system.cpu2.branchPred.lookups 45471146 # Number of BP lookups +system.cpu2.branchPred.condPredicted 31973875 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2129408 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 32992156 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 23695609 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 70.296112 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4850903 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 329695 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.821948 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 5443991 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 364384 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1472,60 +1474,61 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 93863 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 93863 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6661 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29634 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 93863 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 93863 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 93863 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 36295 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 24894.765119 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 21575.810526 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 16144.893393 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 36098 99.46% 99.46% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.46% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 162 0.45% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 6 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 14 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 6 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 36295 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 113177 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 113177 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 8706 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 39954 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 113177 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 113177 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 113177 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 48660 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 26968.937526 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 23542.983422 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 19014.556180 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 48252 99.16% 99.16% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 346 0.71% 99.87% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 19 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 9 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 17 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 48660 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000225500 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000225500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000225500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 29634 81.65% 81.65% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 6661 18.35% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 36295 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93863 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 39954 82.11% 82.11% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 8706 17.89% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 48660 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 113177 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93863 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36295 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 113177 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 48660 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36295 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 130158 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 48660 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 161837 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 31221716 # DTB read hits -system.cpu2.dtb.read_misses 78321 # DTB read misses -system.cpu2.dtb.write_hits 24527548 # DTB write hits -system.cpu2.dtb.write_misses 15542 # DTB write misses -system.cpu2.dtb.flush_tlb 1208 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 32304432 # DTB read hits +system.cpu2.dtb.read_misses 94453 # DTB read misses +system.cpu2.dtb.write_hits 28220489 # DTB write hits +system.cpu2.dtb.write_misses 18724 # DTB write misses +system.cpu2.dtb.flush_tlb 1254 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 6877 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 171 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 21789 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 75 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2014 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 8683 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 195 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 25531 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 2547 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3746 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 31300037 # DTB read accesses -system.cpu2.dtb.write_accesses 24543090 # DTB write accesses +system.cpu2.dtb.perms_faults 4198 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 32398885 # DTB read accesses +system.cpu2.dtb.write_accesses 28239213 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 55749264 # DTB hits -system.cpu2.dtb.misses 93863 # DTB misses -system.cpu2.dtb.accesses 55843127 # DTB accesses +system.cpu2.dtb.hits 60524921 # DTB hits +system.cpu2.dtb.misses 113177 # DTB misses +system.cpu2.dtb.accesses 60638098 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1555,85 +1558,86 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 27202 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27202 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1812 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22525 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27202 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27202 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27202 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 24337 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 28096.416978 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 24969.362897 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 17267.916673 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 12983 53.35% 53.35% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 11116 45.68% 99.02% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 182 0.75% 99.77% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 36 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 10 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 4 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 24337 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 29761 # Table walker walks requested +system.cpu2.itb.walker.walksLong 29761 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1942 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 24191 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 29761 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 29761 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 29761 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 26133 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 29367.313359 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 25512.670377 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 21362.014142 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 13922 53.27% 53.27% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 11740 44.92% 98.20% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 1 0.00% 98.20% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 361 1.38% 99.58% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 66 0.25% 99.84% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 6 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 20 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 6 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::393216-425983 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 26133 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 22525 92.55% 92.55% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1812 7.45% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 24337 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 24191 92.57% 92.57% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1942 7.43% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 26133 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27202 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27202 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 29761 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 29761 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24337 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24337 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 51539 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 74458235 # ITB inst hits -system.cpu2.itb.inst_misses 27202 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 26133 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 26133 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 55894 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 78881959 # ITB inst hits +system.cpu2.itb.inst_misses 29761 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1208 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1254 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 6877 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 171 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 16288 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 8683 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 195 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 18937 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 55804 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 67145 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 74485437 # ITB inst accesses -system.cpu2.itb.hits 74458235 # DTB hits -system.cpu2.itb.misses 27202 # DTB misses -system.cpu2.itb.accesses 74485437 # DTB accesses -system.cpu2.numCycles 6814615454 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 78911720 # ITB inst accesses +system.cpu2.itb.hits 78881959 # DTB hits +system.cpu2.itb.misses 29761 # DTB misses +system.cpu2.itb.accesses 78911720 # DTB accesses +system.cpu2.numCycles 7033284242 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 154831636 # Number of instructions committed -system.cpu2.committedOps 179800875 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 13497272 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1503 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 95900032594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 44.013069 # CPI: cycles per instruction -system.cpu2.ipc 0.022721 # IPC: instructions per cycle +system.cpu2.committedInsts 166119965 # Number of instructions committed +system.cpu2.committedOps 194630787 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 16695727 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1592 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 95760838731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 42.338585 # CPI: cycles per instruction +system.cpu2.ipc 0.023619 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 289096275 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 6525519179 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 86474104 # Number of BP lookups -system.cpu3.branchPred.condPredicted 60464005 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3334878 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 62765880 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 44403586 # Number of BTB hits +system.cpu2.tickCycles 311878847 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 6721405395 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 81889340 # Number of BP lookups +system.cpu3.branchPred.condPredicted 56169669 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3380866 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 55493963 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 40219158 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 70.744784 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9643745 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 102837 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 72.474835 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 10439836 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 109057 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1663,86 +1667,90 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 507978 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 507978 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8239 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50131 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 318118 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 189860 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2312.543453 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 14225.767965 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-65535 188735 99.41% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-131071 609 0.32% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-196607 339 0.18% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-262143 67 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-327679 60 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-393215 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::458752-524287 13 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 189860 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 237967 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 22746.445936 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18445.918313 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 18699.946785 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 233152 97.98% 97.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3733 1.57% 99.55% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 782 0.33% 99.87% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 40 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 125 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 78 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 40 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 237967 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -31430994140 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.113026 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -32002753640 101.82% 101.82% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 312906500 -1.00% 100.82% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 109321000 -0.35% 100.48% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 69521000 -0.22% 100.25% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 26278000 -0.08% 100.17% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 15239000 -0.05% 100.12% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 14010000 -0.04% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 20193000 -0.06% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 4061500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 204000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 20000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 4000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::48-51 1500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -31430994140 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 50131 85.88% 85.88% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8239 14.12% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 58370 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 507978 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 587832 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 587832 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 11030 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 61410 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 367052 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 220780 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2589.344596 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 16088.611072 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-65535 219110 99.24% 99.24% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-131071 781 0.35% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-196607 609 0.28% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-262143 97 0.04% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-327679 110 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-393215 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-458751 21 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-524287 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 220780 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 282413 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 23694.059764 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 19376.224176 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 20061.278653 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-65535 276792 98.01% 98.01% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3971 1.41% 99.42% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-196607 1088 0.39% 99.80% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-262143 102 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-327679 289 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-393215 71 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-458751 75 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-524287 16 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 282413 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -34655191100 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean -0.302186 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -35339735100 101.98% 101.98% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 378573500 -1.09% 100.88% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 130659500 -0.38% 100.51% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 81429500 -0.23% 100.27% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 31558000 -0.09% 100.18% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 16139000 -0.05% 100.13% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 19404500 -0.06% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 22341500 -0.06% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 4213500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 186000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 24000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 5000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::48-51 6000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::52-55 2500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::56-59 1500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -34655191100 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 61410 84.77% 84.77% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 11030 15.23% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 72440 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 587832 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 507978 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58370 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 587832 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 72440 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58370 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 566348 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 72440 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 660272 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 67144172 # DTB read hits -system.cpu3.dtb.read_misses 346038 # DTB read misses -system.cpu3.dtb.write_hits 45597024 # DTB write hits -system.cpu3.dtb.write_misses 161940 # DTB write misses -system.cpu3.dtb.flush_tlb 1207 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 65734744 # DTB read hits +system.cpu3.dtb.read_misses 407673 # DTB read misses +system.cpu3.dtb.write_hits 50830095 # DTB write hits +system.cpu3.dtb.write_misses 180159 # DTB write misses +system.cpu3.dtb.flush_tlb 1253 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 10894 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 329 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 30283 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 73 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 13974 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 340 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 34753 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 86 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 6443 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 33322 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 67490210 # DTB read accesses -system.cpu3.dtb.write_accesses 45758964 # DTB write accesses +system.cpu3.dtb.perms_faults 35079 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 66142417 # DTB read accesses +system.cpu3.dtb.write_accesses 51010254 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 112741196 # DTB hits -system.cpu3.dtb.misses 507978 # DTB misses -system.cpu3.dtb.accesses 113249174 # DTB accesses +system.cpu3.dtb.hits 116564839 # DTB hits +system.cpu3.dtb.misses 587832 # DTB misses +system.cpu3.dtb.accesses 117152671 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1772,395 +1780,391 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 60738 # Table walker walks requested -system.cpu3.itb.walker.walksLong 60738 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1986 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 42002 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8255 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 52483 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1658.003544 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 10682.399901 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 51962 99.01% 99.01% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 312 0.59% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 51 0.10% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 42 0.08% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 81 0.15% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 17 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::393216-425983 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 52483 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 52243 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 29328.072660 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 24939.652289 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 21269.473767 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-32767 27773 53.16% 53.16% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-65535 23452 44.89% 98.05% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-98303 257 0.49% 98.54% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::98304-131071 44 0.08% 98.63% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-163839 455 0.87% 99.50% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::163840-196607 157 0.30% 99.80% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::294912-327679 13 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 52243 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -31433784640 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.872286 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.329149 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -3971528800 12.63% 12.63% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -27500486840 87.49% 100.12% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 33846500 -0.11% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 4000500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 384000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -31433784640 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 42002 95.49% 95.49% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 1986 4.51% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 43988 # Table walker page sizes translated +system.cpu3.itb.walker.walks 63234 # Table walker walks requested +system.cpu3.itb.walker.walksLong 63234 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2096 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 42908 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8590 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 54644 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 2021.164263 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 13009.185259 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 53981 98.79% 98.79% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 301 0.55% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 60 0.11% 99.45% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 76 0.14% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 174 0.32% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 22 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 8 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-294911 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 54644 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 53594 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 30266.951524 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 25142.604210 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 25912.141235 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-65535 52174 97.35% 97.35% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-131071 327 0.61% 97.96% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-196607 902 1.68% 99.64% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-262143 65 0.12% 99.76% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-327679 86 0.16% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-393215 19 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::393216-458751 14 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 53594 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -34657916600 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.961535 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.183175 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -1283225616 3.70% 3.70% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -33417551984 96.42% 100.12% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 37526500 -0.11% 100.02% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 4293000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 605000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 220500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::6 216000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -34657916600 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 42908 95.34% 95.34% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 2096 4.66% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 45004 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60738 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60738 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 63234 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 63234 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43988 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43988 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 104726 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 61673296 # ITB inst hits -system.cpu3.itb.inst_misses 60738 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 45004 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 45004 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 108238 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 57820095 # ITB inst hits +system.cpu3.itb.inst_misses 63234 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1207 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1253 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 10894 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 329 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 23902 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 13974 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 340 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 26508 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 114610 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 125417 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 61734034 # ITB inst accesses -system.cpu3.itb.hits 61673296 # DTB hits -system.cpu3.itb.misses 60738 # DTB misses -system.cpu3.itb.accesses 61734034 # DTB accesses -system.cpu3.numCycles 387266719 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 57883329 # ITB inst accesses +system.cpu3.itb.hits 57820095 # DTB hits +system.cpu3.itb.misses 63234 # DTB misses +system.cpu3.itb.accesses 57883329 # DTB accesses +system.cpu3.numCycles 434126905 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 147097588 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 357588328 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 86474104 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 54047331 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 217420350 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7531775 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1493858 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 6577 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 1847 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 2904102 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 100892 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 5652 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 61540793 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2049174 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 24233 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 372796591 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.109243 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.309692 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 146156253 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 363700570 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 81889340 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 50658994 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 264117346 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7731870 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1657260 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 10621 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 2103 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 3389024 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 101744 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 6028 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 57676698 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2068277 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 25207 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 419306139 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.016419 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.270112 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 281372813 75.48% 75.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 14372234 3.86% 79.33% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10265019 2.75% 82.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7499968 2.01% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 21772422 5.84% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5084969 1.36% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5491693 1.47% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4844554 1.30% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 22092919 5.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 329556532 78.60% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 11088732 2.64% 81.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 11228658 2.68% 83.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 8092801 1.93% 85.85% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 18140495 4.33% 90.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5492721 1.31% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 6039069 1.44% 92.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 5230958 1.25% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 24436173 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 372796591 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.223293 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.923364 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 121849508 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 170403265 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 70427838 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7160823 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2953176 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 13216170 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 824708 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 387980290 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2540688 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 2953176 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 125989175 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14295648 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 134676071 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 73352513 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 21527795 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 379587949 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 66831 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1271643 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 1003345 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 11147601 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2215 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 363999702 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 575721975 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 441176724 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 501598 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 310075973 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 53923724 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 7927696 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 6812130 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 39656771 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 65059563 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 47956782 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7328499 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 8072218 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 362054747 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7911785 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 361524933 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 476222 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 45084510 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 28958350 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 197452 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 372796591 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.969765 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.646815 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 419306139 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.188630 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.837775 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 117967967 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 225080995 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 64189505 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 9003410 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 3062237 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 11922856 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 815112 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 398264937 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2526332 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 3062237 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 122799246 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 19956782 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 172569750 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 68252780 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 32663221 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 389247398 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 82681 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1469691 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 1381042 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 19259922 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2209 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 374365889 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 605949673 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 460740509 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 465469 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 317859037 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 56506847 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 10256222 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 9051847 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 50890020 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 62384560 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 53396526 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 8272508 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 8814741 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 368973435 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 10287007 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 371458257 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 527403 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 47542551 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 30606523 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 220793 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 419306139 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.885888 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.625743 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 227072164 60.91% 60.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 63499277 17.03% 77.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 26503560 7.11% 85.05% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 19490025 5.23% 90.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 15060105 4.04% 94.32% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9087170 2.44% 96.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6095598 1.64% 98.39% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3610933 0.97% 99.36% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2377759 0.64% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 272370865 64.96% 64.96% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 63755387 15.20% 80.16% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 26527410 6.33% 86.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 18802792 4.48% 90.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 14265193 3.40% 94.38% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9871415 2.35% 96.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6899561 1.65% 98.38% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 4083667 0.97% 99.35% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2729849 0.65% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 372796591 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 419306139 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1687705 25.88% 25.88% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 16239 0.25% 26.13% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1469 0.02% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.15% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2644056 40.55% 66.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2171786 33.30% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1874044 25.07% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 14207 0.19% 25.26% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1529 0.02% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 3115796 41.69% 66.97% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2468334 33.03% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 19 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 246126710 68.08% 68.08% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 787460 0.22% 68.30% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 40199 0.01% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 173 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 43036 0.01% 68.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 68327195 18.90% 87.22% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 46200141 12.78% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 252023231 67.85% 67.85% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 873366 0.24% 68.08% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 40952 0.01% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 37311 0.01% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 67010678 18.04% 86.14% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 51472700 13.86% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 361524933 # Type of FU issued -system.cpu3.iq.rate 0.933530 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6521255 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.018038 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1102172941 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 415098174 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 349515725 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 670993 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 333176 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 300023 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 367687576 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 358593 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2643676 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 371458257 # Type of FU issued +system.cpu3.iq.rate 0.855644 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 7473910 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.020120 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1169596628 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 426913403 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 357682131 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 627338 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 312499 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 278370 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 378596824 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 335324 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2893628 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9059982 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 11985 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 386621 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4959688 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 9605329 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 12315 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 430621 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 5363996 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2122346 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 4168343 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2422339 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 5589935 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2953176 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 9025973 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 4011376 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 370041408 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1020577 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 65059563 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 47956782 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6665282 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 121223 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 3842845 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 386621 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1507009 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1322517 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2829526 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 357707316 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 67134694 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3315560 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 3062237 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 10687906 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 7763233 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 379342357 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1032736 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 62384560 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 53396526 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 8880600 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 160790 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 7539596 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 430621 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1536012 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1351234 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2887246 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 367483062 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 65729081 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3395466 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 74876 # number of nop insts executed -system.cpu3.iew.exec_refs 112730172 # number of memory reference insts executed -system.cpu3.iew.exec_branches 73596465 # Number of branches executed -system.cpu3.iew.exec_stores 45595478 # Number of stores executed -system.cpu3.iew.exec_rate 0.923672 # Inst execution rate -system.cpu3.iew.wb_sent 350496089 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 349815748 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 170914672 # num instructions producing a value -system.cpu3.iew.wb_consumers 300090920 # num instructions consuming a value +system.cpu3.iew.exec_nop 81915 # number of nop insts executed +system.cpu3.iew.exec_refs 116559779 # number of memory reference insts executed +system.cpu3.iew.exec_branches 68181123 # Number of branches executed +system.cpu3.iew.exec_stores 50830698 # Number of stores executed +system.cpu3.iew.exec_rate 0.846488 # Inst execution rate +system.cpu3.iew.wb_sent 358682036 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 357960501 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 176824720 # num instructions producing a value +system.cpu3.iew.wb_consumers 308531947 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.903294 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.569543 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.824553 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.573116 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 45110535 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7714333 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2522004 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 365126198 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.889780 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.821639 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 47576745 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 10066214 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2576993 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 411229636 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.806649 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.806100 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 241067877 66.02% 66.02% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 60177968 16.48% 82.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 23030537 6.31% 88.81% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 12678452 3.47% 92.28% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6124253 1.68% 93.96% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3724103 1.02% 94.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3468414 0.95% 95.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2157144 0.59% 96.52% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12697450 3.48% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 288483917 70.15% 70.15% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 61981955 15.07% 85.22% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 20267968 4.93% 90.15% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 9217498 2.24% 92.39% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6652848 1.62% 94.01% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 4003479 0.97% 94.99% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3757671 0.91% 95.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2541712 0.62% 96.52% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 14322588 3.48% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 365126198 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 280963321 # Number of instructions committed -system.cpu3.commit.committedOps 324882017 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 411229636 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 282128500 # Number of instructions committed +system.cpu3.commit.committedOps 331717886 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 98996674 # Number of memory references committed -system.cpu3.commit.loads 55999580 # Number of loads committed -system.cpu3.commit.membars 1980658 # Number of memory barriers committed -system.cpu3.commit.branches 68831058 # Number of branches committed -system.cpu3.commit.fp_insts 288600 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 294637419 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7471816 # Number of function calls committed. +system.cpu3.commit.refs 100811760 # Number of memory references committed +system.cpu3.commit.loads 52779230 # Number of loads committed +system.cpu3.commit.membars 2341382 # Number of memory barriers committed +system.cpu3.commit.branches 63187183 # Number of branches committed +system.cpu3.commit.fp_insts 266447 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 304028105 # Number of committed integer instructions. +system.cpu3.commit.function_calls 8134067 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 225203928 69.32% 69.32% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 613924 0.19% 69.51% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 30363 0.01% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 37128 0.01% 69.53% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 55999580 17.24% 86.77% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 42997094 13.23% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 230158153 69.38% 69.38% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 685246 0.21% 69.59% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 30654 0.01% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.60% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 32073 0.01% 69.61% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 52779230 15.91% 85.52% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 48032530 14.48% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 324882017 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12697450 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 720404728 # The number of ROB reads -system.cpu3.rob.rob_writes 747667993 # The number of ROB writes -system.cpu3.timesIdled 2347863 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 14470128 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98704132703 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 280963321 # Number of Instructions Simulated -system.cpu3.committedOps 324882017 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.378353 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.378353 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.725503 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.725503 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 414317420 # number of integer regfile reads -system.cpu3.int_regfile_writes 245959017 # number of integer regfile writes -system.cpu3.fp_regfile_reads 580593 # number of floating regfile reads -system.cpu3.fp_regfile_writes 365724 # number of floating regfile writes -system.cpu3.cc_regfile_reads 82484676 # number of cc regfile reads -system.cpu3.cc_regfile_writes 83140356 # number of cc regfile writes -system.cpu3.misc_regfile_reads 708702435 # number of misc regfile reads -system.cpu3.misc_regfile_writes 7780128 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40264 # Transaction distribution -system.iobus.trans_dist::ReadResp 40264 # Transaction distribution -system.iobus.trans_dist::WriteReq 136539 # Transaction distribution -system.iobus.trans_dist::WriteResp 136539 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) +system.cpu3.commit.op_class_0::total 331717886 # Class of committed instruction +system.cpu3.commit.bw_lim_events 14322588 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 773873016 # The number of ROB reads +system.cpu3.rob.rob_writes 766677768 # The number of ROB writes +system.cpu3.timesIdled 2386400 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 14820766 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98598665590 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 282128500 # Number of Instructions Simulated +system.cpu3.committedOps 331717886 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.538756 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.538756 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.649876 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.649876 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 433777374 # number of integer regfile reads +system.cpu3.int_regfile_writes 254753352 # number of integer regfile writes +system.cpu3.fp_regfile_reads 550692 # number of floating regfile reads +system.cpu3.fp_regfile_writes 344140 # number of floating regfile writes +system.cpu3.cc_regfile_reads 80727735 # number of cc regfile reads +system.cpu3.cc_regfile_writes 81413298 # number of cc regfile writes +system.cpu3.misc_regfile_reads 763399482 # number of misc regfile reads +system.cpu3.misc_regfile_writes 10252205 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40277 # Transaction distribution +system.iobus.trans_dist::ReadResp 40277 # Transaction distribution +system.iobus.trans_dist::WriteReq 136543 # Transaction distribution +system.iobus.trans_dist::WriteResp 136543 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47710 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2175,13 +2179,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122592 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353606 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353640 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47730 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2196,13 +2200,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155722 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 27822000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 27944000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2218,7 +2222,7 @@ system.iobus.reqLayer16.occupancy 4000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 10208000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 9762000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 84000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2226,64 +2230,64 @@ system.iobus.reqLayer25.occupancy 18725000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 258644416 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 256543158 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 58071000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 57567000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 75528000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 67102000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.429241 # Cycle average of tags in use +system.iocache.tags.replacements 115465 # number of replacements +system.iocache.tags.tagsinuse 10.434887 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089149965509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.541829 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.887412 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221364 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430463 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651828 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13089149976509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.535229 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.899658 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220952 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.431229 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652180 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039632 # Number of tag accesses -system.iocache.tags.data_accesses 1039632 # Number of data accesses +system.iocache.tags.tag_accesses 1039713 # Number of tag accesses +system.iocache.tags.data_accesses 1039713 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses -system.iocache.demand_misses::total 8851 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8820 # number of demand (read+write) misses +system.iocache.demand_misses::total 8860 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8811 # number of overall misses -system.iocache.overall_misses::total 8851 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 1063595797 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1063595797 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 6255460619 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6255460619 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 1063595797 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1063595797 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 1063595797 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1063595797 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8820 # number of overall misses +system.iocache.overall_misses::total 8860 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 731246845 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 731246845 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 6288189313 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6288189313 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 731246845 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 731246845 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 731246845 # number of overall miss cycles +system.iocache.overall_miss_latency::total 731246845 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8820 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8860 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8820 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8860 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2297,504 +2301,503 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120712.268414 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120207.481578 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58646.409463 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 58646.409463 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120712.268414 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120166.737883 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120712.268414 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120166.737883 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 21718 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 82907.805556 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 82561.459298 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58953.248641 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 58953.248641 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 82907.805556 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 82533.503950 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 82907.805556 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 82533.503950 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 14483 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2281 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1449 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.521263 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.995169 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 5692 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 5692 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 48208 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 48208 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 5692 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 5692 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 5692 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 5692 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 778995797 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 778995797 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3845060619 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3845060619 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 778995797 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 778995797 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 778995797 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 778995797 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.646011 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.643309 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.451961 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.451961 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.646011 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.643091 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.646011 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.643091 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136858.010717 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136858.010717 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79759.803746 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79759.803746 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136858.010717 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 136858.010717 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136858.010717 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 136858.010717 # average overall mshr miss latency +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 3943 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 3943 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 48464 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 48464 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 3943 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 3943 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 3943 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 3943 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 534096845 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 534096845 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3864989313 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3864989313 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 534096845 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 534096845 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 534096845 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 534096845 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.447052 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.445185 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.454361 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.454361 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.447052 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.445034 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.447052 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.445034 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135454.436977 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135454.436977 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79749.696950 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79749.696950 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 135454.436977 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 135454.436977 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 135454.436977 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 135454.436977 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1132465 # number of replacements -system.l2c.tags.tagsinuse 65345.559033 # Cycle average of tags in use -system.l2c.tags.total_refs 47267039 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1194837 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 39.559404 # Average number of references to valid blocks. +system.l2c.tags.replacements 1727571 # number of replacements +system.l2c.tags.tagsinuse 65366.434127 # Cycle average of tags in use +system.l2c.tags.total_refs 52377191 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1790828 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.247472 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36744.660878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 142.976738 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 207.950665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3526.912344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7879.628728 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 32.983136 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 50.156100 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 446.637594 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2137.524308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 40.708096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 63.118554 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1712.703333 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4298.761220 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 72.536021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 107.587322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2740.040104 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 5140.673890 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.560679 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.053816 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.120234 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000503 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000765 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.006815 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.032616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000621 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000963 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.026134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.065594 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001107 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.001642 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.041810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.078440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997094 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62115 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 256 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 536 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5067 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53597 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.947800 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 418375193 # Number of tag accesses -system.l2c.tags.data_accesses 418375193 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 157165 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 108147 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 56056 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 42111 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 150625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 56479 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 293742 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 112761 # number of ReadReq hits -system.l2c.ReadReq_hits::total 977086 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7514109 # number of Writeback hits -system.l2c.Writeback_hits::total 7514109 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3816 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1269 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1617 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2624 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9326 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 644415 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 197919 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 264521 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 475053 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1581908 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 5524345 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 1666372 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 3847940 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 4592920 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15631577 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 2467130 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 795993 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 1072744 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 1878580 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6214447 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 282634 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 93077 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu2.data 123933 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu3.data 234442 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 734086 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 157165 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 108147 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 5524345 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3111545 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 56056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 42111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1666372 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 993912 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 150625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 56479 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 3847940 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 1337265 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 293742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 112761 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 4592920 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 2353633 # number of demand (read+write) hits -system.l2c.demand_hits::total 24405018 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 157165 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 108147 # number of overall hits -system.l2c.overall_hits::cpu0.inst 5524345 # number of overall hits -system.l2c.overall_hits::cpu0.data 3111545 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 56056 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 42111 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1666372 # number of overall hits -system.l2c.overall_hits::cpu1.data 993912 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 150625 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 56479 # number of overall hits -system.l2c.overall_hits::cpu2.inst 3847940 # number of overall hits -system.l2c.overall_hits::cpu2.data 1337265 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 293742 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 112761 # number of overall hits -system.l2c.overall_hits::cpu3.inst 4592920 # number of overall hits -system.l2c.overall_hits::cpu3.data 2353633 # number of overall hits -system.l2c.overall_hits::total 24405018 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1348 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1487 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 300 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 451 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 385 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.dtb.walker 975 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.itb.walker 936 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6197 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 13894 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4437 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 5893 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 9463 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 33687 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.tags.occ_blocks::writebacks 35675.383365 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 150.314968 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 221.842308 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3453.336849 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8628.573919 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 25.870351 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 46.456847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 201.612441 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2287.318567 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 59.687727 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 74.075629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1384.134493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3678.892327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 90.341060 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 136.749974 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2263.424269 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 6988.419034 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.544363 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002294 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003385 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.052694 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.131662 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000395 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.034902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000911 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.001130 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.021120 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.056135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001378 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.itb.walker 0.002087 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.034537 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.106635 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997413 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62986 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 271 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 557 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2824 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5088 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54403 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004135 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.961090 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 469232047 # Number of tag accesses +system.l2c.tags.data_accesses 469232047 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 235826 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 121184 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 81459 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 45184 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 191869 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 62064 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 348446 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 115721 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1201753 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8924778 # number of Writeback hits +system.l2c.Writeback_hits::total 8924778 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 4561 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1493 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 2040 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 3109 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11203 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu3.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 686392 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 217346 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 284271 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3.data 485127 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1673136 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 5986561 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 1802233 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 4138498 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 4701144 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 16628436 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3068738 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 952648 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 1326974 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 2219552 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 7567912 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 272293 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 86845 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu2.data 121922 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu3.data 214200 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 695260 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 235826 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 121184 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 5986561 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 3755130 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 81459 # 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average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70729.635539 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 72000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121182.109143 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122421.302905 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 136798.395569 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 129026.681942 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121056.256200 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123896.048619 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125624.131799 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124416.316642 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123670.088543 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124921.835244 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 130791.787725 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127817.814428 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120805.864146 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 129234.810101 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 145863.890621 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 136683.359554 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127435 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127687.301587 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121056.256200 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122072.584105 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 127083.148559 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 128323.376623 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123896.048619 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123460.407997 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 129259.506680 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 126622.294372 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125624.131799 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134141.067640 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 127918.422302 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127435 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127687.301587 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121056.256200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122072.584105 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 127083.148559 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 128323.376623 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123896.048619 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123460.407997 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 129259.506680 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 126622.294372 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125624.131799 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134141.067640 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 127918.422302 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174237.698139 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 171885.668153 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169548.511410 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171964.147239 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179316.406830 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 176961.405530 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 173916.934965 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 176801.004048 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 176682.666190 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 174337.387710 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 171663.769585 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 174299.583735 # average overall mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121397.901159 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122864.802280 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 144150.417161 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 133698.001015 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121453.775039 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123730.722737 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126131.350741 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124651.738185 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123815.452615 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125190.616827 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 130971.148357 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127990.560847 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 121341.477024 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 130927.512718 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 147640.760141 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 137669.293940 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121453.775039 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122063.958913 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123730.722737 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123615.671363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126131.350741 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 140112.298070 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 131246.239664 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121453.775039 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122063.958913 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123730.722737 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123615.671363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126131.350741 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 140112.298070 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 131246.239664 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174583.310192 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 172786.914860 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169478.707224 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172349.352132 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179729.517982 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178025.447849 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 173370.576099 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177081.501976 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177063.691290 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 175322.757112 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 171383.232370 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 174644.779897 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76740 # Transaction distribution -system.membus.trans_dist::ReadResp 434267 # Transaction distribution -system.membus.trans_dist::WriteReq 33649 # Transaction distribution -system.membus.trans_dist::WriteResp 33649 # Transaction distribution -system.membus.trans_dist::Writeback 1051076 # Transaction distribution -system.membus.trans_dist::CleanEvict 194214 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34391 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34393 # Transaction distribution -system.membus.trans_dist::ReadExReq 878752 # Transaction distribution -system.membus.trans_dist::ReadExResp 878752 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 357527 # Transaction distribution +system.membus.trans_dist::ReadReq 76751 # Transaction distribution +system.membus.trans_dist::ReadResp 550767 # Transaction distribution +system.membus.trans_dist::WriteReq 33656 # Transaction distribution +system.membus.trans_dist::WriteResp 33656 # Transaction distribution +system.membus.trans_dist::Writeback 1590295 # Transaction distribution +system.membus.trans_dist::CleanEvict 250132 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40589 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40592 # Transaction distribution +system.membus.trans_dist::ReadExReq 1356297 # Transaction distribution +system.membus.trans_dist::ReadExResp 1356297 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 474016 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122592 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3747318 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3876721 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4219049 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5542839 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5672278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6014819 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155722 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13532 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139182816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 139352250 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7292736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7292736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 146644986 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1691 # Total snoops (count) -system.membus.snoop_fanout::samples 2735655 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 211708448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 211877938 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7303680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7303680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 219181618 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1560 # Total snoops (count) +system.membus.snoop_fanout::samples 3931023 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2735655 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3931023 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2735655 # Request fanout histogram -system.membus.reqLayer0.occupancy 67480499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3931023 # Request fanout histogram +system.membus.reqLayer0.occupancy 67063498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1687500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3012404078 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 4875978841 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2789968901 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4492458378 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 111926505 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 103510165 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3188,60 +3191,60 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 51428395 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26044342 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3013 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2333 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 57525316 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 29151092 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3060 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2399 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2399 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1485574 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23674636 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33649 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33649 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7959451 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 17972959 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43013 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43018 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1971030 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1971030 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15726300 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6468003 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1272625 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1224417 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47261977 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29193320 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 817918 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1719148 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 78992363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006650324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1020855654 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2953520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6072336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2036531834 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1644943 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 53692689 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.011673 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.107408 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1748199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 26397420 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33656 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33656 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 9662082 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 19582233 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51062 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51066 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2478951 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2478951 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16735129 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7917622 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1294933 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1246469 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 50288517 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35153401 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 878892 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2158697 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 88479507 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1071219732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1236530654 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3178896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7750232 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2318679514 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2264699 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 60538896 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.012147 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109543 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 53065946 98.83% 98.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 626743 1.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 59803521 98.79% 98.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 735375 1.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 53692689 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 20600677992 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 60538896 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 23067770487 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 830192 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 767706 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15256484341 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 16065319902 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7870736599 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 9498707196 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 292647751 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 310622695 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 703926527 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 847575032 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |