diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt | 4996 |
1 files changed, 2740 insertions, 2256 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index 4324d934c..25d15fe9a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,173 +1,191 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.235006 # Number of seconds simulated -sim_ticks 51235005618500 # Number of ticks simulated -final_tick 51235005618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.276915 # Number of seconds simulated +sim_ticks 51276914665000 # Number of ticks simulated +final_tick 51276914665000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 299120 # Simulator instruction rate (inst/s) -host_op_rate 351506 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17342892504 # Simulator tick rate (ticks/s) -host_mem_usage 728488 # Number of bytes of host memory used -host_seconds 2954.24 # Real time elapsed on the host -sim_insts 883670074 # Number of instructions simulated -sim_ops 1038432543 # Number of ops (including micro ops) simulated +host_inst_rate 268578 # Simulator instruction rate (inst/s) +host_op_rate 315601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16108564651 # Simulator tick rate (ticks/s) +host_mem_usage 678484 # Number of bytes of host memory used +host_seconds 3183.21 # Real time elapsed on the host +sim_insts 854941205 # Number of instructions simulated +sim_ops 1004625181 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 125376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2934708 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 51720008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 38784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 35712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 741632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9002048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 95296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 86336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 2270528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 22315456 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory -system.physmem.bytes_read::total 89912252 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2934708 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 741632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 2270528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5946868 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77430208 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 83328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 90048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2407092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 43660040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 20288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 19392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 699200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 6175552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 32448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 28928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1537920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 8615616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 64768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 60352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1793920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 16163456 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 420032 # Number of bytes read from this memory +system.physmem.bytes_read::total 81872380 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2407092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 699200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1537920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1793920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6438132 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69681088 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 77450788 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 86262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 808138 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 606 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 11588 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 140657 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 1489 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1349 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 35477 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 348679 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1445299 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1209847 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69701668 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1302 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1407 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 78018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 682201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 96493 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 24030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 134619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 28030 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 252554 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6563 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1319676 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1088767 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1212420 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 57279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1009466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 757 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 175701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 1860 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 1685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 44316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 435551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1754899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 57279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 44316 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 116070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1511275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1511677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1511275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 57279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1009868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 175701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 1860 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 1685 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 44316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 435551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3266576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 540590 # Number of read requests accepted -system.physmem.writeReqs 467319 # Number of write requests accepted -system.physmem.readBursts 540590 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 467319 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 34576064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21696 # Total number of bytes read from write queue -system.physmem.bytesWritten 29908416 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 34597760 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 29908416 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 339 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 1091340 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 46943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 851456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 13636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 120435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 564 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 29992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 168021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 34985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 315219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 46943 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 13636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 29992 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 34985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 125556 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1358917 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1359319 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1358917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 46943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 851857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 13636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 120435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 29992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 168021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 34985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 315219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2955990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 550245 # Number of read requests accepted +system.physmem.writeReqs 481237 # Number of write requests accepted +system.physmem.readBursts 550245 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 481237 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 35190464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 25216 # Total number of bytes read from write queue +system.physmem.bytesWritten 30797568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 35215680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 30799168 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 394 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 52057 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 34722 # Per bank write bursts -system.physmem.perBankRdBursts::1 34925 # Per bank write bursts -system.physmem.perBankRdBursts::2 34806 # Per bank write bursts -system.physmem.perBankRdBursts::3 34433 # Per bank write bursts -system.physmem.perBankRdBursts::4 35553 # Per bank write bursts -system.physmem.perBankRdBursts::5 39917 # Per bank write bursts -system.physmem.perBankRdBursts::6 33295 # Per bank write bursts -system.physmem.perBankRdBursts::7 34606 # Per bank write bursts -system.physmem.perBankRdBursts::8 31417 # Per bank write bursts -system.physmem.perBankRdBursts::9 34834 # Per bank write bursts -system.physmem.perBankRdBursts::10 32861 # Per bank write bursts -system.physmem.perBankRdBursts::11 34723 # Per bank write bursts -system.physmem.perBankRdBursts::12 29445 # Per bank write bursts -system.physmem.perBankRdBursts::13 31855 # Per bank write bursts -system.physmem.perBankRdBursts::14 31705 # Per bank write bursts -system.physmem.perBankRdBursts::15 31154 # Per bank write bursts -system.physmem.perBankWrBursts::0 29588 # Per bank write bursts -system.physmem.perBankWrBursts::1 28520 # Per bank write bursts -system.physmem.perBankWrBursts::2 28987 # Per bank write bursts -system.physmem.perBankWrBursts::3 29728 # Per bank write bursts -system.physmem.perBankWrBursts::4 31002 # Per bank write bursts -system.physmem.perBankWrBursts::5 33624 # Per bank write bursts -system.physmem.perBankWrBursts::6 29096 # Per bank write bursts -system.physmem.perBankWrBursts::7 30620 # Per bank write bursts -system.physmem.perBankWrBursts::8 28064 # Per bank write bursts -system.physmem.perBankWrBursts::9 30877 # Per bank write bursts -system.physmem.perBankWrBursts::10 28622 # Per bank write bursts -system.physmem.perBankWrBursts::11 29758 # Per bank write bursts -system.physmem.perBankWrBursts::12 25484 # Per bank write bursts -system.physmem.perBankWrBursts::13 27499 # Per bank write bursts -system.physmem.perBankWrBursts::14 28130 # Per bank write bursts -system.physmem.perBankWrBursts::15 27720 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 68304 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 35436 # Per bank write bursts +system.physmem.perBankRdBursts::1 39868 # Per bank write bursts +system.physmem.perBankRdBursts::2 34215 # Per bank write bursts +system.physmem.perBankRdBursts::3 34743 # Per bank write bursts +system.physmem.perBankRdBursts::4 34056 # Per bank write bursts +system.physmem.perBankRdBursts::5 38097 # Per bank write bursts +system.physmem.perBankRdBursts::6 32100 # Per bank write bursts +system.physmem.perBankRdBursts::7 33790 # Per bank write bursts +system.physmem.perBankRdBursts::8 31750 # Per bank write bursts +system.physmem.perBankRdBursts::9 37588 # Per bank write bursts +system.physmem.perBankRdBursts::10 34493 # Per bank write bursts +system.physmem.perBankRdBursts::11 35548 # Per bank write bursts +system.physmem.perBankRdBursts::12 32409 # Per bank write bursts +system.physmem.perBankRdBursts::13 32208 # Per bank write bursts +system.physmem.perBankRdBursts::14 31335 # Per bank write bursts +system.physmem.perBankRdBursts::15 32215 # Per bank write bursts +system.physmem.perBankWrBursts::0 29077 # Per bank write bursts +system.physmem.perBankWrBursts::1 32864 # Per bank write bursts +system.physmem.perBankWrBursts::2 29906 # Per bank write bursts +system.physmem.perBankWrBursts::3 31279 # Per bank write bursts +system.physmem.perBankWrBursts::4 30178 # Per bank write bursts +system.physmem.perBankWrBursts::5 33497 # Per bank write bursts +system.physmem.perBankWrBursts::6 28885 # Per bank write bursts +system.physmem.perBankWrBursts::7 30667 # Per bank write bursts +system.physmem.perBankWrBursts::8 29490 # Per bank write bursts +system.physmem.perBankWrBursts::9 32863 # Per bank write bursts +system.physmem.perBankWrBursts::10 29440 # Per bank write bursts +system.physmem.perBankWrBursts::11 30986 # Per bank write bursts +system.physmem.perBankWrBursts::12 28208 # Per bank write bursts +system.physmem.perBankWrBursts::13 28238 # Per bank write bursts +system.physmem.perBankWrBursts::14 27304 # Per bank write bursts +system.physmem.perBankWrBursts::15 28330 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 51233860786000 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 51275914443000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 540590 # Read request sizes (log2) +system.physmem.readPktSize::6 550245 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 467319 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 115802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 481237 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 388368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 101483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -180,186 +198,191 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 20463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 25091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 27451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 27607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 28499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 29120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 30157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 29862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 30268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 29365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 28599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 28666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 27259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 8646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 19148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 23177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 26333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 27904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 27768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 28936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 29500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 30869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 30606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 30707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 29539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 30452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 28468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 28582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 27212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 258364 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.586227 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.482668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 288.931122 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 115624 44.75% 44.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 63401 24.54% 69.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24271 9.39% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12099 4.68% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9378 3.63% 87.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5671 2.19% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4999 1.93% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3884 1.50% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19037 7.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 258364 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 26815 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.147343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 9.386417 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-15 3084 11.50% 11.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16-31 21562 80.41% 91.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-47 1686 6.29% 98.20% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::48-63 338 1.26% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-79 91 0.34% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::80-95 28 0.10% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-111 17 0.06% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::112-127 4 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-143 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 273820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.988445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 145.225402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 282.507263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 125281 45.75% 45.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 68336 24.96% 70.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24972 9.12% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12598 4.60% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9315 3.40% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5687 2.08% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4750 1.73% 91.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3875 1.42% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19006 6.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 273820 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 27019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.349051 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.037322 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-15 3255 12.05% 12.05% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-31 21302 78.84% 90.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-47 1883 6.97% 97.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-63 429 1.59% 99.44% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-79 82 0.30% 99.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-95 50 0.19% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-111 5 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::112-127 5 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-143 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::144-159 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::208-223 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::240-255 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::288-303 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 26815 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 26815 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.427522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.974087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.290252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 17 0.06% 0.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 10 0.04% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 10 0.04% 0.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 46 0.17% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 25300 94.35% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 507 1.89% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 249 0.93% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 127 0.47% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 87 0.32% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 125 0.47% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 58 0.22% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.05% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.07% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.07% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 12 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.03% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 123 0.46% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.07% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 17 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 26815 # Writes before turning the bus around for reads -system.physmem.totQLat 12836932182 # Total ticks spent queuing -system.physmem.totMemAccLat 22966638432 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2701255000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23761.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::336-351 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 27019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 27019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.810134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.198144 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.395128 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 20 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 13 0.05% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 7 0.03% 0.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 44 0.16% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 25225 93.36% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 422 1.56% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 332 1.23% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 185 0.68% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 112 0.41% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 204 0.76% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 76 0.28% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 16 0.06% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.07% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.07% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 23 0.09% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.05% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 191 0.71% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 20 0.07% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 23 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 16 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.05% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 27019 # Writes before turning the bus around for reads +system.physmem.totQLat 11443674557 # Total ticks spent queuing +system.physmem.totMemAccLat 21753380807 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2749255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20812.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42511.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.67 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39562.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.63 # Average write queue length when enqueuing -system.physmem.readRowHits 422337 # Number of row buffer hits during reads -system.physmem.writeRowHits 326863 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.94 # Row buffer hit rate for writes -system.physmem.avgGap 50831831.83 # Average gap between requests -system.physmem.pageHitRate 74.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1022081760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 555373500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2201604600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1562664960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3304577109600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1165623840135 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29580668399250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34056211073805 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.700210 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48799941577250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1689456600000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 6.72 # Average write queue length when enqueuing +system.physmem.readRowHits 421327 # Number of row buffer hits during reads +system.physmem.writeRowHits 335914 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.80 # Row buffer hit rate for writes +system.physmem.avgGap 49710915.40 # Average gap between requests +system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1064213640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 579096375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2201979000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1596367440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3310527770160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1178433187650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30013431943500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34507834557765 # Total energy per rank (pJ) +system.physmem_0.averagePower 666.879372 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48871742574250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1692498860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 106076762500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 121731845500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 931059360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 506149875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2012353200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1465445520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3304577109600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1160291732670 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29572164937500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34041948787725 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.708167 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48807751567992 # Time in different power states -system.physmem_1.memoryStateTime::REF 1689456600000 # Time in different power states +system.physmem_1.actEnergy 1005865560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 547383375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2086788600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1521886320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3310527770160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1173650278320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29856307058250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34345647030585 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.211846 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48878835578992 # Time in different power states +system.physmem_1.memoryStateTime::REF 1692498860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 98247859258 # Time in different power states +system.physmem_1.memoryStateTime::ACT 114595771758 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -419,48 +442,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 112814 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 112814 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 112814 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 112814 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 112814 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 1116892952476 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.571172 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.494909 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 478954833976 42.88% 42.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 637938118500 57.12% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1116892952476 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 81756 84.41% 84.41% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 15104 15.59% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 96860 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 112814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 90556 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 90556 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 90556 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 90556 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 90556 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 391820965788 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.505629 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -198115997962 -50.56% -50.56% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 589936963750 150.56% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 391820965788 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66622 84.81% 84.81% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11928 15.19% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 78550 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90556 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 112814 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96860 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90556 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78550 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96860 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 209674 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78550 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 169106 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 78427319 # DTB read hits -system.cpu0.dtb.read_misses 84483 # DTB read misses -system.cpu0.dtb.write_hits 71558713 # DTB write hits -system.cpu0.dtb.write_misses 28331 # DTB write misses -system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 64673225 # DTB read hits +system.cpu0.dtb.read_misses 68448 # DTB read misses +system.cpu0.dtb.write_hits 58639149 # DTB write hits +system.cpu0.dtb.write_misses 22108 # DTB write misses +system.cpu0.dtb.flush_tlb 1188 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21339 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 502 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 51365 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 15858 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 413 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41832 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3702 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2761 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9826 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78511802 # DTB read accesses -system.cpu0.dtb.write_accesses 71587044 # DTB write accesses +system.cpu0.dtb.perms_faults 7632 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64741673 # DTB read accesses +system.cpu0.dtb.write_accesses 58661257 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 149986032 # DTB hits -system.cpu0.dtb.misses 112814 # DTB misses -system.cpu0.dtb.accesses 150098846 # DTB accesses +system.cpu0.dtb.hits 123312374 # DTB hits +system.cpu0.dtb.misses 90556 # DTB misses +system.cpu0.dtb.accesses 123402930 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -490,585 +512,696 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 63116 # Table walker walks requested -system.cpu0.itb.walker.walksLong 63116 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 63116 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 63116 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 63116 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 1116892951476 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.571207 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.494904 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 478916115976 42.88% 42.88% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 637976835500 57.12% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1116892951476 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54727 95.15% 95.15% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2791 4.85% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 57518 # Table walker page sizes translated +system.cpu0.itb.walker.walks 54313 # Table walker walks requested +system.cpu0.itb.walker.walksLong 54313 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 54313 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 54313 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 54313 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 391820965788 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.505731 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -198155892462 -50.57% -50.57% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 589976858250 150.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 391820965788 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 47491 95.01% 95.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2494 4.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 49985 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63116 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63116 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 54313 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 54313 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57518 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57518 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 120634 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 420544157 # ITB inst hits -system.cpu0.itb.inst_misses 63116 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49985 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49985 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 104298 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 343634485 # ITB inst hits +system.cpu0.itb.inst_misses 54313 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1188 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21339 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 502 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 35909 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 15858 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 413 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29675 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 420607273 # ITB inst accesses -system.cpu0.itb.hits 420544157 # DTB hits -system.cpu0.itb.misses 63116 # DTB misses -system.cpu0.itb.accesses 420607273 # DTB accesses -system.cpu0.numCycles 505895917 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 343688798 # ITB inst accesses +system.cpu0.itb.hits 343634485 # DTB hits +system.cpu0.itb.misses 54313 # DTB misses +system.cpu0.itb.accesses 343688798 # DTB accesses +system.cpu0.numCycles 414612673 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 420346594 # Number of instructions committed -system.cpu0.committedOps 494579830 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 453915139 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 407993 # Number of float alu accesses -system.cpu0.num_func_calls 25255441 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64064604 # number of instructions that are conditional controls -system.cpu0.num_int_insts 453915139 # number of integer instructions -system.cpu0.num_fp_insts 407993 # number of float instructions -system.cpu0.num_int_register_reads 669796814 # number of times the integer registers were read -system.cpu0.num_int_register_writes 361015506 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 660600 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 338556 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 110996958 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 110750515 # number of times the CC registers were written -system.cpu0.num_mem_refs 150079107 # number of memory refs -system.cpu0.num_load_insts 78499668 # Number of load instructions -system.cpu0.num_store_insts 71579439 # Number of store instructions -system.cpu0.num_idle_cycles 493874204.516617 # Number of idle cycles -system.cpu0.num_busy_cycles 12021712.483383 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023763 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976237 # Percentage of idle cycles -system.cpu0.Branches 93830955 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 343614791 69.43% 69.43% # Class of executed instruction -system.cpu0.op_class::IntMult 1086596 0.22% 69.65% # Class of executed instruction -system.cpu0.op_class::IntDiv 48369 0.01% 69.66% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 49130 0.01% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction -system.cpu0.op_class::MemRead 78499668 15.86% 85.54% # Class of executed instruction -system.cpu0.op_class::MemWrite 71579439 14.46% 100.00% # Class of executed instruction +system.cpu0.committedInsts 343491459 # Number of instructions committed +system.cpu0.committedOps 404038438 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 371064332 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 366662 # Number of float alu accesses +system.cpu0.num_func_calls 20606328 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 52246055 # number of instructions that are conditional controls +system.cpu0.num_int_insts 371064332 # number of integer instructions +system.cpu0.num_fp_insts 366662 # number of float instructions +system.cpu0.num_int_register_reads 542308147 # number of times the integer registers were read +system.cpu0.num_int_register_writes 294610052 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 579925 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 335816 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 90131130 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89914881 # number of times the CC registers were written +system.cpu0.num_mem_refs 123386712 # number of memory refs +system.cpu0.num_load_insts 64730993 # Number of load instructions +system.cpu0.num_store_insts 58655719 # Number of store instructions +system.cpu0.num_idle_cycles 404807579.503922 # Number of idle cycles +system.cpu0.num_busy_cycles 9805093.496078 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023649 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976351 # Percentage of idle cycles +system.cpu0.Branches 76646162 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 279922003 69.24% 69.24% # Class of executed instruction +system.cpu0.op_class::IntMult 872785 0.22% 69.46% # Class of executed instruction +system.cpu0.op_class::IntDiv 43154 0.01% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 49919 0.01% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::MemRead 64730993 16.01% 85.49% # Class of executed instruction +system.cpu0.op_class::MemWrite 58655719 14.51% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 494878036 # Class of executed instruction +system.cpu0.op_class::total 404274574 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16312 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 10193982 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 304221340 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10194494 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.841730 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 16555 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 9760623 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999693 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 295406617 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9761135 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.263552 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.636821 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.388351 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.974546 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968041 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010524 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.021435 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.408382 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.358891 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 7.391492 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 3.840928 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.967594 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010467 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.014437 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.007502 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1293146150 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1293146150 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73192810 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 24078178 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 59062839 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156333827 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67632120 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 22097804 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 49843167 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 139573091 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 193481 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58228 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 144072 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395781 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 150752 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 54007 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 125506 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 330265 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1823556 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 547758 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1229270 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3600584 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1933646 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 595016 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1413472 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3942134 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 140824930 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 46175982 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 108906006 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 295906918 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 141018411 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 46234210 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 109050078 # number of overall hits -system.cpu0.dcache.overall_hits::total 296302699 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2530012 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 810343 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 4548856 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7889211 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1084459 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 324852 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 4363130 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5772441 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 629295 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 177552 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 467332 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1274179 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 753152 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 142541 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 338665 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1234358 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 110926 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 47584 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 233520 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 392030 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3614471 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1135195 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 8911986 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13661652 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4243766 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1312747 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 9379318 # number of overall misses -system.cpu0.dcache.overall_misses::total 14935831 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12443944000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 69833838000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 82277782000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9722892000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 137997538214 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 147720430214 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 3829880000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 11756491801 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 15586371801 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 699957500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 2904634000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3604591500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 111000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 275000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 22166836000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 207831376214 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 229998212214 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 22166836000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 207831376214 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 229998212214 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75722822 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 24888521 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 63611695 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 164223038 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 68716579 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 22422656 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 54206297 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 145345532 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 822776 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 235780 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 611404 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1669960 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 903904 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 196548 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 464171 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1564623 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1934482 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 595342 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1462790 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3992614 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1933646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 595018 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 1413479 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3942143 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 144439401 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 47311177 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 117817992 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 309568570 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 145262177 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 47546957 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 118429396 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 311238530 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033411 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032559 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.071510 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.048040 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015782 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014488 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.080491 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.039715 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764844 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.753041 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.764359 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763000 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.833221 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.725222 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.729613 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788917 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057341 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.079927 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.159640 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098189 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025024 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023994 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.075642 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.044131 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029215 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027609 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079198 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.047988 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15356.391059 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15351.956184 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10429.152167 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29930.220531 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31628.106019 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25590.634918 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26868.620257 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34714.221431 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 12627.108020 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14709.934011 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12438.480644 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9194.682805 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15857.142857 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30555.555556 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19526.897141 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23320.433427 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16835.314808 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16885.840150 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22158.474232 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15399.090430 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 17007920 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25831 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1141319 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 442 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.901986 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 58.441176 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 1251530357 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1251530357 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 60440714 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 19079891 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 26457743 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 46030584 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 152008932 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 55470897 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 17632949 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 23585193 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 38751939 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 135440978 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 163149 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 46374 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 80888 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 112448 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 402859 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 132862 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44988 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu2.data 52244 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu3.data 99564 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 329658 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1435046 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 431760 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 583467 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 975735 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3426008 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1528481 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 469205 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 629772 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1126896 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3754354 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 115911611 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 36712840 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 50042936 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu3.data 84782523 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 287449910 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 116074760 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 36759214 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 50123824 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 84894971 # number of overall hits +system.cpu0.dcache.overall_hits::total 287852769 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2074038 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 622706 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 950512 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 3520436 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7167692 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 834575 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 257970 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 650618 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 3386065 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 5129228 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 508589 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 146296 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 212076 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu3.data 322320 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1189281 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 666999 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 114735 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu2.data 152937 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu3.data 292722 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1227393 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 94072 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 37658 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 46539 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 187643 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 365912 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu3.data 4 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2908613 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 880676 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1601130 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu3.data 6906501 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 12296920 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3417202 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1026972 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1813206 # number of overall misses +system.cpu0.dcache.overall_misses::cpu3.data 7228821 # number of overall misses +system.cpu0.dcache.overall_misses::total 13486201 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9559498000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 14919986000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 53204647500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 77684131500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6931134000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17483945500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 95592660029 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 120007739529 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2732317500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 4244347000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 10498361311 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 17475025811 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 520498500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 650995000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2326488500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3497982000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 142500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 142500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 16490632000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 32403931500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu3.data 148797307529 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 197691871029 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 16490632000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 32403931500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu3.data 148797307529 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 197691871029 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 62514752 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 19702597 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 27408255 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu3.data 49551020 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 159176624 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 56305472 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 17890919 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 24235811 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu3.data 42138004 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 140570206 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 671738 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 192670 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 292964 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 434768 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1592140 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 799861 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 159723 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 205181 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 392286 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1557051 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1529118 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 469418 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 630006 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1163378 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3791920 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1528481 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 469205 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 629772 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1126900 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3754358 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 118820224 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 37593516 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 51644066 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 91689024 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 299746830 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 119491962 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 37786186 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 51937030 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 92123792 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 301338970 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033177 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031605 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.034680 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071047 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.045030 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014822 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014419 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.026845 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.080357 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.036489 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.757124 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.759309 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.723898 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.741361 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.746970 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.833894 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.718337 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.745376 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.746195 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788281 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061520 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.080223 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.073871 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.161292 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.096498 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024479 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023426 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.031003 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.075325 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041024 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028598 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027179 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034912 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.078469 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.044754 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15351.543104 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15696.788678 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15113.084715 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10838.095652 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26867.984649 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26872.827834 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 28231.194625 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23396.842474 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23814.158714 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 27752.257465 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35864.613220 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14237.514644 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13821.724468 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13988.160468 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12398.482757 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9559.626358 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 35625 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 35625 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18724.970364 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20238.163984 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21544.528485 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16076.535509 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16057.528345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17871.070082 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20583.897088 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14658.825790 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 12159694 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 10325 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 863086 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 292 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.088624 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 35.359589 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7849789 # number of writebacks -system.cpu0.dcache.writebacks::total 7849789 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2357 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2525238 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2527595 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1733 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3623036 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3624769 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 2374 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2374 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 10549 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 144753 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 155302 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 4090 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 6148274 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 6152364 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 4090 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 6148274 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 6152364 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 807986 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 2023618 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2831604 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 323119 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 740094 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1063213 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 177438 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 455361 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 632799 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 142541 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 336291 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 478832 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 37035 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 88767 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125802 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 1131105 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 2763712 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 3894817 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1308543 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 3219073 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4527616 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 4998 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8152 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 13150 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4942 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 7788 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 12730 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 9940 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15940 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25880 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 11585855500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 31062083000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42647938500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9355442500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24215406665 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33570849165 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2741056000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 8202281000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10943337000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 3687339000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 11324765301 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 15012104301 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 496140000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1176567000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1672707000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 104000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 266000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 20941298000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 55277489665 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 76218787665 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 23682354000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 63479770665 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 87162124665 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 826187000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1474974000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2301161000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 827724000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1436870963 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2264594963 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1653911000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2911844963 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4565755963 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032464 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031812 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014410 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013653 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007315 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752557 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.744779 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.378931 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725222 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.724498 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.306037 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062208 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060683 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031509 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023908 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023457 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.012581 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027521 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027181 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14339.178525 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15349.775995 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15061.406362 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28953.551168 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32719.366276 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31574.904713 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15447.964923 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18012.699814 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17293.543447 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25868.620257 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33675.493251 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31351.505958 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13396.516808 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13254.554057 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13296.346640 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14857.142857 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 29555.555556 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18514.017708 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20001.175833 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19569.285968 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18098.261960 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19719.891616 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19251.218448 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165303.521409 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 180934.003925 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174993.231939 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167487.656819 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184498.069209 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177894.341163 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166389.436620 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 182675.342723 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176420.245866 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 7548701 # number of writebacks +system.cpu0.dcache.writebacks::total 7548701 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3073 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 106555 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1929145 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 2038773 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2189 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 286613 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2805614 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3094416 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 22 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2153 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 2175 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8609 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10642 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 114897 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 134148 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 5262 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 393168 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 4734759 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 5133189 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 5262 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 393168 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 4734759 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 5133189 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 619633 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 843957 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1591291 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3054881 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 255781 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 364005 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 580451 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1200237 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 146073 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 211968 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 317579 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 675620 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 114735 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 152915 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 290569 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 558219 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 29049 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 35897 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 72746 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137692 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 875414 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 1207962 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 2171742 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4255118 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 1021487 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 1419930 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 2489321 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4930738 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6070 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4638 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 5330 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16038 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5514 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4225 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 5069 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14808 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 11584 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8863 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 10399 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 8870276000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12358412500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 24290690000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45519378500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6598387000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9284220500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17173491540 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33056099040 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2440625000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3114719000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 4962911000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10518255000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2617582500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4091120500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10122943811 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 16831646811 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 372258500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 460319500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 958480000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1791058000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 138500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 138500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 15468663000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 21642633000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 41464181540 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 78575477540 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 17909288000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 24757352000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 46427092540 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 89093732540 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1079003500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 788343500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 908401000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2775748000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 999912000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 723848500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 894544000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2618304500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2078915500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1512192000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1802945000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5394052500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031449 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030792 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.032114 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019192 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014297 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015019 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.013775 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008538 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758151 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.723529 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.730456 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.424347 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.718337 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.745269 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.740707 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.358510 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061883 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.056979 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.062530 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036312 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023286 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023390 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023686 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.014196 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027033 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027339 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027021 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.016363 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14315.370550 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14643.414890 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15264.769297 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14900.540643 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25797.017761 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25505.749921 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29586.462148 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27541.309791 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16708.255461 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14694.288761 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15627.327374 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15568.300228 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22814.158714 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 26754.213125 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34838.347556 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30152.407587 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12814.847327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12823.341783 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13175.707255 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13007.712866 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 34625 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34625 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17670.111513 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17916.650524 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 19092.590897 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18466.110115 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17532.565760 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17435.614432 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18650.504511 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18069.046163 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177760.049423 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 169974.881414 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 170431.707317 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173073.201147 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181340.587595 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 171325.088757 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 176473.466167 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 176816.889519 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 179464.390539 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170618.526458 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 173376.766997 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174870.404591 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 14504187 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.976820 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 610702941 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14504699 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.103800 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9090101500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.013968 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.629060 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.333792 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.970730 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.009041 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020183 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 15782789 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.974752 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 561471069 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 15783301 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.573741 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10320549500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.461580 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.134097 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.765697 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 11.613377 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.920823 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006121 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.050324 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.022682 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 640161996 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 640161996 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 414014521 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 133530266 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 63158154 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 610702941 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 414014521 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 133530266 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 63158154 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 610702941 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 414014521 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 133530266 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 63158154 # number of overall hits -system.cpu0.icache.overall_hits::total 610702941 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6587154 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 2095893 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 6271180 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14954227 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6587154 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 2095893 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 6271180 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14954227 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6587154 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 2095893 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 6271180 # number of overall misses -system.cpu0.icache.overall_misses::total 14954227 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 28071619000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 82050168313 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 110121787313 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 28071619000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 82050168313 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 110121787313 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 28071619000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 82050168313 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 110121787313 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 420601675 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 135626159 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 69429334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 625657168 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 420601675 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 135626159 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 69429334 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 625657168 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 420601675 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 135626159 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 69429334 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 625657168 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015661 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015453 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.090325 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023902 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015661 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015453 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.090325 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023902 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015661 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015453 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.090325 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023902 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13393.631736 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13083.688925 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7363.923746 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13393.631736 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13083.688925 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7363.923746 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13393.631736 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13083.688925 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7363.923746 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 53098 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 593396461 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 593396461 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 338161196 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 107417239 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 66543293 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu3.inst 49349341 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 561471069 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 338161196 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 107417239 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 66543293 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu3.inst 49349341 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 561471069 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 338161196 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 107417239 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 66543293 # number of overall hits +system.cpu0.icache.overall_hits::cpu3.inst 49349341 # number of overall hits +system.cpu0.icache.overall_hits::total 561471069 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5523274 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1705507 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 3878392 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu3.inst 5034836 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 16142009 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5523274 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1705507 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 3878392 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu3.inst 5034836 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 16142009 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5523274 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1705507 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 3878392 # number of overall misses +system.cpu0.icache.overall_misses::cpu3.inst 5034836 # number of overall misses +system.cpu0.icache.overall_misses::total 16142009 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22950704500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 52180116500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 65837786856 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 140968607856 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 22950704500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 52180116500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu3.inst 65837786856 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 140968607856 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 22950704500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 52180116500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu3.inst 65837786856 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 140968607856 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 343684470 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 109122746 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 70421685 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu3.inst 54384177 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 577613078 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 343684470 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 109122746 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 70421685 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu3.inst 54384177 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 577613078 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 343684470 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 109122746 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 70421685 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu3.inst 54384177 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 577613078 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016071 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015629 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.055074 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.092579 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.027946 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016071 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015629 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.055074 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu3.inst 0.092579 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.027946 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016071 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015629 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.055074 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu3.inst 0.092579 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.027946 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13456.822224 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13454.059440 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13076.451121 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8733.027460 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13456.822224 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13454.059440 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13076.451121 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8733.027460 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13456.822224 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13454.059440 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13076.451121 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8733.027460 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 36241 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 4092 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 2942 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.976051 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.318491 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 449399 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 449399 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 449399 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 449399 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 449399 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 449399 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2095893 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5821781 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 7917674 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 2095893 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 5821781 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 7917674 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 2095893 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 5821781 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 7917674 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 25975726000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 72655138349 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 98630864349 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 25975726000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 72655138349 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 98630864349 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 25975726000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 72655138349 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 98630864349 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012655 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012655 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012655 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12457.050435 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12457.050435 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12457.050435 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 358626 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 358626 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 358626 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 358626 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 358626 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 358626 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1705507 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3878392 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4676210 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10260109 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1705507 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 3878392 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 4676210 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10260109 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1705507 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 3878392 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 4676210 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10260109 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21245197500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 48301724500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 58313017880 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 127859939880 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21245197500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48301724500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 58313017880 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 127859939880 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21245197500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48301724500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58313017880 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 127859939880 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015629 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055074 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.085985 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017763 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015629 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055074 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.085985 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017763 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015629 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055074 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.085985 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017763 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12456.822224 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12454.059440 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12470.145242 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12461.850052 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12456.822224 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12454.059440 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12470.145242 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12461.850052 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12456.822224 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12454.059440 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12470.145242 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12461.850052 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1099,69 +1232,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 40125 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 40125 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6166 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 29054 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 40123 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.299080 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 59.907962 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 40122 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 40123 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 35222 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25010.164102 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22134.109650 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13083.481555 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 22653 64.31% 64.31% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 12324 34.99% 99.30% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 130 0.37% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 82 0.23% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 6 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 7 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 31718 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 31718 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4562 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23271 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 31713 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 31713 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 31713 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 27838 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23890.419570 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 20799.818642 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 12686.242290 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 18271 65.63% 65.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9416 33.82% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 93 0.33% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 40 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 7 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 2 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 35222 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2750429288 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.373730 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1027918000 -37.37% -37.37% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -3778347288 137.37% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2750429288 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 29054 82.49% 82.49% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 6166 17.51% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 35220 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 40125 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 27838 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1656807784 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.386410 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.486926 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1016600500 61.36% 61.36% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 640207284 38.64% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1656807784 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 23271 83.61% 83.61% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4562 16.39% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 27833 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31718 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 40125 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 35220 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31718 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27833 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 35220 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 75345 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27833 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 59551 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25724641 # DTB read hits -system.cpu1.dtb.read_misses 30962 # DTB read misses -system.cpu1.dtb.write_hits 23221976 # DTB write hits -system.cpu1.dtb.write_misses 9163 # DTB write misses -system.cpu1.dtb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 20370755 # DTB read hits +system.cpu1.dtb.read_misses 24112 # DTB read misses +system.cpu1.dtb.write_hits 18527997 # DTB write hits +system.cpu1.dtb.write_misses 7606 # DTB write misses +system.cpu1.dtb.flush_tlb 1180 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 6096 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 163 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 21958 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5411 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 128 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 17894 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1268 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 972 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2784 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25755603 # DTB read accesses -system.cpu1.dtb.write_accesses 23231139 # DTB write accesses +system.cpu1.dtb.perms_faults 2622 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20394867 # DTB read accesses +system.cpu1.dtb.write_accesses 18535603 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 48946617 # DTB hits -system.cpu1.dtb.misses 40125 # DTB misses -system.cpu1.dtb.accesses 48986742 # DTB accesses +system.cpu1.dtb.hits 38898752 # DTB hits +system.cpu1.dtb.misses 31718 # DTB misses +system.cpu1.dtb.accesses 38930470 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1191,135 +1322,134 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 23205 # Table walker walks requested -system.cpu1.itb.walker.walksLong 23205 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1161 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20405 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 23205 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 23205 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 23205 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 21566 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27973.105815 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25131.407006 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 15236.984733 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 11031 51.15% 51.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 10248 47.52% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 108 0.50% 99.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 142 0.66% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 12 0.06% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 10 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 2 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 21566 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 20405 94.62% 94.62% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1161 5.38% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 21566 # Table walker page sizes translated +system.cpu1.itb.walker.walks 20303 # Table walker walks requested +system.cpu1.itb.walker.walksLong 20303 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 913 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18082 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 20303 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 20303 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 20303 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18995 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26989.076073 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24368.047797 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13392.289816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 10117 53.26% 53.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 8707 45.84% 99.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 60 0.32% 99.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 90 0.47% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 3 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18995 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000001500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000001500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000001500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 18082 95.19% 95.19% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 913 4.81% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18995 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23205 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23205 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20303 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20303 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 21566 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 21566 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 44771 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 135626159 # ITB inst hits -system.cpu1.itb.inst_misses 23205 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18995 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18995 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 39298 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 109122746 # ITB inst hits +system.cpu1.itb.inst_misses 20303 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1180 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 6096 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 163 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 16107 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5411 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 128 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13373 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 135649364 # ITB inst accesses -system.cpu1.itb.hits 135626159 # DTB hits -system.cpu1.itb.misses 23205 # DTB misses -system.cpu1.itb.accesses 135649364 # DTB accesses -system.cpu1.numCycles 1276121974 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 109143049 # ITB inst accesses +system.cpu1.itb.hits 109122746 # DTB hits +system.cpu1.itb.misses 20303 # DTB misses +system.cpu1.itb.accesses 109143049 # DTB accesses +system.cpu1.numCycles 1180099858 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 135538016 # Number of instructions committed -system.cpu1.committedOps 159130731 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 146160247 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 138681 # Number of float alu accesses -system.cpu1.num_func_calls 7978033 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 20702063 # number of instructions that are conditional controls -system.cpu1.num_int_insts 146160247 # number of integer instructions -system.cpu1.num_fp_insts 138681 # number of float instructions -system.cpu1.num_int_register_reads 211618661 # number of times the integer registers were read -system.cpu1.num_int_register_writes 115744147 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 219623 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 127108 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35291781 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 35222922 # number of times the CC registers were written -system.cpu1.num_mem_refs 48943439 # number of memory refs -system.cpu1.num_load_insts 25723579 # Number of load instructions -system.cpu1.num_store_insts 23219860 # Number of store instructions -system.cpu1.num_idle_cycles 1249309266.868014 # Number of idle cycles -system.cpu1.num_busy_cycles 26812707.131986 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021011 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978989 # Percentage of idle cycles -system.cpu1.Branches 30260595 # Number of branches fetched +system.cpu1.committedInsts 109047622 # Number of instructions committed +system.cpu1.committedOps 127894194 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 117464270 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 113646 # Number of float alu accesses +system.cpu1.num_func_calls 6418056 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16543747 # number of instructions that are conditional controls +system.cpu1.num_int_insts 117464270 # number of integer instructions +system.cpu1.num_fp_insts 113646 # number of float instructions +system.cpu1.num_int_register_reads 169880190 # number of times the integer registers were read +system.cpu1.num_int_register_writes 93121428 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 186254 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 89372 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 28297680 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 28206937 # number of times the CC registers were written +system.cpu1.num_mem_refs 38895648 # number of memory refs +system.cpu1.num_load_insts 20369525 # Number of load instructions +system.cpu1.num_store_insts 18526123 # Number of store instructions +system.cpu1.num_idle_cycles 1154177022.629432 # Number of idle cycles +system.cpu1.num_busy_cycles 25922835.370568 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021967 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978033 # Percentage of idle cycles +system.cpu1.Branches 24335155 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 109906813 69.03% 69.03% # Class of executed instruction -system.cpu1.op_class::IntMult 333855 0.21% 69.24% # Class of executed instruction -system.cpu1.op_class::IntDiv 14527 0.01% 69.25% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.25% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 20240 0.01% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.26% # Class of executed instruction -system.cpu1.op_class::MemRead 25723579 16.16% 85.42% # Class of executed instruction -system.cpu1.op_class::MemWrite 23219860 14.58% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 88791781 69.39% 69.39% # Class of executed instruction +system.cpu1.op_class::IntMult 259621 0.20% 69.59% # Class of executed instruction +system.cpu1.op_class::IntDiv 10323 0.01% 69.60% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 11904 0.01% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction +system.cpu1.op_class::MemRead 20369525 15.92% 85.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 18526123 14.48% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 159218874 # Class of executed instruction +system.cpu1.op_class::total 127969318 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 96379868 # Number of BP lookups -system.cpu2.branchPred.condPredicted 65507682 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 4329047 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 66096416 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 46823178 # Number of BTB hits +system.cpu2.branchPred.lookups 40525945 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28226804 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1998617 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 29685490 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 21101641 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 70.840722 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 12400698 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 133614 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.084025 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4984455 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 337609 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1349,86 +1479,63 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 662632 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 662632 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11252 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 67139 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 410741 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 251891 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 2203.738919 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 12798.903480 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-65535 250391 99.40% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-131071 1085 0.43% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::131072-196607 243 0.10% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::196608-262143 75 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 251891 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 304707 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 22494.824536 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 18425.462627 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 15718.326432 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 298255 97.88% 97.88% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-131071 5951 1.95% 99.84% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 243 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 191 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 38 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 304707 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 640151154620 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.510260 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.628480 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-3 639427998620 99.89% 99.89% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-7 404049000 0.06% 99.95% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-11 134377500 0.02% 99.97% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-15 87391000 0.01% 99.98% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-19 34713500 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-23 17695000 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-27 17014000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::28-31 22612000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::32-35 4758500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::36-39 448500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::40-43 50500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::44-47 27500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::48-51 19000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 640151154620 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 67139 85.65% 85.65% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 11252 14.35% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 78391 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 662632 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 94850 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 94850 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7112 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30265 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 94850 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 94850 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 94850 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 37377 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 24334.778072 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 21415.303868 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 12070.350338 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-32767 24490 65.52% 65.52% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12692 33.96% 99.48% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-98303 111 0.30% 99.78% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::98304-131071 62 0.17% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::163840-196607 6 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 37377 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000229500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000229500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000229500 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 30265 80.97% 80.97% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 7112 19.03% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 37377 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 94850 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 662632 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 78391 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 94850 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37377 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 78391 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 741023 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37377 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 132227 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 76683824 # DTB read hits -system.cpu2.dtb.read_misses 455088 # DTB read misses -system.cpu2.dtb.write_hits 59509350 # DTB write hits -system.cpu2.dtb.write_misses 207544 # DTB write misses -system.cpu2.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28616458 # DTB read hits +system.cpu2.dtb.read_misses 79197 # DTB read misses +system.cpu2.dtb.write_hits 25171351 # DTB write hits +system.cpu2.dtb.write_misses 15653 # DTB write misses +system.cpu2.dtb.flush_tlb 1181 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 14760 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 38772 # Number of entries that have been flushed from TLB +system.cpu2.dtb.flush_tlb_mva_asid 6998 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 187 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 22525 # Number of entries that have been flushed from TLB system.cpu2.dtb.align_faults 82 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 6499 # Number of TLB faults due to prefetch +system.cpu2.dtb.prefetch_faults 2323 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 41159 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 77138912 # DTB read accesses -system.cpu2.dtb.write_accesses 59716894 # DTB write accesses +system.cpu2.dtb.perms_faults 3900 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28695655 # DTB read accesses +system.cpu2.dtb.write_accesses 25187004 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 136193174 # DTB hits -system.cpu2.dtb.misses 662632 # DTB misses -system.cpu2.dtb.accesses 136855806 # DTB accesses +system.cpu2.dtb.hits 53787809 # DTB hits +system.cpu2.dtb.misses 94850 # DTB misses +system.cpu2.dtb.accesses 53882659 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1458,395 +1565,610 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 81585 # Table walker walks requested -system.cpu2.itb.walker.walksLong 81585 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2498 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 56536 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 10896 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 70689 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1473.991710 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 8586.891139 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-32767 70027 99.06% 99.06% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-65535 428 0.61% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-98303 144 0.20% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::98304-131071 50 0.07% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::131072-163839 13 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::294912-327679 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 70689 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 69930 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 28234.749035 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 24509.520790 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 16350.855698 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 36490 52.18% 52.18% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 32158 45.99% 98.17% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 628 0.90% 99.06% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 491 0.70% 99.77% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 45 0.06% 99.83% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 57 0.08% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 10 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 69930 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 485530683964 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.892648 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.309939 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 52174022580 10.75% 10.75% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 433310679884 89.24% 99.99% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 41019000 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 4632000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 311000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::5 12000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::6 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::7 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 485530683964 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 56536 95.77% 95.77% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 2498 4.23% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 59034 # Table walker page sizes translated +system.cpu2.itb.walker.walks 27487 # Table walker walks requested +system.cpu2.itb.walker.walksLong 27487 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1835 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22882 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 27487 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 27487 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 27487 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24717 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 27209.107092 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 24621.462305 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 12743.919659 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 12896 52.17% 52.17% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 11567 46.80% 98.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 97 0.39% 99.36% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 138 0.56% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 7 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 6 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24717 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000203500 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000203500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000203500 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 22882 92.58% 92.58% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1835 7.42% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24717 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 81585 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 81585 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27487 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27487 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 59034 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 59034 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 140619 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 69601857 # ITB inst hits -system.cpu2.itb.inst_misses 81585 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24717 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24717 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 52204 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70482542 # ITB inst hits +system.cpu2.itb.inst_misses 27487 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1181 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 14760 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 30530 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 6998 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 187 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 17121 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 148496 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 57866 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 69683442 # ITB inst accesses -system.cpu2.itb.hits 69601857 # DTB hits -system.cpu2.itb.misses 81585 # DTB misses -system.cpu2.itb.accesses 69683442 # DTB accesses -system.cpu2.numCycles 461100419 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70510029 # ITB inst accesses +system.cpu2.itb.hits 70482542 # DTB hits +system.cpu2.itb.misses 27487 # DTB misses +system.cpu2.itb.accesses 70510029 # DTB accesses +system.cpu2.numCycles 6664328122 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 177123206 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 428437277 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 96379868 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 59223876 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 257401667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 9762973 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 2005280 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 7949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 2437 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 3773015 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 114784 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 5106 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 69429398 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 2656278 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 32686 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 445314772 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.124877 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.366658 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 339836575 76.31% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 13185142 2.96% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 13574991 3.05% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 9797674 2.20% 84.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 20004635 4.49% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 6578482 1.48% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 7061868 1.59% 92.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 6288982 1.41% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 28986423 6.51% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 445314772 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.209021 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.929163 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 144945569 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 209061419 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 78115064 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 9308814 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 3881927 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 14332703 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 1014310 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 468249315 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 3113109 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 3881927 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 150342023 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 16281945 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 167363518 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 81901775 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 25541188 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 457027313 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 55411 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 1577150 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 1077305 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 12432724 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 2850 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 436738370 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 696876474 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 538877799 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 611175 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 365603185 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 71135185 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 10148334 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 8698822 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 51282276 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 73817911 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 62641049 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 9297155 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 10241835 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 434108561 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 10116895 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 433413553 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 631683 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 59503474 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 37916216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 236413 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 445314772 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.973275 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.689353 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 278168249 62.47% 62.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 68048730 15.28% 77.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 31692331 7.12% 84.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22597394 5.07% 89.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 16978227 3.81% 93.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 11874624 2.67% 96.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 7985798 1.79% 98.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 4768189 1.07% 99.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 3201230 0.72% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 445314772 # Number of insts issued each cycle -system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2163580 25.08% 25.08% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 17452 0.20% 25.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 1463 0.02% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 3490107 40.46% 65.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 2952914 34.23% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 293684501 67.76% 67.76% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 1025227 0.24% 68.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 47766 0.01% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 317 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 1 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.01% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 48576 0.01% 68.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 68.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.02% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 78271434 18.06% 86.08% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 60335731 13.92% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 433413553 # Type of FU issued -system.cpu2.iq.rate 0.939955 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 8625516 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.019901 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 1320585789 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 503812289 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 417285848 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 813288 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 405263 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 361974 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 441604210 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 434859 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 3381259 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 11998288 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 16552 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 496769 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 6557326 # Number of stores squashed -system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 2684885 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 5754188 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 3881927 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10679636 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 4407291 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 444323917 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 1337797 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 73817911 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 62641049 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 8508217 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 157244 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4192594 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 496769 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 2009659 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1725096 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3734755 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 428275662 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 76671253 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 4484086 # Number of squashed instructions skipped in execute -system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 98461 # number of nop insts executed -system.cpu2.iew.exec_refs 136179692 # number of memory reference insts executed -system.cpu2.iew.exec_branches 79539500 # Number of branches executed -system.cpu2.iew.exec_stores 59508439 # Number of stores executed -system.cpu2.iew.exec_rate 0.928812 # Inst execution rate -system.cpu2.iew.wb_sent 418566552 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 417647822 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 206637380 # num instructions producing a value -system.cpu2.iew.wb_consumers 358874398 # num instructions consuming a value -system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.905763 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575793 # average fanout of values written-back -system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 59540982 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9880482 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 3329329 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 435241532 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.883928 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.881300 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 296713491 68.17% 68.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 66287598 15.23% 83.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 24183303 5.56% 88.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 11166549 2.57% 91.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 8012002 1.84% 93.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 4870056 1.12% 94.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 4489994 1.03% 95.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 2918433 0.67% 96.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 16600106 3.81% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 435241532 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 327785464 # Number of instructions committed -system.cpu2.commit.committedOps 384721982 # Number of ops (including micro ops) committed -system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 117903346 # Number of memory references committed -system.cpu2.commit.loads 61819623 # Number of loads committed -system.cpu2.commit.membars 2573370 # Number of memory barriers committed -system.cpu2.commit.branches 73211237 # Number of branches committed -system.cpu2.commit.fp_insts 346819 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 353394375 # Number of committed integer instructions. -system.cpu2.commit.function_calls 9534563 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 265954850 69.13% 69.13% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 786882 0.20% 69.33% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 35653 0.01% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 41251 0.01% 69.35% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 61819623 16.07% 85.42% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 56083723 14.58% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 384721982 # Class of committed instruction -system.cpu2.commit.bw_lim_events 16600106 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 860271406 # The number of ROB reads -system.cpu2.rob.rob_writes 898612976 # The number of ROB writes -system.cpu2.timesIdled 2954119 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 15785647 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 99456385277 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 327785464 # Number of Instructions Simulated -system.cpu2.committedOps 384721982 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.406714 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.406714 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.710877 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.710877 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 503674657 # number of integer regfile reads -system.cpu2.int_regfile_writes 298593848 # number of integer regfile writes -system.cpu2.fp_regfile_reads 690106 # number of floating regfile reads -system.cpu2.fp_regfile_writes 421944 # number of floating regfile writes -system.cpu2.cc_regfile_reads 91580916 # number of cc regfile reads -system.cpu2.cc_regfile_writes 92419773 # number of cc regfile writes -system.cpu2.misc_regfile_reads 837090025 # number of misc regfile reads -system.cpu2.misc_regfile_writes 9982057 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40263 # Transaction distribution -system.iobus.trans_dist::ReadResp 40263 # Transaction distribution -system.iobus.trans_dist::WriteReq 136537 # Transaction distribution -system.iobus.trans_dist::WriteResp 136537 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes) +system.cpu2.committedInsts 147830191 # Number of instructions committed +system.cpu2.committedOps 173473680 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 14792725 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1537 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 95888456497 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 45.080968 # CPI: cycles per instruction +system.cpu2.ipc 0.022182 # IPC: instructions per cycle +system.cpu2.kern.inst.arm 0 # number of arm instructions executed +system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu2.tickCycles 277268742 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 6387059380 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 75157877 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50856390 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3416721 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 51465907 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 36468064 # Number of BTB hits +system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu3.branchPred.BTBHitPct 70.858683 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9896161 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 105828 # Number of incorrect RAS predictions. +system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu3.dtb.walker.walks 516175 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 516175 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8289 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49802 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 319657 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 196518 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2097.090343 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 12006.037085 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-65535 195408 99.44% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-131071 810 0.41% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-196607 191 0.10% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-262143 57 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-327679 27 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-393215 12 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-458751 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 196518 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 233052 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 21512.128195 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 17601.941392 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 14913.346295 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-65535 228911 98.22% 98.22% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3858 1.66% 99.88% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-196607 119 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-262143 117 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-327679 29 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 233052 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -26470108720 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.558973 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -27011428720 102.05% 102.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 297974000 -1.13% 100.92% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 102453500 -0.39% 100.53% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 64308500 -0.24% 100.29% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 26659500 -0.10% 100.19% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 13977000 -0.05% 100.14% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 12432000 -0.05% 100.09% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 20278500 -0.08% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 3004000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 171500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 49500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 10000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::48-51 2000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -26470108720 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 49802 85.73% 85.73% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8289 14.27% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 58091 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 516175 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 516175 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58091 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58091 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 574266 # Table walker requests started/completed, data/inst +system.cpu3.dtb.inst_hits 0 # ITB inst hits +system.cpu3.dtb.inst_misses 0 # ITB inst misses +system.cpu3.dtb.read_hits 59190068 # DTB read hits +system.cpu3.dtb.read_misses 354265 # DTB read misses +system.cpu3.dtb.write_hits 46339519 # DTB write hits +system.cpu3.dtb.write_misses 161910 # DTB write misses +system.cpu3.dtb.flush_tlb 1179 # Number of times complete TLB was flushed +system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva_asid 11674 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 299 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 28883 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 57 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 5029 # Number of TLB faults due to prefetch +system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu3.dtb.perms_faults 29040 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 59544333 # DTB read accesses +system.cpu3.dtb.write_accesses 46501429 # DTB write accesses +system.cpu3.dtb.inst_accesses 0 # ITB inst accesses +system.cpu3.dtb.hits 105529587 # DTB hits +system.cpu3.dtb.misses 516175 # DTB misses +system.cpu3.dtb.accesses 106045762 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu3.itb.walker.walks 59515 # Table walker walks requested +system.cpu3.itb.walker.walksLong 59515 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1820 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40428 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8158 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 51357 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1446.696653 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 8669.763957 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 50895 99.10% 99.10% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 295 0.57% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 94 0.18% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 42 0.08% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 10 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 51357 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 50406 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 27093.679324 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 23240.458219 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 16758.841159 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-32767 28504 56.55% 56.55% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-65535 21034 41.73% 98.28% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-98303 420 0.83% 99.11% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::98304-131071 332 0.66% 99.77% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-163839 37 0.07% 99.84% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::163840-196607 32 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-229375 12 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 50406 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -26472605720 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 1.148605 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 3969304628 -14.99% -14.99% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -30473405348 115.11% 100.12% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 28081500 -0.11% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 3146000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 137000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 114000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::6 8000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::7 8500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -26472605720 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 40428 95.69% 95.69% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 1820 4.31% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 42248 # Table walker page sizes translated +system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59515 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59515 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42248 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42248 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 101763 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 54520119 # ITB inst hits +system.cpu3.itb.inst_misses 59515 # ITB inst misses +system.cpu3.itb.read_hits 0 # DTB read hits +system.cpu3.itb.read_misses 0 # DTB read misses +system.cpu3.itb.write_hits 0 # DTB write hits +system.cpu3.itb.write_misses 0 # DTB write misses +system.cpu3.itb.flush_tlb 1179 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva_asid 11674 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 299 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 21966 # Number of entries that have been flushed from TLB +system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu3.itb.perms_faults 118601 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.read_accesses 0 # DTB read accesses +system.cpu3.itb.write_accesses 0 # DTB write accesses +system.cpu3.itb.inst_accesses 54579634 # ITB inst accesses +system.cpu3.itb.hits 54520119 # DTB hits +system.cpu3.itb.misses 59515 # DTB misses +system.cpu3.itb.accesses 54579634 # DTB accesses +system.cpu3.numCycles 361365292 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.fetch.icacheStallCycles 141188803 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 334212277 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 75157877 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46364225 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 199187397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7734395 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1397358 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 6420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 2372 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 3033071 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 90584 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 3440 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 54384224 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2106741 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 23723 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 348776447 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.121764 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.363245 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 266236191 76.33% 76.33% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10517145 3.02% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10460372 3.00% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7763584 2.23% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15658447 4.49% 89.06% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5090746 1.46% 90.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5553519 1.59% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4863826 1.39% 93.51% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 22632617 6.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 348776447 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.207983 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.924860 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 115165884 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 162148875 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 61184358 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7206821 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 3068716 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 11212761 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 810030 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 365054891 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2491895 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 3068716 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 119377384 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 12649358 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 130577518 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 64081160 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 19020412 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 356185546 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 41963 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1038308 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 801382 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 8908900 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2068 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 339701413 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 543048215 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 420838737 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 489590 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 283499579 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 56201829 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 7935014 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 6800551 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 39752644 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 57621684 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 48771091 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7646320 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 8098105 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 338209447 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7991300 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 336799958 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 493625 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 46981873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 30279381 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 194982 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 348776447 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.965661 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.679402 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 218198931 62.56% 62.56% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 53432546 15.32% 77.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24862182 7.13% 85.01% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17747115 5.09% 90.10% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 13068769 3.75% 93.85% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9162782 2.63% 96.47% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6242831 1.79% 98.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3634597 1.04% 99.30% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2426694 0.70% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 348776447 # Number of insts issued each cycle +system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1722255 26.20% 26.20% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 16072 0.24% 26.44% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1128 0.02% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 1 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2609788 39.70% 66.16% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2224178 33.84% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 228441301 67.83% 67.83% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 866625 0.26% 68.08% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 39602 0.01% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 39134 0.01% 68.11% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 60438362 17.94% 86.05% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 46974933 13.95% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::total 336799958 # Type of FU issued +system.cpu3.iq.rate 0.932021 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6573422 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019517 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1028800637 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 393256983 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 324790914 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 642773 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 320221 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 286838 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 343029301 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 344078 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2684495 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.squashedLoads 9539540 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 13050 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 400702 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 5115949 # Number of stores squashed +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.rescheduledLoads 2114056 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 3866933 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu3.iew.iewSquashCycles 3068716 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8569768 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 3216654 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 346278716 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1046515 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 57621684 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 48771091 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6645619 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 129030 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 3038668 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 400702 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1583590 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1353598 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2937188 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 332817802 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 59181929 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3473252 # Number of squashed instructions skipped in execute +system.cpu3.iew.exec_swp 0 # number of swp insts executed +system.cpu3.iew.exec_nop 77969 # number of nop insts executed +system.cpu3.iew.exec_refs 105520536 # number of memory reference insts executed +system.cpu3.iew.exec_branches 61786884 # Number of branches executed +system.cpu3.iew.exec_stores 46338607 # Number of stores executed +system.cpu3.iew.exec_rate 0.921001 # Inst execution rate +system.cpu3.iew.wb_sent 325791778 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 325077752 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 160558315 # num instructions producing a value +system.cpu3.iew.wb_consumers 278246243 # num instructions consuming a value +system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu3.iew.wb_rate 0.899582 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.577037 # average fanout of values written-back +system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu3.commit.commitSquashedInsts 47005398 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7796318 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2618044 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 340807461 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.877970 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.872285 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 232401746 68.19% 68.19% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 52180181 15.31% 83.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 19062195 5.59% 89.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8578726 2.52% 91.61% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6304961 1.85% 93.46% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3698650 1.09% 94.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3483571 1.02% 95.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2215848 0.65% 96.22% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 12881583 3.78% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::total 340807461 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 254571933 # Number of instructions committed +system.cpu3.commit.committedOps 299218869 # Number of ops (including micro ops) committed +system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu3.commit.refs 91737285 # Number of memory references committed +system.cpu3.commit.loads 48082143 # Number of loads committed +system.cpu3.commit.membars 2101761 # Number of memory barriers committed +system.cpu3.commit.branches 56830426 # Number of branches committed +system.cpu3.commit.fp_insts 274837 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 275203911 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7606631 # Number of function calls committed. +system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 206755279 69.10% 69.10% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 663617 0.22% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 29152 0.01% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 33536 0.01% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 48082143 16.07% 85.41% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 43655142 14.59% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::total 299218869 # Class of committed instruction +system.cpu3.commit.bw_lim_events 12881583 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 672002413 # The number of ROB reads +system.cpu3.rob.rob_writes 700430084 # The number of ROB writes +system.cpu3.timesIdled 2364277 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 12588845 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98652153144 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 254571933 # Number of Instructions Simulated +system.cpu3.committedOps 299218869 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.419502 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.419502 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.704473 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.704473 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 392353216 # number of integer regfile reads +system.cpu3.int_regfile_writes 232744708 # number of integer regfile writes +system.cpu3.fp_regfile_reads 564242 # number of floating regfile reads +system.cpu3.fp_regfile_writes 330472 # number of floating regfile writes +system.cpu3.cc_regfile_reads 70058550 # number of cc regfile reads +system.cpu3.cc_regfile_writes 70773135 # number of cc regfile writes +system.cpu3.misc_regfile_reads 654632577 # number of misc regfile reads +system.cpu3.misc_regfile_writes 7821457 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40271 # Transaction distribution +system.iobus.trans_dist::ReadResp 40271 # Transaction distribution +system.iobus.trans_dist::WriteReq 136539 # Transaction distribution +system.iobus.trans_dist::WriteResp 136539 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1861,13 +2183,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230964 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230964 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353600 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353620 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1882,87 +2204,96 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334288 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13118000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 14862000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 7299000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 10428000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 16991000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 18725000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 175678218 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 246351678 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 37744000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 45146000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 35540000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 48770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 80000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.416552 # Cycle average of tags in use +system.iocache.tags.replacements 115464 # number of replacements +system.iocache.tags.tagsinuse 10.421022 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115480 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13085993128009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.913060 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.503492 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.369566 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.281468 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651035 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13087689851509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547375 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.873647 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221711 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429603 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651314 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039641 # Number of tag accesses -system.iocache.tags.data_accesses 1039641 # Number of data accesses +system.iocache.tags.tag_accesses 1039695 # Number of tag accesses +system.iocache.tags.data_accesses 1039695 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8818 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8855 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses -system.iocache.demand_misses::total 8852 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8818 # number of demand (read+write) misses +system.iocache.demand_misses::total 8858 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8812 # number of overall misses -system.iocache.overall_misses::total 8852 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 2432000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 80359879 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 82791879 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 3987954339 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3987954339 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 2432000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 80359879 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 82791879 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 2432000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 80359879 # number of overall miss cycles -system.iocache.overall_miss_latency::total 82791879 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8818 # number of overall misses +system.iocache.overall_misses::total 8858 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 66023672 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 66023672 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 5601261006 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5601261006 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 66023672 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 66023672 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 66023672 # number of overall miss cycles +system.iocache.overall_miss_latency::total 66023672 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8818 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8855 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8818 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8858 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8818 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8858 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1976,425 +2307,506 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 65729.729730 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 9119.368929 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 9356.071760 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 37388.006628 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 37388.006628 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 60800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 9119.368929 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 9352.900926 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 60800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 9119.368929 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 9352.900926 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1026 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 7487.374915 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 7456.089441 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52513.134760 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 52513.134760 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 7487.374915 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 7453.564236 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 7487.374915 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 7453.564236 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 106 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 47 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.679245 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.191489 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 518 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 534 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 33736 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 33736 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 518 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 534 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 518 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 534 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1632000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 54459879 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 56091879 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2301154339 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2301154339 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 1632000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 54459879 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 56091879 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 1632000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 54459879 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 56091879 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.060346 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.316283 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.316283 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.060325 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.060325 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105134.901544 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105040.971910 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68210.645571 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68210.645571 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 102000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 105134.901544 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 105040.971910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 102000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 105134.901544 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 105040.971910 # average overall mshr miss latency +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 493 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 493 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 47400 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 47400 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 493 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 493 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 493 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 41373672 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 41373672 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3231261006 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3231261006 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 41373672 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 41373672 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 41373672 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 41373672 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.055908 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.055675 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.444386 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.444386 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.055908 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.055656 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.055908 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.055656 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83922.255578 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 83922.255578 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68170.063418 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68170.063418 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 83922.255578 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 83922.255578 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 83922.255578 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 83922.255578 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1303829 # number of replacements -system.l2c.tags.tagsinuse 65263.667418 # Cycle average of tags in use -system.l2c.tags.total_refs 45613639 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1366689 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 33.375288 # Average number of references to valid blocks. +system.l2c.tags.replacements 1178201 # number of replacements +system.l2c.tags.tagsinuse 65342.536635 # Cycle average of tags in use +system.l2c.tags.total_refs 47533778 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1240935 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 38.304809 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37041.292991 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 185.441819 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 257.864893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3799.344283 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8420.169172 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 49.795293 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 72.886191 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 899.312109 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2654.836821 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 113.517705 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 173.967622 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2205.940609 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 9389.297910 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.565205 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002830 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003935 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.057973 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.128482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000760 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.013722 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.040510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001732 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.002655 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.033660 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.143269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995845 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 366 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62494 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 36457.259516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 134.391742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 206.626869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3141.459987 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 10234.454405 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 42.556098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 61.614862 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 851.307108 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2279.755035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 36.540857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 56.575168 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1930.782572 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2582.079000 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 98.957647 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 152.820118 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2413.377960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 4661.977691 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.556294 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002051 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003153 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.047935 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.156165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000649 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000940 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.012990 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.034786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000558 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000863 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.029461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.039399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.itb.walker 0.002332 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.036825 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.071136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997048 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 348 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62386 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 365 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 561 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2733 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4954 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54104 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005585 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.953583 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 407870689 # Number of tag accesses -system.l2c.tags.data_accesses 407870689 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 197247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 127080 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 74241 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 49038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 389886 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 153027 # number of ReadReq hits -system.l2c.ReadReq_hits::total 990519 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7849789 # number of Writeback hits -system.l2c.Writeback_hits::total 7849789 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 4877 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1479 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 3456 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9812 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 800462 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 239420 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 561376 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1601258 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 6543980 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 2084305 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 5786165 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 14414450 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3131607 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 987096 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 2453224 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6571927 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 344275 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 113975 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu2.data 264333 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 722583 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 197247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 127080 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6543980 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3932069 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 74241 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 49038 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 2084305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 1226516 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 389886 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 153027 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 5786165 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 3014600 # number of demand (read+write) hits -system.l2c.demand_hits::total 23578154 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 197247 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 127080 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6543980 # number of overall hits -system.l2c.overall_hits::cpu0.data 3932069 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 74241 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 49038 # number of overall hits -system.l2c.overall_hits::cpu1.inst 2084305 # number of overall hits -system.l2c.overall_hits::cpu1.data 1226516 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 389886 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 153027 # number of overall hits -system.l2c.overall_hits::cpu2.inst 5786165 # number of overall hits -system.l2c.overall_hits::cpu2.data 3014600 # number of overall hits -system.l2c.overall_hits::total 23578154 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1978 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1959 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 606 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 558 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 1500 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1371 # number of ReadReq misses -system.l2c.ReadReq_misses::total 7972 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17687 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5395 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 12690 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35772 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 261433 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76825 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 166750 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 505008 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 43174 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 11588 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 35478 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 90240 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 138626 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 35363 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 110344 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 284333 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 408877 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 28566 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu2.data 71958 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 509401 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1978 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1959 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 43174 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 400059 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 606 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 558 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 11588 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 112188 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 1500 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1371 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 35478 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 277094 # number of demand (read+write) misses -system.l2c.demand_misses::total 887553 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1978 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1959 # number of overall misses -system.l2c.overall_misses::cpu0.inst 43174 # number of overall misses -system.l2c.overall_misses::cpu0.data 400059 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 606 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 558 # number of overall misses -system.l2c.overall_misses::cpu1.inst 11588 # number of overall misses -system.l2c.overall_misses::cpu1.data 112188 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 1500 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1371 # number of overall misses -system.l2c.overall_misses::cpu2.inst 35478 # number of overall misses -system.l2c.overall_misses::cpu2.data 277094 # number of overall misses -system.l2c.overall_misses::total 887553 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 52967500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 49106500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 131463500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 122401500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 355939000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 83182000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 202962500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 286144500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 6175953000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 16594839500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 22770792500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 940204000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3036482500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 3976686500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 2924693000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 10192533500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 13117226500 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 2276790000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu2.data 7675556000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 9952346000 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 52967500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 49106500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 940204000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 9100646000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 131463500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 122401500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 3036482500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 26787373000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 40220644500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 52967500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 49106500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 940204000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 9100646000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 131463500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 122401500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 3036482500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 26787373000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 40220644500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 199225 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 129039 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 74847 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 49596 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 391386 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 154398 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 998491 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 7849789 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 7849789 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 22564 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 6874 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16146 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45584 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1061895 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 316245 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 728126 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2106266 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 6587154 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 2095893 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 5821643 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 14504690 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 3270233 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 1022459 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 2563568 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 6856260 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 753152 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 142541 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu2.data 336291 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 1231984 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 199225 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 129039 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 6587154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4332128 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 74847 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 49596 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 2095893 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1338704 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 391386 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 154398 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 5821643 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 3291694 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 24465707 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 199225 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 129039 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 6587154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4332128 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 74847 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 49596 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 2095893 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1338704 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 391386 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 154398 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 5821643 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 3291694 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 24465707 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.009928 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.015181 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.008097 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011251 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.008880 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.007984 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.783859 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.784841 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.785953 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.784749 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.142857 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.246195 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.242929 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.229013 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.239765 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006554 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005529 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.006094 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.006221 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.042390 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.034586 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.043043 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.041471 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.542888 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.200405 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu2.data 0.213975 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.413480 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.009928 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.015181 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006554 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.092347 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.008097 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.011251 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005529 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.083803 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003833 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.008880 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.006094 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.084180 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.036277 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.009928 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.015181 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006554 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.092347 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.008097 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.011251 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005529 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.083803 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003833 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.008880 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.006094 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.084180 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.036277 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87405.115512 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88004.480287 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87642.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 89278.993435 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 44648.645258 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15418.350324 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15993.892829 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 7999.119423 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 53000 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80389.886105 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 99519.277361 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 45089.963921 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81136.002761 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85587.758611 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 44067.891179 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82704.889291 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 92370.527623 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 46133.324306 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79702.793531 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 106667.166959 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 19537.350732 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87405.115512 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88004.480287 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81136.002761 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 81119.602810 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87642.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 89278.993435 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 85587.758611 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 96672.511855 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 45316.329842 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87405.115512 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88004.480287 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81136.002761 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 81119.602810 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87642.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 89278.993435 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 85587.758611 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 96672.511855 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 45316.329842 # average overall miss latency +system.l2c.tags.age_task_id_blocks_1023::4 346 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 559 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2832 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5180 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53698 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005310 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.951935 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 421030068 # Number of tag accesses +system.l2c.tags.data_accesses 421030068 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 160105 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 111071 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 55142 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 41666 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 153356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 57206 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 292962 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 104864 # number of ReadReq hits +system.l2c.ReadReq_hits::total 976372 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7548701 # number of Writeback hits +system.l2c.Writeback_hits::total 7548701 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3766 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1252 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 1641 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 2803 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9462 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu3.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 634186 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 200968 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 288741 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3.data 458130 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1582025 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 5488344 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 1694582 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 3854361 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 4648089 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 15685376 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 2558848 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 765070 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 1053468 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 1902951 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6280337 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 284863 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 96754 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu2.data 124346 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu3.data 225674 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 731637 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 160105 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 111071 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 5488344 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 3193034 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 55142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 41666 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 1694582 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 966038 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 153356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 57206 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 3854361 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 1342209 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.dtb.walker 292962 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.itb.walker 104864 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 4648089 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 2361081 # number of demand (read+write) hits +system.l2c.demand_hits::total 24524110 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 160105 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 111071 # number of overall hits +system.l2c.overall_hits::cpu0.inst 5488344 # number of overall hits +system.l2c.overall_hits::cpu0.data 3193034 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 55142 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 41666 # number of overall hits +system.l2c.overall_hits::cpu1.inst 1694582 # number of overall hits +system.l2c.overall_hits::cpu1.data 966038 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 153356 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 57206 # number of overall hits +system.l2c.overall_hits::cpu2.inst 3854361 # number of overall hits +system.l2c.overall_hits::cpu2.data 1342209 # number of overall hits +system.l2c.overall_hits::cpu3.dtb.walker 292962 # number of overall hits +system.l2c.overall_hits::cpu3.itb.walker 104864 # number of overall hits +system.l2c.overall_hits::cpu3.inst 4648089 # number of overall hits +system.l2c.overall_hits::cpu3.data 2361081 # number of overall hits +system.l2c.overall_hits::total 24524110 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1302 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1407 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 317 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 303 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 507 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 452 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.dtb.walker 1016 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.itb.walker 958 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6262 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 13735 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4483 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 5785 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 10296 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 34299 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu3.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 182889 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 49078 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 67882 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 112079 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 411928 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 34930 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 10925 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 24031 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 28031 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 97917 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 117851 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 29685 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 38310 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 75808 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 261654 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 382135 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 17981 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu2.data 28569 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu3.data 64895 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 493580 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1302 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1407 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 34930 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 300740 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 317 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 303 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 10925 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 78763 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 507 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 452 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 24031 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 106192 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.dtb.walker 1016 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.itb.walker 958 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 28031 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 187887 # number of demand (read+write) misses +system.l2c.demand_misses::total 777761 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1302 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1407 # number of overall misses +system.l2c.overall_misses::cpu0.inst 34930 # number of overall misses +system.l2c.overall_misses::cpu0.data 300740 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 317 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 303 # number of overall misses +system.l2c.overall_misses::cpu1.inst 10925 # number of overall misses +system.l2c.overall_misses::cpu1.data 78763 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 507 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 452 # number of overall misses +system.l2c.overall_misses::cpu2.inst 24031 # number of overall misses +system.l2c.overall_misses::cpu2.data 106192 # number of overall misses +system.l2c.overall_misses::cpu3.dtb.walker 1016 # number of overall misses +system.l2c.overall_misses::cpu3.itb.walker 958 # number of overall misses +system.l2c.overall_misses::cpu3.inst 28031 # number of overall misses +system.l2c.overall_misses::cpu3.data 187887 # number of overall misses +system.l2c.overall_misses::total 777761 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 27522500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 26481000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 43212000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 38388000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 88884500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.itb.walker 86213000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 310701000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 68441500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 90805000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3.data 164582000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 323828500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu3.data 81000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 81000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3953928500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 5507688000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 10998115500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 20459732000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 888341500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 1996189000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2389519000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 5274049500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 2457700500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 3192549500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 6788552500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 12438802500 # number of ReadSharedReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu1.data 1429563000 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu2.data 2523386500 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu3.data 6994477500 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::total 10947427000 # number of InvalidateReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 27522500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 26481000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 888341500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6411629000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 43212000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 38388000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 1996189000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 8700237500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.dtb.walker 88884500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.itb.walker 86213000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 2389519000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 17786668000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 38483285000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 27522500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 26481000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 888341500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6411629000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 43212000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 38388000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 1996189000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 8700237500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.dtb.walker 88884500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.itb.walker 86213000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 2389519000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 17786668000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 38483285000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 161407 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 112478 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 55459 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 41969 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 153863 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 57658 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.dtb.walker 293978 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.itb.walker 105822 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 982634 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 7548701 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 7548701 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 17501 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5735 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 7426 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 13099 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 43761 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu3.data 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 817075 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 250046 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 356623 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 570209 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1993953 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 5523274 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 1705507 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 3878392 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 4676120 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 15783293 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 2676699 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 794755 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 1091778 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 1978759 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 6541991 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 666998 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 114735 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu2.data 152915 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu3.data 290569 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1225217 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 161407 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 112478 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 5523274 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 3493774 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 55459 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 41969 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 1705507 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1044801 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 153863 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 57658 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 3878392 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 1448401 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.dtb.walker 293978 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.itb.walker 105822 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 4676120 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 2548968 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 25301871 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 161407 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 112478 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 5523274 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 3493774 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 55459 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 41969 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 1705507 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1044801 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 153863 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 57658 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 3878392 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 1448401 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.dtb.walker 293978 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.itb.walker 105822 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 4676120 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 2548968 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 25301871 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.008067 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012509 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005716 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.007220 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.007839 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003456 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.009053 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.006373 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784812 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781691 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.779020 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 0.786014 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.783780 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.500000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.223834 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.196276 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.190347 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 0.196558 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.206589 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006324 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.006406 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.006196 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.005994 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.006204 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.044028 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.037351 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.035090 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.038311 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.039996 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.572918 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.156718 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu2.data 0.186829 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu3.data 0.223338 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.402851 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.008067 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.012509 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006324 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.086079 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005716 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.007220 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.006406 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.075386 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003295 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.007839 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.006196 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.073317 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003456 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.itb.walker 0.009053 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.005994 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.073711 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.030739 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.008067 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.012509 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006324 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.086079 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005716 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.007220 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.006406 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.075386 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003295 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.007839 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.006196 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.073317 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003456 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.itb.walker 0.009053 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.005994 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.073711 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.030739 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86821.766562 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87396.039604 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85230.769231 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 84929.203540 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 87484.744094 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 89992.693111 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49616.895561 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15266.897167 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15696.629213 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15985.042735 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 9441.339398 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 40500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 40500 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80564.173357 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81136.206947 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 98128.244363 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 49668.223573 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81312.723112 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83067.246473 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 85245.585245 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 53862.449830 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82792.673067 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83334.625424 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 89549.288993 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 47539.126098 # average ReadSharedReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79504.087648 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 88326.035213 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 107781.454658 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::total 22179.640585 # average InvalidateReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86821.766562 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87396.039604 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81312.723112 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81404.072978 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85230.769231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 84929.203540 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 83067.246473 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 81929.312001 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 87484.744094 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.itb.walker 89992.693111 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 85245.585245 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 94666.836982 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 49479.576631 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86821.766562 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87396.039604 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81312.723112 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81404.072978 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85230.769231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 84929.203540 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 83067.246473 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 81929.312001 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 87484.744094 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.itb.walker 89992.693111 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 85245.585245 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 94666.836982 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 49479.576631 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2403,270 +2815,342 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1103217 # number of writebacks -system.l2c.writebacks::total 1103217 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.itb.walker 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2.data 5 # number of ReadSharedReq MSHR hits +system.l2c.writebacks::writebacks 982136 # number of writebacks +system.l2c.writebacks::total 982136 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.itb.walker 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2.data 3 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3.data 2 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.dtb.walker 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.itb.walker 22 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 38 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.dtb.walker 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.itb.walker 22 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 38 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 606 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 558 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 1489 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1349 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 4002 # number of ReadReq MSHR misses -system.l2c.CleanEvict_mshr_misses::writebacks 328 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 328 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5395 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 12690 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 18085 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76825 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 166750 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 243575 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 11588 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 35478 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 47066 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 35363 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2.data 110339 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 145702 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 28566 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu2.data 71958 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 100524 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 606 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 558 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 11588 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 112188 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 1489 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1349 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 35478 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 277089 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 440345 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 606 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 558 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 11588 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 112188 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 1489 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1349 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 35478 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 277089 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 440345 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 4998 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8152 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 13150 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4942 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 7788 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 12730 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 9940 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 15940 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 25880 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 46907500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 43526500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 115771000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 107384500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 313589500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 111371500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 263334500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 374706000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 139000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 20500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 159500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5407703000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 14927339500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 20335042500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 824324000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2681702500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 3506026500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 2571063000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 9088897000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 11659960000 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1991130000 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 6955976000 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 8947106000 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 46907500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 43526500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 824324000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 7978766000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 115771000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 107384500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 2681702500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 24016236500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 35814618500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 46907500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 43526500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 824324000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 7978766000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 115771000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 107384500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 2681702500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 24016236500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 35814618500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 763712000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1373074000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 2136786000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 770891000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1347269000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2118160000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1534603000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2720343000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4254946000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.008097 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011251 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003804 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.008737 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.004008 # mshr miss rate for ReadReq accesses +system.l2c.demand_mshr_hits::cpu2.data 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.dtb.walker 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.itb.walker 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.data 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.dtb.walker 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.itb.walker 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.data 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 25 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 317 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 303 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 507 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 452 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 1012 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 943 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 3534 # number of ReadReq MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 457 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 457 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4483 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 5785 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 10296 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 20564 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 49078 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 67882 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 112079 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 229039 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10925 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 24031 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 28030 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 62986 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 29685 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 38307 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 75806 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 143798 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 17981 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu2.data 28569 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu3.data 64895 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 111445 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 317 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 303 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10925 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 78763 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 507 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 452 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 24031 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 106189 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.dtb.walker 1012 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.itb.walker 943 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 28030 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 187885 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 439357 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 317 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 303 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10925 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 78763 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 507 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 452 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 24031 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 106189 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.dtb.walker 1012 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.itb.walker 943 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 28030 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 187885 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 439357 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6070 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 4638 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3.data 5330 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 16038 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5514 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4225 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3.data 5069 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 14808 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 11584 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 8863 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3.data 10399 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 30846 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 24352500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 23451000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 38142000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 33868000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 78456500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 75654000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 273924000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 92604000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 120054000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 213635500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 426293500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 91500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 91500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3463148500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4828868000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 9877325500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 18169342000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 779091500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1755879000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 2109208500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 4644179000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 2160850500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 2809328500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 6030368000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 11000547000 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1249753000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 2237696500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data 6345527500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 9832977000 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 24352500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 23451000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 779091500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5623999000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 38142000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 33868000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 1755879000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 7638196500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 78456500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 75654000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 2109208500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 15907693500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 34087992000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 24352500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 23451000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 779091500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5623999000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 38142000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 33868000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 1755879000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 7638196500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 78456500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 75654000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 2109208500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 15907693500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 34087992000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1003128500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 730361500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 841776000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2575266000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 936501000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 675184500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 836243500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2447929000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1939629500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1405546000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1678019500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5023195000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005716 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.007220 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003295 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.007839 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003442 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.008911 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.003596 # mshr miss rate for ReadReq accesses system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784841 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.785953 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.396740 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.142857 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.242929 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.229013 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.115643 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005529 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006094 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003245 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.034586 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.043041 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021251 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.200405 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.213975 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.081595 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008097 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011251 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005529 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.083803 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003804 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006094 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.084178 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.017998 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008097 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011251 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005529 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.083803 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003804 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006094 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.084178 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.017998 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 78358.195902 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20643.466172 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20751.339638 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20719.159524 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 20500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70389.886105 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 89519.277361 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 83485.753875 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71136.002761 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75587.758611 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74491.703140 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72704.889291 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 82372.479359 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80026.080630 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69702.793531 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 96667.166959 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 89004.675500 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71136.002761 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71119.602810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75587.758611 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86673.366680 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 81333.087693 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71136.002761 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71119.602810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75587.758611 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86673.366680 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 81333.087693 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152803.521409 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 168434.003925 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 162493.231939 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 155987.656819 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 172992.937853 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 166391.201885 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154386.619718 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 170661.417817 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 164410.587326 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781691 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.779020 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.786014 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.469916 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.196276 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.190347 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.196558 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.114867 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006406 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006196 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005994 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.037351 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.035087 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.038310 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021981 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.156718 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.186829 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.223338 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.090959 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005716 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006406 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.075386 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.007839 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.073315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003442 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.073710 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017365 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005716 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006406 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.075386 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.007839 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.073315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003442 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005994 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.073710 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017365 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77511.035654 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20656.703101 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20752.636128 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20749.368687 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20730.086559 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45750 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70564.173357 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71136.206947 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88128.244363 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 79328.594693 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71312.723112 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73067.246473 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75248.251873 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73733.512209 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72792.673067 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73337.209909 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79550.009234 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69504.087648 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78326.035213 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97781.454658 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 88231.656871 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71312.723112 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71404.072978 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73067.246473 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71930.204635 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75248.251873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84667.182053 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 77586.090582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71312.723112 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71404.072978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73067.246473 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71930.204635 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75248.251873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84667.182053 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 77586.090582 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165260.049423 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157473.372143 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 157931.707317 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160572.764684 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169840.587595 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 159806.982249 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 164972.085224 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 165311.250675 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 167440.391920 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158585.806160 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 161363.544572 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 162847.532905 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76733 # Transaction distribution -system.membus.trans_dist::ReadResp 468089 # Transaction distribution -system.membus.trans_dist::WriteReq 33644 # Transaction distribution -system.membus.trans_dist::WriteResp 33644 # Transaction distribution -system.membus.trans_dist::Writeback 1209847 # Transaction distribution -system.membus.trans_dist::CleanEvict 210029 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36410 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36413 # Transaction distribution -system.membus.trans_dist::ReadExReq 1013774 # Transaction distribution -system.membus.trans_dist::ReadExResp 1013774 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 391356 # Transaction distribution +system.membus.trans_dist::ReadReq 76737 # Transaction distribution +system.membus.trans_dist::ReadResp 451400 # Transaction distribution +system.membus.trans_dist::WriteReq 33647 # Transaction distribution +system.membus.trans_dist::WriteResp 33647 # Transaction distribution +system.membus.trans_dist::Writeback 1088767 # Transaction distribution +system.membus.trans_dist::CleanEvict 205338 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34966 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 34968 # Transaction distribution +system.membus.trans_dist::ReadExReq 904844 # Transaction distribution +system.membus.trans_dist::ReadExResp 904844 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 374663 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4261294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4390673 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 345792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4736465 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 62 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6756 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3881435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4010829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345611 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 345611 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4356440 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 160146208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 160315602 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7368448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7368448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 167684050 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 579 # Total snoops (count) -system.membus.snoop_fanout::samples 3078821 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144353760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 144523174 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7363392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7363392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 151886566 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 711 # Total snoops (count) +system.membus.snoop_fanout::samples 2826104 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3078821 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2826104 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3078821 # Request fanout histogram -system.membus.reqLayer0.occupancy 45758500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2826104 # Request fanout histogram +system.membus.reqLayer0.occupancy 51928000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1294500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1759000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3125844189 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3236688724 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2930708426 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2999492092 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 61033927 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 84543932 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2710,56 +3194,56 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 1510117 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 22871416 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8317119 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 16946911 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45584 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45593 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2106266 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2106266 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 14504828 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6856794 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1265720 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1231984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 43598497 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30808593 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 852484 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760318 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 77019892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 928472660 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1076191614 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3123312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6312032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2014099618 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 938060 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 51670008 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.040962 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.198203 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1501925 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23827607 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33647 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33647 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8029950 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 18099474 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43761 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43765 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1993953 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1993953 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15783383 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6542484 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1272617 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1225217 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47433804 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29504905 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 816519 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1737039 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 79492267 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1010303252 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1029626962 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2926248 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6100712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2048957174 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1001590 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 53371149 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039891 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195703 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 49553478 95.90% 95.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 2116530 4.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 51242120 96.01% 96.01% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 2129029 3.99% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 51670008 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 17416968994 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 53371149 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 20695529987 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 316500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 462000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 11880834300 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15394171442 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7217033015 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7879772837 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 275805669 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 290523250 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 649517949 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 715846054 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu2.kern.inst.arm 0 # number of arm instructions executed -system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu3.kern.inst.arm 0 # number of arm instructions executed +system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |