diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt | 4291 |
1 files changed, 2147 insertions, 2144 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index e7103dcb2..8e7b17b1a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.234984 # Number of seconds simulated -sim_ticks 51234983764500 # Number of ticks simulated -final_tick 51234983764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.274696 # Number of seconds simulated +sim_ticks 51274696167500 # Number of ticks simulated +final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 293597 # Simulator instruction rate (inst/s) -host_op_rate 345003 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16999127000 # Simulator tick rate (ticks/s) -host_mem_usage 723216 # Number of bytes of host memory used -host_seconds 3013.98 # Real time elapsed on the host -sim_insts 884896163 # Number of instructions simulated -sim_ops 1039832130 # Number of ops (including micro ops) simulated +host_inst_rate 298693 # Simulator instruction rate (inst/s) +host_op_rate 350975 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17280969451 # Simulator tick rate (ticks/s) +host_mem_usage 723560 # Number of bytes of host memory used +host_seconds 2967.12 # Real time elapsed on the host +sim_insts 886256415 # Number of instructions simulated +sim_ops 1041383802 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 129856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 125184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2903796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24969352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 34560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 29888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 811648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7348736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 94656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 89280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 2169408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 17774080 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 413120 # Number of bytes read from this memory -system.physmem.bytes_read::total 56893564 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2903796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 811648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 2169408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5884852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77105472 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 116160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 120000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2956980 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25219400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 40192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 37376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 753536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7117376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 92544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 94080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 2191808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 17867136 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430080 # Number of bytes read from this memory +system.physmem.bytes_read::total 57036668 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2956980 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 753536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 2191808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5902324 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77190720 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 77126052 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 85779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 390159 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 114824 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 1479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 33897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 277720 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6455 # Number of read requests responded to by this memory -system.physmem.num_reads::total 929382 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1204773 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77211300 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1875 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 394066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 584 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 11774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 111209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 1446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1470 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 34247 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 279174 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6720 # Number of read requests responded to by this memory +system.physmem.num_reads::total 931618 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1206105 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1207346 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 56676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 487350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 675 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 15842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 143432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 1847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 1743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 42342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 346913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1110444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 56676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 15842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 42342 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 114860 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1504938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1505340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1504938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 56676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 487751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 15842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 143432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 1847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 1743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 42342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 346913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2615783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443127 # Number of read requests accepted -system.physmem.writeReqs 607625 # Number of write requests accepted -system.physmem.readBursts 443127 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 607625 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28344960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 15168 # Total number of bytes read from write queue -system.physmem.bytesWritten 38801344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28360128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 38888000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 237 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1354 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18550 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25211 # Per bank write bursts -system.physmem.perBankRdBursts::1 29295 # Per bank write bursts -system.physmem.perBankRdBursts::2 27890 # Per bank write bursts -system.physmem.perBankRdBursts::3 27887 # Per bank write bursts -system.physmem.perBankRdBursts::4 27824 # Per bank write bursts -system.physmem.perBankRdBursts::5 30839 # Per bank write bursts -system.physmem.perBankRdBursts::6 26245 # Per bank write bursts -system.physmem.perBankRdBursts::7 26732 # Per bank write bursts -system.physmem.perBankRdBursts::8 26610 # Per bank write bursts -system.physmem.perBankRdBursts::9 29578 # Per bank write bursts -system.physmem.perBankRdBursts::10 29152 # Per bank write bursts -system.physmem.perBankRdBursts::11 31219 # Per bank write bursts -system.physmem.perBankRdBursts::12 26466 # Per bank write bursts -system.physmem.perBankRdBursts::13 26838 # Per bank write bursts -system.physmem.perBankRdBursts::14 25148 # Per bank write bursts -system.physmem.perBankRdBursts::15 25956 # Per bank write bursts -system.physmem.perBankWrBursts::0 36103 # Per bank write bursts -system.physmem.perBankWrBursts::1 37925 # Per bank write bursts -system.physmem.perBankWrBursts::2 36544 # Per bank write bursts -system.physmem.perBankWrBursts::3 38823 # Per bank write bursts -system.physmem.perBankWrBursts::4 41056 # Per bank write bursts -system.physmem.perBankWrBursts::5 42229 # Per bank write bursts -system.physmem.perBankWrBursts::6 37594 # Per bank write bursts -system.physmem.perBankWrBursts::7 36950 # Per bank write bursts -system.physmem.perBankWrBursts::8 37999 # Per bank write bursts -system.physmem.perBankWrBursts::9 38649 # Per bank write bursts -system.physmem.perBankWrBursts::10 38477 # Per bank write bursts -system.physmem.perBankWrBursts::11 38558 # Per bank write bursts -system.physmem.perBankWrBursts::12 34649 # Per bank write bursts -system.physmem.perBankWrBursts::13 36757 # Per bank write bursts -system.physmem.perBankWrBursts::14 36686 # Per bank write bursts -system.physmem.perBankWrBursts::15 37272 # Per bank write bursts +system.physmem.num_writes::total 1208678 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 57669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 491849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 138809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 1805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 1835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 348459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1112375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 57669 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 115112 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1505435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1505836 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1505435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 57669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 492250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 138809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 1805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 1835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 348459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2618211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 440592 # Number of read requests accepted +system.physmem.writeReqs 615308 # Number of write requests accepted +system.physmem.readBursts 440592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 615308 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28181248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue +system.physmem.bytesWritten 38332736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28197888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 39379712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 16359 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 18561 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25854 # Per bank write bursts +system.physmem.perBankRdBursts::1 28544 # Per bank write bursts +system.physmem.perBankRdBursts::2 25469 # Per bank write bursts +system.physmem.perBankRdBursts::3 27506 # Per bank write bursts +system.physmem.perBankRdBursts::4 26728 # Per bank write bursts +system.physmem.perBankRdBursts::5 30588 # Per bank write bursts +system.physmem.perBankRdBursts::6 26415 # Per bank write bursts +system.physmem.perBankRdBursts::7 27502 # Per bank write bursts +system.physmem.perBankRdBursts::8 26500 # Per bank write bursts +system.physmem.perBankRdBursts::9 31676 # Per bank write bursts +system.physmem.perBankRdBursts::10 27941 # Per bank write bursts +system.physmem.perBankRdBursts::11 30917 # Per bank write bursts +system.physmem.perBankRdBursts::12 25895 # Per bank write bursts +system.physmem.perBankRdBursts::13 27920 # Per bank write bursts +system.physmem.perBankRdBursts::14 25066 # Per bank write bursts +system.physmem.perBankRdBursts::15 25811 # Per bank write bursts +system.physmem.perBankWrBursts::0 36067 # Per bank write bursts +system.physmem.perBankWrBursts::1 36031 # Per bank write bursts +system.physmem.perBankWrBursts::2 34636 # Per bank write bursts +system.physmem.perBankWrBursts::3 37309 # Per bank write bursts +system.physmem.perBankWrBursts::4 37132 # Per bank write bursts +system.physmem.perBankWrBursts::5 40234 # Per bank write bursts +system.physmem.perBankWrBursts::6 38375 # Per bank write bursts +system.physmem.perBankWrBursts::7 37986 # Per bank write bursts +system.physmem.perBankWrBursts::8 35542 # Per bank write bursts +system.physmem.perBankWrBursts::9 42123 # Per bank write bursts +system.physmem.perBankWrBursts::10 38624 # Per bank write bursts +system.physmem.perBankWrBursts::11 39603 # Per bank write bursts +system.physmem.perBankWrBursts::12 35582 # Per bank write bursts +system.physmem.perBankWrBursts::13 38033 # Per bank write bursts +system.physmem.perBankWrBursts::14 36333 # Per bank write bursts +system.physmem.perBankWrBursts::15 35339 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 51233787261500 # Total gap between requests +system.physmem.numWrRetry 73 # Number of times write queue was full causing retry +system.physmem.totGap 51273531025000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443127 # Read request sizes (log2) +system.physmem.readPktSize::6 440592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 607625 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 312054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 615308 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 297815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 95022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -180,199 +180,206 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 474 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 468 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 24672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 28080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 33366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 36383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 37105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 38583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 39124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 40093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 39396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 38019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 37237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 37691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 33410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 31074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 274343 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.749383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.139289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 288.784627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 125431 45.72% 45.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 68607 25.01% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24542 8.95% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12363 4.51% 84.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8633 3.15% 87.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5464 1.99% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4467 1.63% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3979 1.45% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20857 7.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 274343 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 29886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.819313 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10.330264 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-15 12451 41.66% 41.66% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16-31 16121 53.94% 95.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-47 1059 3.54% 99.15% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::48-63 175 0.59% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-79 53 0.18% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::80-95 15 0.05% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-111 5 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::9 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 22598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 26146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 30213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 32129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 33829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 34268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 34523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 35690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 34679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 37755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 35326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 34217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 40396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 33787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 31090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 182 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 276595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.471737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.485529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.203347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 127319 46.03% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 69542 25.14% 71.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24812 8.97% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12377 4.47% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8866 3.21% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5372 1.94% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4514 1.63% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3651 1.32% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20142 7.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 276595 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 29231 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.063871 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.425422 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-15 11898 40.70% 40.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-31 15954 54.58% 95.28% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-47 1083 3.70% 98.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-63 204 0.70% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-79 56 0.19% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-95 22 0.08% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-111 6 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::128-143 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-271 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::304-319 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 29886 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 29886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.286121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.739916 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.649180 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 14 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 35 0.12% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 26501 88.67% 88.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 1006 3.37% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 913 3.05% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 433 1.45% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 255 0.85% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 96 0.32% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 167 0.56% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 135 0.45% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 90 0.30% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 37 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 67 0.22% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 27 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 22 0.07% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 15 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 37 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 7 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 29886 # Writes before turning the bus around for reads -system.physmem.totQLat 10134279500 # Total ticks spent queuing -system.physmem.totMemAccLat 18438467000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2214450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22882.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::176-191 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::288-303 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::320-335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 29231 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 29231 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.490199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.518949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.634153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 58 0.20% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 27476 94.00% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 804 2.75% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 250 0.86% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 169 0.58% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 102 0.35% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 99 0.34% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 124 0.42% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 61 0.21% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 8 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 19 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 14 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 5 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 7 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 29231 # Writes before turning the bus around for reads +system.physmem.totQLat 10175638298 # Total ticks spent queuing +system.physmem.totMemAccLat 18431863298 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2201660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23109.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41632.16 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41859.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 0.75 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.76 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.77 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.35 # Average write queue length when enqueuing -system.physmem.readRowHits 333517 # Number of row buffer hits during reads -system.physmem.writeRowHits 441289 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.79 # Row buffer hit rate for writes -system.physmem.avgGap 48759162.26 # Average gap between requests -system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1059231600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 575701500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1730999400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1990714320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3304502351280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1163638516455 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29573392417500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34046889932055 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.714209 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48801846776250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1689418380000 # Time in different power states +system.physmem.avgWrQLen 25.67 # Average write queue length when enqueuing +system.physmem.readRowHits 330665 # Number of row buffer hits during reads +system.physmem.writeRowHits 432014 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.13 # Row buffer hit rate for writes +system.physmem.avgGap 48559078.53 # Average gap between requests +system.physmem.pageHitRate 73.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1047672360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 569481000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1705126800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1929536640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3307165171440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1163738784870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29596559989500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34072715762610 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.713146 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48842268608197 # Time in different power states +system.physmem_0.memoryStateTime::REF 1690779740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 103138521750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102045610303 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1014703200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 551648625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1723542600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1937720880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3304502351280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1160546619285 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29579668954500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34049945540370 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.696345 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48806318983250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1689418380000 # Time in different power states +system.physmem_1.actEnergy 1043355600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 567088500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1729462800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1951549200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3307165171440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1164487973490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29604202640250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34081147241280 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.697375 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48841133395944 # Time in different power states +system.physmem_1.memoryStateTime::REF 1690779740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 98691186250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 103204176556 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -409,48 +416,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 113519 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 113519 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 113519 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 113519 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 113519 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 1125423795568 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.567721 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.495393 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 486496827068 43.23% 43.23% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 638926968500 56.77% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1125423795568 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 82853 84.60% 84.60% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 15081 15.40% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 97934 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 113519 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 113114 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 113114 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 113114 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 113114 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 113114 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 1113616699016 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.572841 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.494666 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 475691482516 42.72% 42.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 637925216500 57.28% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1113616699016 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 82726 84.85% 84.85% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 14770 15.15% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 97496 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 113114 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 113519 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97934 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 113114 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97496 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97934 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 211453 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97496 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 210610 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 78562985 # DTB read hits -system.cpu0.dtb.read_misses 85240 # DTB read misses -system.cpu0.dtb.write_hits 72018023 # DTB write hits -system.cpu0.dtb.write_misses 28279 # DTB write misses -system.cpu0.dtb.flush_tlb 1287 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 78321186 # DTB read hits +system.cpu0.dtb.read_misses 84847 # DTB read misses +system.cpu0.dtb.write_hits 71529400 # DTB write hits +system.cpu0.dtb.write_misses 28267 # DTB write misses +system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21013 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 51639 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 20997 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 507 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 51007 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3776 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4028 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9794 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78648225 # DTB read accesses -system.cpu0.dtb.write_accesses 72046302 # DTB write accesses +system.cpu0.dtb.perms_faults 9780 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78406033 # DTB read accesses +system.cpu0.dtb.write_accesses 71557667 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 150581008 # DTB hits -system.cpu0.dtb.misses 113519 # DTB misses -system.cpu0.dtb.accesses 150694527 # DTB accesses +system.cpu0.dtb.hits 149850586 # DTB hits +system.cpu0.dtb.misses 113114 # DTB misses +system.cpu0.dtb.accesses 149963700 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -480,432 +487,430 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 63212 # Table walker walks requested -system.cpu0.itb.walker.walksLong 63212 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 63212 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 63212 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 63212 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 1125423794068 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.567766 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.495387 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 486446960568 43.22% 43.22% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 638976833500 56.78% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1125423794068 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54978 95.14% 95.14% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2806 4.86% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 57784 # Table walker page sizes translated +system.cpu0.itb.walker.walks 63285 # Table walker walks requested +system.cpu0.itb.walker.walksLong 63285 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 63285 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 63285 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 63285 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 1113616695516 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.572887 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.494659 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 475639854016 42.71% 42.71% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 637976841500 57.29% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1113616695516 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 55054 95.20% 95.20% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2776 4.80% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57830 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63212 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63212 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63285 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63285 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57784 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57784 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 120996 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 421062407 # ITB inst hits -system.cpu0.itb.inst_misses 63212 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57830 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57830 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 121115 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 419986176 # ITB inst hits +system.cpu0.itb.inst_misses 63285 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1287 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21013 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 36180 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 20997 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 507 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 35884 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 421125619 # ITB inst accesses -system.cpu0.itb.hits 421062407 # DTB hits -system.cpu0.itb.misses 63212 # DTB misses -system.cpu0.itb.accesses 421125619 # DTB accesses -system.cpu0.numCycles 506570818 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 420049461 # ITB inst accesses +system.cpu0.itb.hits 419986176 # DTB hits +system.cpu0.itb.misses 63285 # DTB misses +system.cpu0.itb.accesses 420049461 # DTB accesses +system.cpu0.numCycles 505091044 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 420869800 # Number of instructions committed -system.cpu0.committedOps 495253800 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 454669961 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 407169 # Number of float alu accesses -system.cpu0.num_func_calls 25355566 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64011433 # number of instructions that are conditional controls -system.cpu0.num_int_insts 454669961 # number of integer instructions -system.cpu0.num_fp_insts 407169 # number of float instructions -system.cpu0.num_int_register_reads 669912724 # number of times the integer registers were read -system.cpu0.num_int_register_writes 361261423 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 658306 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 339356 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 110690043 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 110438637 # number of times the CC registers were written -system.cpu0.num_mem_refs 150674741 # number of memory refs -system.cpu0.num_load_insts 78636195 # Number of load instructions -system.cpu0.num_store_insts 72038546 # Number of store instructions -system.cpu0.num_idle_cycles 494843268.961767 # Number of idle cycles -system.cpu0.num_busy_cycles 11727549.038232 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023151 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976849 # Percentage of idle cycles -system.cpu0.Branches 93932517 # Number of branches fetched +system.cpu0.committedInsts 419794202 # Number of instructions committed +system.cpu0.committedOps 493796806 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 453197936 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 421943 # Number of float alu accesses +system.cpu0.num_func_calls 25265539 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 63928321 # number of instructions that are conditional controls +system.cpu0.num_int_insts 453197936 # number of integer instructions +system.cpu0.num_fp_insts 421943 # number of float instructions +system.cpu0.num_int_register_reads 668318275 # number of times the integer registers were read +system.cpu0.num_int_register_writes 360308744 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 682016 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 353392 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 110766057 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 110481712 # number of times the CC registers were written +system.cpu0.num_mem_refs 149944655 # number of memory refs +system.cpu0.num_load_insts 78394551 # Number of load instructions +system.cpu0.num_store_insts 71550104 # Number of store instructions +system.cpu0.num_idle_cycles 493080351.361326 # Number of idle cycles +system.cpu0.num_busy_cycles 12010692.638674 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023779 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976221 # Percentage of idle cycles +system.cpu0.Branches 93737042 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 343715794 69.36% 69.36% # Class of executed instruction -system.cpu0.op_class::IntMult 1059861 0.21% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 47874 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 49044 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 78636195 15.87% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 72038546 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 342973363 69.42% 69.42% # Class of executed instruction +system.cpu0.op_class::IntMult 1071330 0.22% 69.63% # Class of executed instruction +system.cpu0.op_class::IntDiv 48623 0.01% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 51721 0.01% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::MemRead 78394551 15.87% 85.52% # Class of executed instruction +system.cpu0.op_class::MemWrite 71550104 14.48% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 495547316 # Class of executed instruction +system.cpu0.op_class::total 494089735 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16313 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 10214702 # number of replacements +system.cpu0.dcache.tags.replacements 10220953 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999720 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 304791830 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10215214 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.837048 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 305187926 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10221465 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.857552 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.816800 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.965643 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.217276 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970345 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009699 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.019956 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.221457 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.755911 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 8.022352 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971136 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.013195 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.015669 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1295808199 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1295808199 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73344072 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 23670257 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 59561251 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156575580 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68109688 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 21690684 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 50098487 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 139898859 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 192172 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58926 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 140820 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 391918 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 149127 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 52869 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 128452 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 330448 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1807582 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 555748 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1239879 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3603209 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1920927 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 598964 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1426295 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3946186 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 141453760 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 45360941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 109659738 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 296474439 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 141645932 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 45419867 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 109800558 # number of overall hits -system.cpu0.dcache.overall_hits::total 296866357 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2534039 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 789361 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 4745712 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 8069112 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1082533 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 339457 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 4257122 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5679112 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 624926 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 200468 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 451799 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1277193 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 751391 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 141795 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu2.data 340989 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1234175 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 114175 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 43476 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 234793 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 392444 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1297346809 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1297346809 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73103498 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 24004695 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 59713819 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156822012 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67621876 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 22136915 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 50273570 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 140032361 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 191205 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58550 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 144781 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 394536 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 151179 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 54099 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 126065 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 331343 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1805832 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 567281 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1240318 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3613431 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1916828 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 614023 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1418006 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3948857 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 140725374 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 46141610 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 109987389 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 296854373 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 140916579 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 46200160 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 110132170 # number of overall hits +system.cpu0.dcache.overall_hits::total 297248909 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2537446 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 778664 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 4676407 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7992517 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1084233 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 329896 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 4337927 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 5752056 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 625359 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 184328 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 464541 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1274228 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 751309 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 143971 # 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average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 47500 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19729.141289 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23481.873364 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16991.752768 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16916.342999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22331.072986 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15550.135215 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 14700393 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25808 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1130734 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 457 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.000753 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 56.472648 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7876656 # number of writebacks -system.cpu0.dcache.writebacks::total 7876656 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 1060 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2696706 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2697766 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 3203 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3527121 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3530324 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data 2450 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 2450 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 10619 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 143143 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 153762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 4263 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 6223827 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 6228090 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 4263 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 6223827 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 146500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 202999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19410768882 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 55596137872 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 75006906754 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22377765382 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 64782643827 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 87160409209 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 886387500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1429299000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2315686500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 799886500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1453115957 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2253002457 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1686274000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2882414957 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4568688957 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032229 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017233 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015263 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013430 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.772612 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.750803 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.386644 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.728409 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.721153 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.306997 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054833 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.062149 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031161 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 1104626 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 2807222 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 3911848 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 1288838 # 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number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 184000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 20066054383 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 54721440751 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 74787495134 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22783073883 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 62807969010 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 85591042893 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 895108750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1474898001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2370006751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 895104500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1438317956 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2333422456 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1790213250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2913215957 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4703429207 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031330 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.032110 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017256 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014606 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013544 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758455 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.746313 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.382892 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.726869 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.723656 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.306874 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059658 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060507 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031364 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024189 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023419 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.012583 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027034 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.014585 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13174.512020 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15018.399262 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14506.104274 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26840.685559 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34004.539272 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31745.347553 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14804.559131 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20646.617420 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18832.391141 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15614.478635 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29214.023956 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25199.426761 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12459.369389 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12636.193464 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12589.530155 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33833.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17260.844407 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20005.756686 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19214.990502 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16889.312920 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20094.202488 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19160.711407 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023378 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023590 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.012595 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027137 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027271 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.014573 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13969.532503 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14813.666446 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14583.200315 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28093.961722 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32572.882762 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31196.486788 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14749.416433 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 17782.555628 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.098290 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 18686.985567 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 20406.521061 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 19891.191595 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12659.081608 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12920.839934 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12844.355241 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 46000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18165.473548 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19493.093439 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19118.200690 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -916,142 +921,142 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 14521093 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.976902 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 611027566 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14521605 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.077137 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9055108500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.542496 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.290435 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.143971 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.971763 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.008380 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019812 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 14550991 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.976833 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 611237841 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14551503 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.005135 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9058621500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 496.705744 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.210417 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.060673 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.970128 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.010177 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019650 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999955 # 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miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015691 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015337 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089419 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023873 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015691 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015337 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089419 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023873 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13430.431356 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13330.867342 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7449.834453 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13430.431356 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13330.867342 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7449.834453 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13430.431356 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13330.867342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7449.834453 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 42762 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 640780747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 640780747 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 413451033 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 134065919 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 63720889 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 70003732 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 626229125 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 420044006 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 136181387 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 70003732 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 626229125 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015696 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015534 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089750 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023939 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015696 # 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number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 2115468 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 5843181 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 7958649 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 2115468 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 5843181 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 7958649 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 25161480508 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 69932206790 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 95093687298 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 25161480508 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 69932206790 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 95093687298 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 25161480508 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 69932206790 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 95093687298 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012709 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012709 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012709 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11948.471066 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11948.471066 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11948.471066 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1082,72 +1087,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 39379 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 39379 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 5977 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 28234 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 39373 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.279379 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 55.436197 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 39372 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::10240-11263 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 39373 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 34217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21462.701289 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17640.355852 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13201.639709 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 33415 97.66% 97.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 571 1.67% 99.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 171 0.50% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 26 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 5 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 6 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 6 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 34217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1508431008 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.298098 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.457423 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1058770000 70.19% 70.19% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 449661008 29.81% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1508431008 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 28234 82.53% 82.53% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 5977 17.47% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 34211 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 39379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 40069 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 40069 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6011 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 28822 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 40066 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.287026 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 57.452621 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-1023 40065 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 40066 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 34836 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23148.919221 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19687.951217 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13456.896972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 22742 65.28% 65.28% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 11809 33.90% 99.18% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 149 0.43% 99.61% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 100 0.29% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 8 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 34836 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2552299344 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.586801 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.492408 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1054607500 41.32% 41.32% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1497691844 58.68% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2552299344 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 28822 82.74% 82.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6011 17.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 34833 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 40069 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 39379 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 34211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 40069 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 34833 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 34211 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 73590 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 34833 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 74902 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25323699 # DTB read hits -system.cpu1.dtb.read_misses 30085 # DTB read misses -system.cpu1.dtb.write_hits 22831654 # DTB write hits -system.cpu1.dtb.write_misses 9294 # DTB write misses -system.cpu1.dtb.flush_tlb 1278 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25646035 # DTB read hits +system.cpu1.dtb.read_misses 30818 # DTB read misses +system.cpu1.dtb.write_hits 23287178 # DTB write hits +system.cpu1.dtb.write_misses 9251 # DTB write misses +system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 6693 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 149 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 21869 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 6462 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 159 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 22057 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1270 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1362 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 3016 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25353784 # DTB read accesses -system.cpu1.dtb.write_accesses 22840948 # DTB write accesses +system.cpu1.dtb.perms_faults 2875 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25676853 # DTB read accesses +system.cpu1.dtb.write_accesses 23296429 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 48155353 # DTB hits -system.cpu1.dtb.misses 39379 # DTB misses -system.cpu1.dtb.accesses 48194732 # DTB accesses +system.cpu1.dtb.hits 48933213 # DTB hits +system.cpu1.dtb.misses 40069 # DTB misses +system.cpu1.dtb.accesses 48973282 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1177,135 +1180,137 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 23659 # Table walker walks requested -system.cpu1.itb.walker.walksLong 23659 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1141 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20683 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 23659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 23659 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 23659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 21824 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24542.418897 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21182.327207 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14187.388293 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 20284 92.94% 92.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 1308 5.99% 98.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 160 0.73% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 37 0.17% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 9 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 7 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 21824 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 23826 # Table walker walks requested +system.cpu1.itb.walker.walksLong 23826 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1156 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20921 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 23826 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 23826 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 23826 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 22077 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26240.136794 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22930.281403 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15976.450560 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 11277 51.08% 51.08% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 10485 47.49% 98.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 121 0.55% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 153 0.69% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 7 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 22077 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 20683 94.77% 94.77% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1141 5.23% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 21824 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 20921 94.76% 94.76% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1156 5.24% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 22077 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23659 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23659 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23826 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23826 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 21824 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 21824 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 45483 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 134740091 # ITB inst hits -system.cpu1.itb.inst_misses 23659 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 22077 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 22077 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 45903 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 136181387 # ITB inst hits +system.cpu1.itb.inst_misses 23826 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1278 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 6693 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 149 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 16092 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 6462 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 159 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 16176 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 134763750 # ITB inst accesses -system.cpu1.itb.hits 134740091 # DTB hits -system.cpu1.itb.misses 23659 # DTB misses -system.cpu1.itb.accesses 134763750 # DTB accesses -system.cpu1.numCycles 1278124825 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 136205213 # ITB inst accesses +system.cpu1.itb.hits 136181387 # DTB hits +system.cpu1.itb.misses 23826 # DTB misses +system.cpu1.itb.accesses 136205213 # DTB accesses +system.cpu1.numCycles 1276125055 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 134646225 # Number of instructions committed -system.cpu1.committedOps 158126706 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 145069492 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 137737 # Number of float alu accesses -system.cpu1.num_func_calls 7885244 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 20644863 # number of instructions that are conditional controls -system.cpu1.num_int_insts 145069492 # number of integer instructions -system.cpu1.num_fp_insts 137737 # number of float instructions -system.cpu1.num_int_register_reads 212132646 # number of times the integer registers were read -system.cpu1.num_int_register_writes 115229722 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 221669 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 118820 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35576682 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 35511484 # number of times the CC registers were written -system.cpu1.num_mem_refs 48152949 # number of memory refs -system.cpu1.num_load_insts 25322940 # Number of load instructions -system.cpu1.num_store_insts 22830009 # Number of store instructions -system.cpu1.num_idle_cycles 1251340382.439470 # Number of idle cycles -system.cpu1.num_busy_cycles 26784442.560530 # Number of busy cycles -system.cpu1.not_idle_fraction 0.020956 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.979044 # Percentage of idle cycles -system.cpu1.Branches 30070128 # Number of branches fetched +system.cpu1.committedInsts 136088494 # Number of instructions committed +system.cpu1.committedOps 159971532 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 146914767 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 136439 # Number of float alu accesses +system.cpu1.num_func_calls 8067189 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 20777484 # number of instructions that are conditional controls +system.cpu1.num_int_insts 146914767 # number of integer instructions +system.cpu1.num_fp_insts 136439 # number of float instructions +system.cpu1.num_int_register_reads 213265371 # number of times the integer registers were read +system.cpu1.num_int_register_writes 116491926 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 215836 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 125376 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 35465151 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 35400633 # number of times the CC registers were written +system.cpu1.num_mem_refs 48930269 # number of memory refs +system.cpu1.num_load_insts 25645213 # Number of load instructions +system.cpu1.num_store_insts 23285056 # Number of store instructions +system.cpu1.num_idle_cycles 1249288140.787440 # Number of idle cycles +system.cpu1.num_busy_cycles 26836914.212560 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021030 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978970 # Percentage of idle cycles +system.cpu1.Branches 30426471 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 109684380 69.32% 69.32% # Class of executed instruction -system.cpu1.op_class::IntMult 350403 0.22% 69.55% # Class of executed instruction -system.cpu1.op_class::IntDiv 14329 0.01% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 18470 0.01% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::MemRead 25322940 16.00% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 22830009 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 110766463 69.20% 69.20% # Class of executed instruction +system.cpu1.op_class::IntMult 334649 0.21% 69.41% # Class of executed instruction +system.cpu1.op_class::IntDiv 13512 0.01% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 19532 0.01% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::MemRead 25645213 16.02% 85.45% # Class of executed instruction +system.cpu1.op_class::MemWrite 23285056 14.55% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 158220572 # Class of executed instruction +system.cpu1.op_class::total 160064425 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 97203672 # Number of BP lookups -system.cpu2.branchPred.condPredicted 66186757 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 4359750 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 65808751 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 47109720 # Number of BTB hits +system.cpu2.branchPred.lookups 97087615 # Number of BP lookups +system.cpu2.branchPred.condPredicted 66103650 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 4347660 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 66231841 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 47108077 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.585799 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 12465679 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 131865 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.126027 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 12454763 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 133862 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1335,81 +1340,88 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 641865 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 641865 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11159 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 66692 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 388613 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 253252 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 1931.812977 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 11499.357470 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-65535 251854 99.45% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-131071 1074 0.42% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::131072-196607 172 0.07% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::196608-262143 83 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::262144-327679 31 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 253252 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 288612 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 20860.236245 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 16529.214515 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 15237.417207 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 285772 99.02% 99.02% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-131071 2386 0.83% 99.84% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 259 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 137 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 41 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 288612 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 644386966916 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.557890 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.603276 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-3 643756648416 99.90% 99.90% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-7 358289000 0.06% 99.96% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-11 119891000 0.02% 99.98% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-15 74898000 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-19 28944500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-23 14290500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-27 13699500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::28-31 16934500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::32-35 3107500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walks 649855 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 649855 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11017 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 66935 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 396890 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 252965 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 2053.590418 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 12193.038070 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-65535 251454 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-131071 1182 0.47% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::131072-196607 177 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::262144-327679 45 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::393216-458751 17 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 252965 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 293492 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 21382.093181 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 17292.884496 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 15231.620197 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 288902 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-131071 4097 1.40% 99.83% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 265 0.09% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 159 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 56 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 293492 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 636867012660 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.530422 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.615162 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-3 636197778160 99.89% 99.89% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-7 383895000 0.06% 99.96% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-11 122059000 0.02% 99.97% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-15 78250500 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-19 30640500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-23 15817000 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-27 14461500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-31 20012000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::32-35 3793500 0.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::36-39 253000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::40-43 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 644386966916 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 66692 85.67% 85.67% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 11159 14.33% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 77851 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 641865 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walksPending::40-43 22000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::44-47 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::48-51 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::56-59 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 636867012660 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 66935 85.87% 85.87% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 11017 14.13% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 77952 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 649855 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 641865 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 77851 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 649855 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 77952 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 77851 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 719716 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 77952 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 727807 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 77755602 # DTB read hits -system.cpu2.dtb.read_misses 445998 # DTB read misses -system.cpu2.dtb.write_hits 59736492 # DTB write hits -system.cpu2.dtb.write_misses 195867 # DTB write misses -system.cpu2.dtb.flush_tlb 1279 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 77417011 # DTB read hits +system.cpu2.dtb.read_misses 450124 # DTB read misses +system.cpu2.dtb.write_hits 59942200 # DTB write hits +system.cpu2.dtb.write_misses 199731 # DTB write misses +system.cpu2.dtb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 14489 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 395 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 38251 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 105 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 6104 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 14741 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 38279 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 93 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 6471 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 37697 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 78201600 # DTB read accesses -system.cpu2.dtb.write_accesses 59932359 # DTB write accesses +system.cpu2.dtb.perms_faults 38915 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 77867135 # DTB read accesses +system.cpu2.dtb.write_accesses 60141931 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 137492094 # DTB hits -system.cpu2.dtb.misses 641865 # DTB misses -system.cpu2.dtb.accesses 138133959 # DTB accesses +system.cpu2.dtb.hits 137359211 # DTB hits +system.cpu2.dtb.misses 649855 # DTB misses +system.cpu2.dtb.accesses 138009066 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1439,396 +1451,397 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 80363 # Table walker walks requested -system.cpu2.itb.walker.walksLong 80363 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2481 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 55642 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 10291 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 70072 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1335.283708 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 8007.621087 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-32767 69580 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-65535 258 0.37% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-98303 168 0.24% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::98304-131071 29 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::131072-163839 18 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walks 80378 # Table walker walks requested +system.cpu2.itb.walker.walksLong 80378 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2425 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 10589 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 69789 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1377.194114 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 8185.559112 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-32767 69315 99.32% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-65535 221 0.32% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-98303 162 0.23% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::98304-131071 61 0.09% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu2.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 70072 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 68414 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 25615.416172 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 21446.317164 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 15929.809681 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 60316 88.16% 88.16% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 7055 10.31% 98.48% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 610 0.89% 99.37% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 277 0.40% 99.77% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 68 0.10% 99.87% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 37 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 13 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 11 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 68414 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 468293315780 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.887572 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.316276 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 52695891356 11.25% 11.25% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 415558218424 88.74% 99.99% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 33808000 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 3984500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 940500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::5 404000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::6 21500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::7 47500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 468293315780 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 55642 95.73% 95.73% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 2481 4.27% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 58123 # Table walker page sizes translated +system.cpu2.itb.walker.walkWaitTime::total 69789 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 68780 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 26602.237307 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 22568.644275 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 16910.110071 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 37031 53.84% 53.84% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 30619 44.52% 98.36% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 406 0.59% 98.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 526 0.76% 99.71% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 70 0.10% 99.81% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 66 0.10% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 22 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 14 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 68780 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 465075818820 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.908790 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.288323 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 42467517784 9.13% 9.13% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 422566839536 90.86% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 36100000 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 4751500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 426500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 73000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::6 66000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::7 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 465075818820 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 55766 95.83% 95.83% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 2425 4.17% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 58191 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 80363 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 80363 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 80378 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 80378 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 58123 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 58123 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 138486 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 70281222 # ITB inst hits -system.cpu2.itb.inst_misses 80363 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 58191 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 58191 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 138569 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70175055 # ITB inst hits +system.cpu2.itb.inst_misses 80378 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1279 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 14489 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 395 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 29841 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 14741 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 30057 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 147172 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 147979 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70361585 # ITB inst accesses -system.cpu2.itb.hits 70281222 # DTB hits -system.cpu2.itb.misses 80363 # DTB misses -system.cpu2.itb.accesses 70361585 # DTB accesses -system.cpu2.numCycles 465003102 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70255433 # ITB inst accesses +system.cpu2.itb.hits 70175055 # DTB hits +system.cpu2.itb.misses 80378 # DTB misses +system.cpu2.itb.accesses 70255433 # DTB accesses +system.cpu2.numCycles 460136549 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 180276648 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 431826640 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 97203672 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 59575399 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 257301281 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 9838745 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 1858453 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 8409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1979 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 3769521 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 119476 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 4195 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 70111000 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 2676908 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 31653 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 448259178 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.125687 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.367693 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 178152693 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 431776536 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 97087615 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 59562840 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 255654820 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 9805571 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 1895155 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 7918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1866 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 3768954 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 115299 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 5484 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 70003785 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 2663761 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 31715 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 444504807 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.135202 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.375157 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 341932387 76.28% 76.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 13442109 3.00% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 13673824 3.05% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 9898176 2.21% 84.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 19945540 4.45% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 6633561 1.48% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 7181223 1.60% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 6340938 1.41% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 29211420 6.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 338236255 76.09% 76.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 13308034 2.99% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 13681319 3.08% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 9908939 2.23% 84.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 20069262 4.51% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 6632314 1.49% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 7130783 1.60% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 6321378 1.42% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 29216523 6.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 448259178 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.209039 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.928653 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 147221492 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 209051737 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 78610938 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 9453516 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 3919439 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 14421531 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 1013878 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 471467563 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 3120361 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 3919439 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 152659562 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18224952 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 165892682 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82476717 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 25083567 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 460107253 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 59923 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 1862817 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 1245864 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 11710592 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 3796 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 439693345 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 700325975 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 542687716 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 700561 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 367082877 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 72610468 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 9962331 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 8523572 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 52244758 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 74674759 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 62877107 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 9528051 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 10323504 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 437324992 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 9951593 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 435965427 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 606984 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 56598171 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 39504404 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 237598 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 448259178 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.972574 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.684760 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 444504807 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.210997 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.938366 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 145587242 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 206867789 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 78822121 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 9322949 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 3902682 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 14396196 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 1015243 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 471778409 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 3111772 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 3902682 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 151005109 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 15075303 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 166939616 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82595953 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 24983877 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 460482983 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 55875 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 1575989 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 1122405 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 11824382 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 2747 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 440049969 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 701739830 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 543201034 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 591948 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 368298602 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 71751367 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 10111591 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 8659381 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 51276485 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 74779146 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 63098170 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 9504759 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 10253668 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 437555873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10088471 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 436351243 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 628919 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 55749778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 38531819 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 239828 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 444504807 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.981657 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.695270 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 279914977 62.44% 62.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 68317821 15.24% 77.69% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 32057682 7.15% 84.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22901153 5.11% 89.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 17277675 3.85% 93.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 11955785 2.67% 96.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 7990147 1.78% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 4753228 1.06% 99.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 3090710 0.69% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 276381275 62.18% 62.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 68338590 15.37% 77.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 31936602 7.18% 84.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 22769301 5.12% 89.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 16982310 3.82% 93.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 11978521 2.69% 96.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 8056839 1.81% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 4822285 1.08% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 3239084 0.73% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 448259178 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 444504807 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2208249 25.46% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 17979 0.21% 25.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 1386 0.02% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 1 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 3543832 40.86% 66.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 2901485 33.45% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2174414 25.25% 25.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 16907 0.20% 25.44% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 1448 0.02% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 3443156 39.98% 65.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 2977212 34.57% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 294954302 67.66% 67.66% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 1046783 0.24% 67.90% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 49286 0.01% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 204 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 50291 0.01% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 79323839 18.19% 86.11% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 60540722 13.89% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 20 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 295429003 67.70% 67.70% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 1051015 0.24% 67.95% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50004 0.01% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 103 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 46521 0.01% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 79012045 18.11% 86.07% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 60762532 13.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 435965427 # Type of FU issued -system.cpu2.iq.rate 0.937554 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 8672932 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.019894 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 1328634186 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 503978442 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 419353037 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 835762 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 397688 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 361980 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 444191291 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 447068 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 3425545 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 436351243 # Type of FU issued +system.cpu2.iq.rate 0.948308 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 8613137 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.019739 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 1325660566 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 503495404 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 420349481 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 788783 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 388209 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 352523 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 444542452 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 421908 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 3464909 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 12352202 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 15972 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 509888 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 6626020 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 12199650 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 16692 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 497657 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 6603925 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 2713782 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 6189069 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 2708670 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 5665546 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 3919439 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10963120 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 5851568 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 447374999 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 1338773 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 74674759 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 62877107 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 8331773 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 175433 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 5598830 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 509888 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 2010429 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1729641 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3740070 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 430866261 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77742862 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 4466264 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 3902682 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10385108 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 3443992 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 447742813 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 1337786 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 74779146 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 63098170 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 8466807 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 165633 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3216656 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 497657 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 2020710 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1734931 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3755641 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 431226765 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77404459 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 4484174 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 98414 # number of nop insts executed -system.cpu2.iew.exec_refs 137478821 # number of memory reference insts executed -system.cpu2.iew.exec_branches 79993995 # Number of branches executed -system.cpu2.iew.exec_stores 59735959 # Number of stores executed -system.cpu2.iew.exec_rate 0.926588 # Inst execution rate -system.cpu2.iew.wb_sent 420591447 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 419715017 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 207428552 # num instructions producing a value -system.cpu2.iew.wb_consumers 360230847 # num instructions consuming a value +system.cpu2.iew.exec_nop 98469 # number of nop insts executed +system.cpu2.iew.exec_refs 137346126 # number of memory reference insts executed +system.cpu2.iew.exec_branches 80126150 # Number of branches executed +system.cpu2.iew.exec_stores 59941667 # Number of stores executed +system.cpu2.iew.exec_rate 0.937171 # Inst execution rate +system.cpu2.iew.wb_sent 421619050 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 420702004 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 208179390 # num instructions producing a value +system.cpu2.iew.wb_consumers 361509938 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.902607 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575821 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.914298 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575861 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 60870503 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9713995 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 3359660 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 437963055 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.882384 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.879484 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 60056737 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9848643 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 3347389 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 434346973 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.892410 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.889968 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 298875540 68.24% 68.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 66218430 15.12% 83.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 24721461 5.64% 89.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 11149325 2.55% 91.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 8001884 1.83% 93.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 4923567 1.12% 94.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 4422174 1.01% 95.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 3021510 0.69% 96.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 16629164 3.80% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 295032576 67.93% 67.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 66481508 15.31% 83.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 24486149 5.64% 88.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 11154018 2.57% 91.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 8043816 1.85% 93.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 4878030 1.12% 94.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 4540806 1.05% 95.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 2951206 0.68% 96.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 16778864 3.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 437963055 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 329380138 # Number of instructions committed -system.cpu2.commit.committedOps 386451624 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 434346973 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 330373719 # Number of instructions committed +system.cpu2.commit.committedOps 387615464 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 118573644 # Number of memory references committed -system.cpu2.commit.loads 62322557 # Number of loads committed -system.cpu2.commit.membars 2596368 # Number of memory barriers committed -system.cpu2.commit.branches 73601182 # Number of branches committed -system.cpu2.commit.fp_insts 348235 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 355043998 # Number of committed integer instructions. -system.cpu2.commit.function_calls 9589619 # Number of function calls committed. +system.cpu2.commit.refs 119073741 # Number of memory references committed +system.cpu2.commit.loads 62579496 # Number of loads committed +system.cpu2.commit.membars 2588612 # Number of memory barriers committed +system.cpu2.commit.branches 73762518 # Number of branches committed +system.cpu2.commit.fp_insts 337914 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 356071087 # Number of committed integer instructions. +system.cpu2.commit.function_calls 9588871 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 267002089 69.09% 69.09% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 796041 0.21% 69.30% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 36743 0.01% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 43107 0.01% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 62322557 16.13% 85.44% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 56251087 14.56% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 267662094 69.05% 69.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 802922 0.21% 69.26% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 37337 0.01% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 39370 0.01% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 62579496 16.14% 85.43% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 56494245 14.57% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 386451624 # Class of committed instruction -system.cpu2.commit.bw_lim_events 16629164 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 387615464 # Class of committed instruction +system.cpu2.commit.bw_lim_events 16778864 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 866035132 # The number of ROB reads -system.cpu2.rob.rob_writes 904953656 # The number of ROB writes -system.cpu2.timesIdled 2976137 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 16743924 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 99448354933 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 329380138 # Number of Instructions Simulated -system.cpu2.committedOps 386451624 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.411752 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.411752 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.708340 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.708340 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 506713870 # number of integer regfile reads -system.cpu2.int_regfile_writes 300217827 # number of integer regfile writes -system.cpu2.fp_regfile_reads 684649 # number of floating regfile reads -system.cpu2.fp_regfile_writes 429068 # number of floating regfile writes -system.cpu2.cc_regfile_reads 91867416 # number of cc regfile reads -system.cpu2.cc_regfile_writes 92641749 # number of cc regfile writes -system.cpu2.misc_regfile_reads 1672272175 # number of misc regfile reads -system.cpu2.misc_regfile_writes 9817116 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40335 # Transaction distribution -system.iobus.trans_dist::ReadResp 40335 # Transaction distribution -system.iobus.trans_dist::WriteReq 136665 # Transaction distribution -system.iobus.trans_dist::WriteResp 30001 # Transaction distribution +system.cpu2.rob.rob_reads 862595097 # The number of ROB reads +system.cpu2.rob.rob_writes 905518660 # The number of ROB writes +system.cpu2.timesIdled 2960768 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 15631742 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 99536690500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 330373719 # Number of Instructions Simulated +system.cpu2.committedOps 387615464 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.392776 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.392776 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.717991 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.717991 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 507371314 # number of integer regfile reads +system.cpu2.int_regfile_writes 300778245 # number of integer regfile writes +system.cpu2.fp_regfile_reads 673893 # number of floating regfile reads +system.cpu2.fp_regfile_writes 409456 # number of floating regfile writes +system.cpu2.cc_regfile_reads 92253105 # number of cc regfile reads +system.cpu2.cc_regfile_writes 93114012 # number of cc regfile writes +system.cpu2.misc_regfile_reads 1670741863 # number of misc regfile reads +system.cpu2.misc_regfile_writes 9943766 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40265 # Transaction distribution +system.iobus.trans_dist::ReadResp 40265 # Transaction distribution +system.iobus.trans_dist::WriteReq 136537 # Transaction distribution +system.iobus.trans_dist::WriteResp 29873 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48070 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1843,13 +1856,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353604 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1864,87 +1877,87 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13687000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13825000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 7449000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 8203000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 16992000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 16991000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 331631076 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 196611881 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 38629000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39351000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36767371 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36922037 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 80000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.417241 # Cycle average of tags in use +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.421568 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13085934181009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.549977 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.867264 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221874 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429204 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651078 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13085930884009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547277 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.874291 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221705 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429643 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651348 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses +system.iocache.tags.tag_accesses 1039659 # Number of tag accesses +system.iocache.tags.data_accesses 1039659 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8820 # number of demand (read+write) misses -system.iocache.demand_misses::total 8860 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses +system.iocache.demand_misses::total 8854 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8820 # number of overall misses -system.iocache.overall_misses::total 8860 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 2752000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 78330160 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 81082160 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9376503545 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9376503545 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 2752000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 78330160 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 81082160 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 2752000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 78330160 # number of overall miss cycles -system.iocache.overall_miss_latency::total 81082160 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8814 # number of overall misses +system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 2432000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 61206163 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 63638163 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6636577681 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6636577681 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 2432000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 61206163 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 63638163 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 2432000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 61206163 # number of overall miss cycles +system.iocache.overall_miss_latency::total 63638163 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8820 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8860 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8820 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8860 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1958,416 +1971,410 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 8880.970522 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 9154.585074 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87906.918407 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 87906.918407 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 8880.970522 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 9151.485327 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 8880.970522 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 9151.485327 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 58174 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 65729.729730 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 6944.198207 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 7189.940459 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 62219.471246 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 62219.471246 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 60800 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 6944.198207 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 7187.504292 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 60800 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 6944.198207 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 7187.504292 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 24555 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7340 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3712 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.925613 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.615032 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 459 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 34504 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 34504 # number of WriteInvalidateReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 424 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 35584 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 35584 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 459 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 424 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 459 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 475 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1920000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 54458660 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 56378660 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7582053787 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7582053787 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 1920000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 54458660 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 56378660 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 1920000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 54458660 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 56378660 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 424 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 440 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1600000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 38938201 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 40538201 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4786173717 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4786173717 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 1600000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 38938201 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 40538201 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 1600000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 38938201 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 40538201 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.053630 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.323483 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.323483 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.049712 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.333608 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.333608 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.053612 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.049695 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.053612 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 120000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 118646.318083 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 118691.915789 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219744.197397 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219744.197397 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 118646.318083 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 118691.915789 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 118646.318083 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 118691.915789 # average overall mshr miss latency +system.iocache.overall_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.049695 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 91835.379717 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 92132.275000 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134503.532964 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134503.532964 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 100000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 91835.379717 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 92132.275000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 100000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 91835.379717 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 92132.275000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1296056 # number of replacements -system.l2c.tags.tagsinuse 65324.265743 # Cycle average of tags in use -system.l2c.tags.total_refs 28829950 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1358778 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.217557 # Average number of references to valid blocks. +system.l2c.tags.replacements 1296366 # number of replacements +system.l2c.tags.tagsinuse 65320.100787 # Cycle average of tags in use +system.l2c.tags.total_refs 28848747 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1358615 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.233938 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37285.924880 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 168.149057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 240.751709 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3675.446789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8312.608354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 50.722331 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 75.631311 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1066.604817 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3135.281683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 117.351685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 183.998379 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2140.151911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 8871.642837 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.568938 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003674 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.126840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000774 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.016275 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.047841 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001791 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.002808 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032656 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.135371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996769 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 311 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 310 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4926 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54001 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004745 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.952316 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 273473120 # Number of tag accesses -system.l2c.tags.data_accesses 273473120 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 199000 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 127150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6565279 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73925.270446 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 69662.173862 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20456.882185 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 26943.763266 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 25030.403741 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10004.602396 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.512234 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60250 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 43500.333333 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61375.342097 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 82629.743678 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75956.062337 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62052.824983 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 79214.264043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 73157.282017 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62052.824983 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 79214.264043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 73157.282017 # average overall mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.237202 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.229828 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.115309 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.084449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.083799 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017972 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.084449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.083799 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017972 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70684.888876 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 80226.246291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 76625.596229 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31506.347922 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 32994.424201 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32557.461479 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17532.667268 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17754.370121 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17687.229290 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68006.622871 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 88461.348427 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82062.371797 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68853.054520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68853.054520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2565,55 +2568,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 464425 # Transaction distribution -system.membus.trans_dist::ReadResp 464425 # Transaction distribution -system.membus.trans_dist::WriteReq 33772 # Transaction distribution -system.membus.trans_dist::WriteResp 33772 # Transaction distribution -system.membus.trans_dist::Writeback 1204773 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 613884 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 613884 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36393 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36397 # Transaction distribution -system.membus.trans_dist::ReadExReq 501696 # Transaction distribution -system.membus.trans_dist::ReadExResp 501696 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 465050 # Transaction distribution +system.membus.trans_dist::ReadResp 465050 # Transaction distribution +system.membus.trans_dist::WriteReq 33644 # Transaction distribution +system.membus.trans_dist::WriteResp 33644 # Transaction distribution +system.membus.trans_dist::Writeback 1206105 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 615969 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 615969 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36256 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36258 # Transaction distribution +system.membus.trans_dist::ReadExReq 502974 # Transaction distribution +system.membus.trans_dist::ReadExResp 502974 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4037435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4167195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337326 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337326 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4504521 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156082 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4046690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4176068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4513354 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159270496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 159440210 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14195136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14195136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173635346 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 600 # Total snoops (count) -system.membus.snoop_fanout::samples 2744389 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159620960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159790354 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173983314 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 541 # Total snoops (count) +system.membus.snoop_fanout::samples 2749696 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2744389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2749696 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2744389 # Request fanout histogram -system.membus.reqLayer0.occupancy 42480999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2749696 # Request fanout histogram +system.membus.reqLayer0.occupancy 47655000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1323000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1342002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6141947499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3662717737 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4337026701 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2514330197 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 38901629 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37911963 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2657,55 +2662,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 22911195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 22910936 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7876656 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1266229 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1231725 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45591 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45598 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2107463 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2107463 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29129582 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28533410 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 850957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 60274765 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 929555284 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1158084670 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3113192 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6291728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2097044874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 377016 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 34216462 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003376 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.058008 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 22942749 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22942559 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7872498 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1267320 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1231707 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45322 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45326 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2110986 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2110986 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29189373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28540858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 848998 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760970 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 60340199 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 931468564 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1158220350 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3098688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6299696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2099087298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 376855 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 34241641 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003374 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.057992 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 34100938 99.66% 99.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115524 0.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 34126094 99.66% 99.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115547 0.34% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 34216462 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 26470973727 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 972000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 34241641 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 13384646524 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 375000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 35634626823 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 21264279204 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11949873226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 7318478020 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 276240027 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 275201891 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 654460701 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 650856160 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |