diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt | 4357 |
1 files changed, 2179 insertions, 2178 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index a910c6b4e..d04b59f4b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.289328 # Number of seconds simulated -sim_ticks 51289327844000 # Number of ticks simulated -final_tick 51289327844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.408461 # Number of seconds simulated +sim_ticks 51408461373000 # Number of ticks simulated +final_tick 51408461373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135228 # Simulator instruction rate (inst/s) -host_op_rate 158909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7809061274 # Simulator tick rate (ticks/s) -host_mem_usage 694320 # Number of bytes of host memory used -host_seconds 6567.93 # Real time elapsed on the host -sim_insts 888164103 # Number of instructions simulated -sim_ops 1043699308 # Number of ops (including micro ops) simulated +host_inst_rate 195616 # Simulator instruction rate (inst/s) +host_op_rate 229875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11322692573 # Simulator tick rate (ticks/s) +host_mem_usage 696388 # Number of bytes of host memory used +host_seconds 4540.30 # Real time elapsed on the host +sim_insts 888155433 # Number of instructions simulated +sim_ops 1043703833 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 136512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3641344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 41468960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 150528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 137472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3597568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 42676392 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428864 # Number of bytes read from this memory -system.physmem.bytes_read::total 92364360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3641344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3597568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7238912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78441216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 142656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 137152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3491584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 41406368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 143936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 139584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3767424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 42881448 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 438400 # Number of bytes read from this memory +system.physmem.bytes_read::total 92548552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3491584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3767424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7259008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78363136 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 78461796 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2133 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 56896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 647961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2352 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2148 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56212 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 666823 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6701 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1443206 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1225644 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78383716 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2143 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 54556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 646983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58866 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 670027 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6850 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1446084 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1224424 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1228217 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 70996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 808530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 832072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1800849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 70996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1529387 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1226997 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 67918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 805439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 73284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 834132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1800259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 67918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 73284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1524324 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1529788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1529387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 70996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 808530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 832473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3330637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1443206 # Number of read requests accepted -system.physmem.writeReqs 1228217 # Number of write requests accepted -system.physmem.readBursts 1443206 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1228217 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 92312576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 52608 # Total number of bytes read from write queue -system.physmem.bytesWritten 78461696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 92364360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78461796 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 822 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::cpu1.data 400 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1524724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1524324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 67918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 805439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 73284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 834532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3324983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1446084 # Number of read requests accepted +system.physmem.writeReqs 1226997 # Number of write requests accepted +system.physmem.readBursts 1446084 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1226997 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 92503744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 45632 # Total number of bytes read from write queue +system.physmem.bytesWritten 78384064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 92548552 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78383716 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 713 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 356478 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 87850 # Per bank write bursts -system.physmem.perBankRdBursts::1 89651 # Per bank write bursts -system.physmem.perBankRdBursts::2 87083 # Per bank write bursts -system.physmem.perBankRdBursts::3 86997 # Per bank write bursts -system.physmem.perBankRdBursts::4 87338 # Per bank write bursts -system.physmem.perBankRdBursts::5 97616 # Per bank write bursts -system.physmem.perBankRdBursts::6 89147 # Per bank write bursts -system.physmem.perBankRdBursts::7 87735 # Per bank write bursts -system.physmem.perBankRdBursts::8 84823 # Per bank write bursts -system.physmem.perBankRdBursts::9 114942 # Per bank write bursts -system.physmem.perBankRdBursts::10 92351 # Per bank write bursts -system.physmem.perBankRdBursts::11 95964 # Per bank write bursts -system.physmem.perBankRdBursts::12 83458 # Per bank write bursts -system.physmem.perBankRdBursts::13 87171 # Per bank write bursts -system.physmem.perBankRdBursts::14 84360 # Per bank write bursts -system.physmem.perBankRdBursts::15 85898 # Per bank write bursts -system.physmem.perBankWrBursts::0 74977 # Per bank write bursts -system.physmem.perBankWrBursts::1 75819 # Per bank write bursts -system.physmem.perBankWrBursts::2 74752 # Per bank write bursts -system.physmem.perBankWrBursts::3 76261 # Per bank write bursts -system.physmem.perBankWrBursts::4 75660 # Per bank write bursts -system.physmem.perBankWrBursts::5 82258 # Per bank write bursts -system.physmem.perBankWrBursts::6 76272 # Per bank write bursts -system.physmem.perBankWrBursts::7 77177 # Per bank write bursts -system.physmem.perBankWrBursts::8 74263 # Per bank write bursts -system.physmem.perBankWrBursts::9 81618 # Per bank write bursts -system.physmem.perBankWrBursts::10 78101 # Per bank write bursts -system.physmem.perBankWrBursts::11 81113 # Per bank write bursts -system.physmem.perBankWrBursts::12 72977 # Per bank write bursts -system.physmem.perBankWrBursts::13 75983 # Per bank write bursts -system.physmem.perBankWrBursts::14 73541 # Per bank write bursts -system.physmem.perBankWrBursts::15 75192 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 88572 # Per bank write bursts +system.physmem.perBankRdBursts::1 91936 # Per bank write bursts +system.physmem.perBankRdBursts::2 86142 # Per bank write bursts +system.physmem.perBankRdBursts::3 85794 # Per bank write bursts +system.physmem.perBankRdBursts::4 86883 # Per bank write bursts +system.physmem.perBankRdBursts::5 96343 # Per bank write bursts +system.physmem.perBankRdBursts::6 89494 # Per bank write bursts +system.physmem.perBankRdBursts::7 87879 # Per bank write bursts +system.physmem.perBankRdBursts::8 83471 # Per bank write bursts +system.physmem.perBankRdBursts::9 112607 # Per bank write bursts +system.physmem.perBankRdBursts::10 93875 # Per bank write bursts +system.physmem.perBankRdBursts::11 93808 # Per bank write bursts +system.physmem.perBankRdBursts::12 88268 # Per bank write bursts +system.physmem.perBankRdBursts::13 91281 # Per bank write bursts +system.physmem.perBankRdBursts::14 84984 # Per bank write bursts +system.physmem.perBankRdBursts::15 84034 # Per bank write bursts +system.physmem.perBankWrBursts::0 75348 # Per bank write bursts +system.physmem.perBankWrBursts::1 77371 # Per bank write bursts +system.physmem.perBankWrBursts::2 73838 # Per bank write bursts +system.physmem.perBankWrBursts::3 75932 # Per bank write bursts +system.physmem.perBankWrBursts::4 75756 # Per bank write bursts +system.physmem.perBankWrBursts::5 80933 # Per bank write bursts +system.physmem.perBankWrBursts::6 75453 # Per bank write bursts +system.physmem.perBankWrBursts::7 77252 # Per bank write bursts +system.physmem.perBankWrBursts::8 72443 # Per bank write bursts +system.physmem.perBankWrBursts::9 79503 # Per bank write bursts +system.physmem.perBankWrBursts::10 78639 # Per bank write bursts +system.physmem.perBankWrBursts::11 80056 # Per bank write bursts +system.physmem.perBankWrBursts::12 76299 # Per bank write bursts +system.physmem.perBankWrBursts::13 79068 # Per bank write bursts +system.physmem.perBankWrBursts::14 73755 # Per bank write bursts +system.physmem.perBankWrBursts::15 73105 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 51289326709500 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 51408460130000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1443191 # Read request sizes (log2) +system.physmem.readPktSize::6 1446069 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1225644 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 662564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 216343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 159104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 787 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1224424 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 664932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 398664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 216465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 159288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 757 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -165,180 +165,185 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 753 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 30025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 43300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 73608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 74875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 75340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 78249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 77578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 77941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 84747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 79458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 91879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 98217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 76400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 80241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 72208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 56 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 565463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.007183 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.069104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.382789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 226805 40.11% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 129321 22.87% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55220 9.77% 72.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26563 4.70% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23290 4.12% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13002 2.30% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13617 2.41% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9017 1.59% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 68628 12.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 565463 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 70251 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.531565 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 230.543084 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 70246 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::11 762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 43103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 72394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 72889 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 259 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 563019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.519817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.962282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.070466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 224938 39.95% 39.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 128250 22.78% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55139 9.79% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26598 4.72% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23698 4.21% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13004 2.31% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13485 2.40% 86.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9030 1.60% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 68877 12.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 563019 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.665075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 231.098088 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 69936 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::59392-61439 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 70251 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 70251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.451196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.927151 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.708530 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 38 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 20 0.03% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 12 0.02% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 64 0.09% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 66179 94.20% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1570 2.23% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 250 0.36% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 470 0.67% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 89 0.13% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 339 0.48% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 221 0.31% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 41 0.06% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 76 0.11% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 130 0.19% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 30 0.04% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 31 0.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 448 0.64% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 32 0.05% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.04% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 123 0.18% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 30 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 70251 # Writes before turning the bus around for reads -system.physmem.totQLat 41993928125 # Total ticks spent queuing -system.physmem.totMemAccLat 69038628125 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7211920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29114.25 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 69941 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69941 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.511202 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.923338 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.360496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 37 0.05% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 29 0.04% 0.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 15 0.02% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 59 0.08% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 66137 94.56% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1542 2.20% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 224 0.32% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 273 0.39% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 66 0.09% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 90 0.13% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 208 0.30% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 42 0.06% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 345 0.49% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 68 0.10% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 33 0.05% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 68 0.10% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 312 0.45% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 25 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 113 0.16% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69941 # Writes before turning the bus around for reads +system.physmem.totQLat 42029385276 # Total ticks spent queuing +system.physmem.totMemAccLat 69130091526 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7226855000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29078.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47864.25 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47828.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.56 # Average write queue length when enqueuing -system.physmem.readRowHits 1183273 # Number of row buffer hits during reads -system.physmem.writeRowHits 919611 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.01 # Row buffer hit rate for writes -system.physmem.avgGap 19199253.25 # Average gap between requests -system.physmem.pageHitRate 78.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2152490760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1174474125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5564652600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3973380480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3349969140960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1239658923690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29686172799750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34288665862365 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.534207 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49385348498815 # Time in different power states -system.physmem_0.memoryStateTime::REF 1712663160000 # Time in different power states +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.08 # Average write queue length when enqueuing +system.physmem.readRowHits 1187061 # Number of row buffer hits during reads +system.physmem.writeRowHits 920040 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes +system.physmem.avgGap 19231912.59 # Average gap between requests +system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2145112200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1170448125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5561735400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3965001840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3357750617520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1242334329840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29755308399000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34368235643925 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.532696 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49500352455310 # Time in different power states +system.physmem_0.memoryStateTime::REF 1716641420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 191309868685 # Time in different power states +system.physmem_0.memoryStateTime::ACT 191465063440 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2122409520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1158060750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5685895800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3970866240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3349969140960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1241047287225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29684954937000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34288908597495 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.538939 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49383290725827 # Time in different power states -system.physmem_1.memoryStateTime::REF 1712663160000 # Time in different power states +system.physmem_1.actEnergy 2111311440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1152005250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5712111600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3971384640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3357750617520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1241846921700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29755735950000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34368280302150 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.533565 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49501052297586 # Time in different power states +system.physmem_1.memoryStateTime::REF 1716641420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 193373338673 # Time in different power states +system.physmem_1.memoryStateTime::ACT 190767036414 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -368,15 +373,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 128583219 # Number of BP lookups -system.cpu0.branchPred.condPredicted 87130706 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5608498 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 87627947 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 62974583 # Number of BTB hits +system.cpu0.branchPred.lookups 131317234 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89033308 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5711784 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 89061890 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 64034993 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.865866 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16935709 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187300 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.899432 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17159386 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 186222 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -407,87 +412,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 888652 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 888652 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16421 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 87809 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 549489 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 339163 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2672.191542 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 16085.449478 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 336454 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1394 0.41% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 896 0.26% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 159 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 148 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 39 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 31 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 339163 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 409656 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22857.613461 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18421.045367 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 19320.142266 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 401054 97.90% 97.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6459 1.58% 99.48% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1486 0.36% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 99 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 354 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 127 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 51 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 409656 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 372489857920 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.125711 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.685370 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 371484178920 99.73% 99.73% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 543967500 0.15% 99.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 197972000 0.05% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 122397500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 45621000 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 26772000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 27386500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 35231000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 5712500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 472000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 66500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 35000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 45500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 372489857920 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 87810 84.25% 84.25% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 16421 15.75% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 104231 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 888652 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 882165 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 882165 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16962 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90283 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 541135 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 341030 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2470.671202 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14842.312664 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 338635 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1231 0.36% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 836 0.25% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 125 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 123 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 22 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 27 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 341030 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 406695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23181.687751 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18594.894940 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 20266.186322 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 397583 97.76% 97.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6749 1.66% 99.42% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1620 0.40% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 348 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 158 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 81 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 17 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 406695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 362445074540 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.202763 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.718091 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 361444437540 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 559911000 0.15% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 188863000 0.05% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 117378000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 44663000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 25341500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 26888500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 30794500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6481000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 299000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 3500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 362445074540 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90283 84.18% 84.18% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16962 15.82% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107245 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 882165 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 888652 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104231 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 882165 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107245 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104231 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 992883 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 989410 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 102519767 # DTB read hits -system.cpu0.dtb.read_misses 608916 # DTB read misses -system.cpu0.dtb.write_hits 79730858 # DTB write hits -system.cpu0.dtb.write_misses 279736 # DTB write misses -system.cpu0.dtb.flush_tlb 1105 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 104764153 # DTB read hits +system.cpu0.dtb.read_misses 607812 # DTB read misses +system.cpu0.dtb.write_hits 82241693 # DTB write hits +system.cpu0.dtb.write_misses 274353 # DTB write misses +system.cpu0.dtb.flush_tlb 1109 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21393 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 535 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55242 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 209 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9412 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 21084 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 563 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 55854 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 162 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9058 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56039 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 103128683 # DTB read accesses -system.cpu0.dtb.write_accesses 80010594 # DTB write accesses +system.cpu0.dtb.perms_faults 56832 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 105371965 # DTB read accesses +system.cpu0.dtb.write_accesses 82516046 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 182250625 # DTB hits -system.cpu0.dtb.misses 888652 # DTB misses -system.cpu0.dtb.accesses 183139277 # DTB accesses +system.cpu0.dtb.hits 187005846 # DTB hits +system.cpu0.dtb.misses 882165 # DTB misses +system.cpu0.dtb.accesses 187888011 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -517,824 +524,838 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 102152 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102152 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3042 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 68901 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14128 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88024 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1905.912024 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 12139.697138 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 87548 99.46% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 189 0.21% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 243 0.28% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 22 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 18 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88024 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 86071 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 29335.746070 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24303.412638 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 23702.116672 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 84000 97.59% 97.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 669 0.78% 98.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1177 1.37% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.07% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 107 0.12% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 38 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 86071 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 290883014796 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.826730 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -240403892944 -82.65% -82.65% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 531218150240 182.62% 99.98% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 61167000 0.02% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 6375000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 1069000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 146500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 290883014796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 68901 95.77% 95.77% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3042 4.23% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 71943 # Table walker page sizes translated +system.cpu0.itb.walker.walks 108290 # Table walker walks requested +system.cpu0.itb.walker.walksLong 108290 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3192 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 74908 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14795 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 93495 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1790.395208 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11668.511629 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 92494 98.93% 98.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 513 0.55% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 98 0.10% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 116 0.12% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 207 0.22% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 24 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 10 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 93495 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 92895 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 29889.315894 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24974.829894 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 23485.865012 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 49009 52.76% 52.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 41574 44.75% 97.51% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 612 0.66% 98.17% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 79 0.09% 98.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 1038 1.12% 99.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 333 0.36% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 46 0.05% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 56 0.06% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 94 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 13 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 9 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 92895 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 289428770008 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.837978 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -242453514464 -83.77% -83.77% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 531809766472 183.74% 99.97% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 64887000 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6499500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 871000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 248000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 12500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 289428770008 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 74908 95.91% 95.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 3192 4.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 78100 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102152 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102152 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 108290 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 108290 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71943 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71943 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 174095 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 92233828 # ITB inst hits -system.cpu0.itb.inst_misses 102152 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 78100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 78100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 186390 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 94461785 # ITB inst hits +system.cpu0.itb.inst_misses 108290 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1105 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1109 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21393 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 535 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40730 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21084 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 563 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41856 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 204444 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 202434 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 92335980 # ITB inst accesses -system.cpu0.itb.hits 92233828 # DTB hits -system.cpu0.itb.misses 102152 # DTB misses -system.cpu0.itb.accesses 92335980 # DTB accesses -system.cpu0.numCycles 692838439 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94570075 # ITB inst accesses +system.cpu0.itb.hits 94461785 # DTB hits +system.cpu0.itb.misses 108290 # DTB misses +system.cpu0.itb.accesses 94570075 # DTB accesses +system.cpu0.numCycles 692991159 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 240908960 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 572231445 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 128583219 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 79910292 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 408388774 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 12834591 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2570044 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 24306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 5220 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5457264 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 161454 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 3138 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 92012846 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3478486 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 41135 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 663936181 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.010011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.263466 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 244811791 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 585398201 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 131317234 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81194379 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 404384012 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13047908 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2817091 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21621 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 5789 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5286158 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 175205 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 3136 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94240840 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3527611 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 42921 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 664028482 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.032942 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.287290 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 522394328 78.68% 78.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 17725810 2.67% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 17688411 2.66% 84.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13071873 1.97% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28203827 4.25% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8736087 1.32% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9493633 1.43% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8170343 1.23% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 38451869 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 519576745 78.25% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18052759 2.72% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18229592 2.75% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13406945 2.02% 85.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28061689 4.23% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8964232 1.35% 91.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9738895 1.47% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8312010 1.25% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39685615 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 663936181 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.185589 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.825923 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 195480668 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 347525883 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 102363007 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13531611 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5032846 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19144374 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1404061 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 624972262 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4324699 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5032846 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 202972273 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 31908208 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 264942356 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 108280793 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 50797146 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 610471334 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 95561 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2181622 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1833281 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 31100121 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3748 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 584763041 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 944825531 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 722111361 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 774403 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 494202829 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 90560207 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15441984 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13500490 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 76181815 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 97914623 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 83796282 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13494788 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14509188 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 578969956 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15549087 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 581387385 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 830768 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 76282364 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 48796155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 362907 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 663936181 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.875668 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.614381 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 664028482 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.189493 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.844741 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 199609312 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 340272761 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105735491 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13276963 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5131471 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19616175 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1412684 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 640319872 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4351333 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5131471 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 207083748 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 31652470 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 258696093 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111398501 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 50063478 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 625547022 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 86953 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2120320 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1651060 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 31054223 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 4011 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 597792979 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 961356441 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 739385367 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 793267 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 505102127 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 92690852 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14931756 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12960965 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 74096600 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 100382456 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86370742 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13395217 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14366752 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 594049171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14966536 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 595443977 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 833379 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 77816816 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 49417916 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 356669 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 664028482 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.896715 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.636729 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 434128190 65.39% 65.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 98370789 14.82% 80.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 42377650 6.38% 86.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30067622 4.53% 91.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22403128 3.37% 94.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 15594972 2.35% 96.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10621983 1.60% 98.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6235616 0.94% 99.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4136231 0.62% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 431629347 65.00% 65.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 97195183 14.64% 79.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43390380 6.53% 86.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 30835149 4.64% 90.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23006785 3.46% 94.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16163925 2.43% 96.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10905989 1.64% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6533904 0.98% 99.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4367820 0.66% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 663936181 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 664028482 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2959786 25.50% 25.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 23278 0.20% 25.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2380 0.02% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4810604 41.45% 67.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3809012 32.82% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3037620 25.70% 25.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 25191 0.21% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2899 0.02% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4781762 40.45% 66.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3973331 33.61% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 394568235 67.87% 67.87% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1380833 0.24% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 65255 0.01% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 66 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 59226 0.01% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 104545250 17.98% 86.11% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 80768506 13.89% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 44 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 403794947 67.81% 67.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1402722 0.24% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 64715 0.01% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 26 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 70887 0.01% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106816149 17.94% 86.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83294486 13.99% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 581387385 # Type of FU issued -system.cpu0.iq.rate 0.839138 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11605060 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1838113951 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 670976650 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 559986003 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1032828 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 510697 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 459801 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 592439966 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 552468 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4598569 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 595443977 # Type of FU issued +system.cpu0.iq.rate 0.859237 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11820804 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019852 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1866487578 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 687019560 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 573922610 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1083041 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 536746 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 483014 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 606686496 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 578241 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4705214 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 15443537 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 19687 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 696908 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8570730 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 15648573 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20037 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 735656 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8693789 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3841968 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8263079 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3938518 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7949396 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5032846 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 16244018 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 13852341 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 594652790 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1703484 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 97914623 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 83796282 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13208370 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 224559 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13543277 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 696908 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2523457 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2209016 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4732473 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 575002762 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 102511874 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5508716 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5131471 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 16124670 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 13736061 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 609148290 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1755735 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 100382456 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86370742 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12679523 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 224965 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 13426906 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 735656 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2579656 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2261003 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4840659 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 588863732 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 104752148 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5709737 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 133747 # number of nop insts executed -system.cpu0.iew.exec_refs 182243986 # number of memory reference insts executed -system.cpu0.iew.exec_branches 106498541 # Number of branches executed -system.cpu0.iew.exec_stores 79732112 # Number of stores executed -system.cpu0.iew.exec_rate 0.829923 # Inst execution rate -system.cpu0.iew.wb_sent 561628821 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 560445804 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 276455484 # num instructions producing a value -system.cpu0.iew.wb_consumers 480133798 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.808913 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575788 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 76323092 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15186180 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4223774 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 650882635 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.796206 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.791535 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 132583 # number of nop insts executed +system.cpu0.iew.exec_refs 186992207 # number of memory reference insts executed +system.cpu0.iew.exec_branches 108909859 # Number of branches executed +system.cpu0.iew.exec_stores 82240059 # Number of stores executed +system.cpu0.iew.exec_rate 0.849742 # Inst execution rate +system.cpu0.iew.wb_sent 575604648 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 574405624 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 283543762 # num instructions producing a value +system.cpu0.iew.wb_consumers 491943015 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.828879 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.576375 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 77856968 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14609867 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4319026 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 650724527 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.816319 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.818422 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 459027992 70.52% 70.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 95977430 14.75% 85.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32265262 4.96% 90.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 14738583 2.26% 92.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10675615 1.64% 94.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6384145 0.98% 95.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5905756 0.91% 96.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3807566 0.58% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22100286 3.40% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 457095790 70.24% 70.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 94826206 14.57% 84.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 32956684 5.06% 89.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15335469 2.36% 92.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10858481 1.67% 93.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6641395 1.02% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6158141 0.95% 95.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3955723 0.61% 96.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22896638 3.52% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 650882635 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 440797694 # Number of instructions committed -system.cpu0.commit.committedOps 518236674 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 650724527 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 451838462 # Number of instructions committed +system.cpu0.commit.committedOps 531198891 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 157696637 # Number of memory references committed -system.cpu0.commit.loads 82471085 # Number of loads committed -system.cpu0.commit.membars 3674667 # Number of memory barriers committed -system.cpu0.commit.branches 98481561 # Number of branches committed -system.cpu0.commit.fp_insts 441323 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 475654398 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13113007 # Number of function calls committed. +system.cpu0.commit.refs 162410836 # Number of memory references committed +system.cpu0.commit.loads 84733883 # Number of loads committed +system.cpu0.commit.membars 3641724 # Number of memory barriers committed +system.cpu0.commit.branches 100706106 # Number of branches committed +system.cpu0.commit.fp_insts 463962 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 487973755 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13314640 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 359364507 69.34% 69.34% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1076711 0.21% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48368 0.01% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 50451 0.01% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 82471085 15.91% 85.48% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 75225552 14.52% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 367585865 69.20% 69.20% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1092900 0.21% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48363 0.01% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 60927 0.01% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84733883 15.95% 85.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77676953 14.62% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 518236674 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22100286 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1219379931 # The number of ROB reads -system.cpu0.rob.rob_writes 1202193257 # The number of ROB writes -system.cpu0.timesIdled 4085117 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28902258 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 52406782764 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 440797694 # Number of Instructions Simulated -system.cpu0.committedOps 518236674 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.571783 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.571783 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.636220 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.636220 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 678374188 # number of integer regfile reads -system.cpu0.int_regfile_writes 399817042 # number of integer regfile writes -system.cpu0.fp_regfile_reads 838109 # number of floating regfile reads -system.cpu0.fp_regfile_writes 474946 # number of floating regfile writes -system.cpu0.cc_regfile_reads 123617139 # number of cc regfile reads -system.cpu0.cc_regfile_writes 124729221 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1203854145 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15290594 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10436084 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.972968 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 299959666 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10436596 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.741140 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 531198891 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22896638 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1233051269 # The number of ROB reads +system.cpu0.rob.rob_writes 1231435060 # The number of ROB writes +system.cpu0.timesIdled 4157054 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28962677 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 49016383217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 451838462 # Number of Instructions Simulated +system.cpu0.committedOps 531198891 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.533714 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.533714 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.652012 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.652012 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 694247819 # number of integer regfile reads +system.cpu0.int_regfile_writes 410288637 # number of integer regfile writes +system.cpu0.fp_regfile_reads 858111 # number of floating regfile reads +system.cpu0.fp_regfile_writes 534016 # number of floating regfile writes +system.cpu0.cc_regfile_reads 125553876 # number of cc regfile reads +system.cpu0.cc_regfile_writes 126720582 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1210004868 # number of misc regfile reads +system.cpu0.misc_regfile_writes 14749855 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10444529 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.973029 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 299923189 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10445041 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.714410 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 279.244386 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 232.728582 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.545399 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.454548 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.726470 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.246559 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.608841 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391107 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1323106613 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1323106613 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77963580 # 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number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 142945251 # number of overall hits +system.cpu0.dcache.overall_hits::total 292056324 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6171666 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 6278457 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 12450123 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6360667 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 6298405 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 12659072 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 645106 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 634374 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1279480 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 599720 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 638706 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1238426 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 340434 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 305579 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 646013 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 12805598 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 12288650 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 25094248 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 13479948 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 12892834 # 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average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14134.402297 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13808.317745 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 33571.428571 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 41700 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 36958.333333 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30762.590162 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31092.612904 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30924.202256 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29223.655986 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29635.550847 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 29425.018590 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 88195384 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 113546 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3493866 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 1091 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25.242921 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 104.075160 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.077629 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.080971 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.079268 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.081198 # 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number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29565 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 37817 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67382 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47767699000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 50570666500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98338365500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 51048745765 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 47967542154 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 99016287919 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12938219500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11970277000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24908496500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 42479134250 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 47413708556 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 89892842806 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1851393500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1735514500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3586908000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 224500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 187500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 412000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 98816444765 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 98538208654 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 197354653419 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111754664265 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110508485654 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 222263149919 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2756867500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3474155500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6231023000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2706893000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3501005491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6207898491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5463760500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6975160991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12438921491 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032930 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014385 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014880 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014626 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.744068 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749436 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.746723 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.771883 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.803397 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787821 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062538 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057248 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059901 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024948 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023988 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024463 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029005 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027555 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028273 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17179.075935 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17795.798310 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17487.447831 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46221.714950 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46571.740290 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46391.323007 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20547.718254 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18836.423170 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19738.160098 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 70381.509685 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 75807.317399 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73126.057617 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13893.833563 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15026.922985 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14464.183525 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 32571.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 40700 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35958.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25355.736594 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25542.267355 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25448.211063 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24660.136465 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24645.099411 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24652.729234 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180078.416682 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189481.739426 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185009.590831 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187746.374838 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181510.311517 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184228.780597 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183746.580473 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185349.718856 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184619.081411 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023996 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025001 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024489 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027766 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028858 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028301 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17080.614946 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17908.550556 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17496.587984 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47385.337906 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45276.574241 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46339.777521 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20468.077112 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19212.786721 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19844.972410 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71240.963466 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 74663.612573 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73006.154288 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14301.002634 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14728.719703 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.806079 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 32071.428571 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 46875 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 37454.545455 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25508.166873 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25375.112123 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25441.559328 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24801.130810 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24523.114346 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24662.118444 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181695.610624 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187690.734738 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184990.143396 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188083.171206 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181333.479619 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184216.104068 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184805.022831 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184445.117037 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184603.031833 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 15974128 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.921242 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 168806839 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15974640 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.567176 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 16002915 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.921323 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 168727471 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16003427 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.543209 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 23708267500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 281.088545 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 230.832697 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.549001 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.450845 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 280.765706 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 231.155617 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.548371 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.451476 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 201986364 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 201986364 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 83405429 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 85401410 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 168806839 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 83405429 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 85401410 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 168806839 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 83405429 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 85401410 # number of overall hits -system.cpu0.icache.overall_hits::total 168806839 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8594272 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 8610485 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 17204757 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8594272 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 8610485 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 17204757 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8594272 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 8610485 # number of overall misses -system.cpu0.icache.overall_misses::total 17204757 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115674670362 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116624708317 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 232299378679 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 115674670362 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 116624708317 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 232299378679 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 115674670362 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 116624708317 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 232299378679 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 91999701 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 94011895 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 186011596 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 91999701 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 94011895 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 186011596 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 91999701 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 94011895 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 186011596 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.093416 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091589 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092493 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.093416 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091589 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092493 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.093416 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091589 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092493 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13459.507724 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13544.499330 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13502.043573 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13459.507724 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13544.499330 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13502.043573 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13459.507724 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13544.499330 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13502.043573 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 130388 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 201964404 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 201964404 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 85532749 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 83194722 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 168727471 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 85532749 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 83194722 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 168727471 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 85532749 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 83194722 # number of overall hits +system.cpu0.icache.overall_hits::total 168727471 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8694942 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 8538418 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 17233360 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8694942 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 8538418 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 17233360 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8694942 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 8538418 # number of overall misses +system.cpu0.icache.overall_misses::total 17233360 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116564920862 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116224713334 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 232789634196 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 116564920862 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 116224713334 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 232789634196 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 116564920862 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 116224713334 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 232789634196 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 94227691 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 91733140 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 185960831 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 94227691 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 91733140 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 185960831 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 94227691 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 91733140 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 185960831 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.093079 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092672 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092276 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.093079 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092672 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092276 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.093079 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.092672 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13406.060772 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13611.972772 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13508.081662 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13406.060772 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13611.972772 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13508.081662 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13406.060772 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13611.972772 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13508.081662 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 124982 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 8896 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 8393 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.656924 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.891219 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 15974128 # number of writebacks -system.cpu0.icache.writebacks::total 15974128 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 611973 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 618016 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1229989 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 611973 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 618016 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1229989 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 611973 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 618016 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1229989 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 7982299 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7992469 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 15974768 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 7982299 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 7992469 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 15974768 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 7982299 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 7992469 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 15974768 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 16002915 # number of writebacks +system.cpu0.icache.writebacks::total 16002915 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 618920 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 610867 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1229787 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 618920 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 610867 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1229787 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 618920 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 610867 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1229787 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8076022 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7927551 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16003573 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8076022 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 7927551 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16003573 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8076022 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 7927551 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16003573 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 20646 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 20646 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 102168974407 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 102903128872 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 205072103279 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 102168974407 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 102903128872 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 205072103279 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 102168974407 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 102903128872 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 205072103279 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 102996587403 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 102473648883 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 205470236286 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 102996587403 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 102473648883 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 205470236286 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 102996587403 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 102473648883 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 205470236286 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960890000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636383000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960890000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636383000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086764 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085016 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085880 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086764 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085016 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085880 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086764 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085016 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085880 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12799.442167 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12875.011323 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12837.250799 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12799.442167 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12875.011323 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12837.250799 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12799.442167 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12875.011323 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12837.250799 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12839.022654 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12839.022654 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12839.022654 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969 # average ReadReq mshr uncacheable latency @@ -1342,15 +1363,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 130968102 # Number of BP lookups -system.cpu1.branchPred.condPredicted 88970124 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5750252 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 89023495 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 63858591 # Number of BTB hits +system.cpu1.branchPred.lookups 128216560 # Number of BP lookups +system.cpu1.branchPred.condPredicted 87052179 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5647036 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 87531901 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 62765206 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.732289 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16978119 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 186369 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.705521 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16746465 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 188086 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1380,94 +1401,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 886500 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 886500 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16614 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90854 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 546971 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 339529 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2635.682077 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 15582.194898 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 331369 97.60% 97.60% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 5485 1.62% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 837 0.25% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 574 0.17% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 696 0.20% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 183 0.05% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 92 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 51 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 111 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 44 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 21 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 9 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::425984-458751 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-491519 24 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::491520-524287 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 339529 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 415382 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23662.319263 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19025.805885 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20147.084285 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 405553 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7307 1.76% 99.39% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1720 0.41% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 155 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 425 0.10% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 150 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 57 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 415382 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 346321236644 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.073903 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.674380 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 345291497644 99.70% 99.70% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 564895000 0.16% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 201129000 0.06% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 122101500 0.04% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 48136500 0.01% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 26097000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 27118000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 32649000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 7117000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 414500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 28000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 21500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 30000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 346321236644 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 90854 84.54% 84.54% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 16614 15.46% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 107468 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 886500 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 886664 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 886664 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16465 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89324 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 548056 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 338608 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2680.249728 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15884.122714 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 335881 99.19% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1416 0.42% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 912 0.27% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 152 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 149 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 41 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 27 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 24 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 338608 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 414311 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23113.131199 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18566.304673 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 20214.309005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 405108 97.78% 97.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6775 1.64% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1700 0.41% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 115 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 357 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 138 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 86 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 23 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 414311 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 341299530060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.159336 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.721695 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 340284229060 99.70% 99.70% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 551479000 0.16% 99.86% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 203508500 0.06% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 121654000 0.04% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 47328500 0.01% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 25233500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 25945000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 34128500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 5458500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 539500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 14000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 341299530060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 89325 84.44% 84.44% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 16465 15.56% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 105790 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 886664 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 886500 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 107468 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 886664 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105790 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 107468 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 993968 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105790 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 992454 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 104053210 # DTB read hits -system.cpu1.dtb.read_misses 608792 # DTB read misses -system.cpu1.dtb.write_hits 81022913 # DTB write hits -system.cpu1.dtb.write_misses 277708 # DTB write misses -system.cpu1.dtb.flush_tlb 1101 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 101829672 # DTB read hits +system.cpu1.dtb.read_misses 610637 # DTB read misses +system.cpu1.dtb.write_hits 78493819 # DTB write hits +system.cpu1.dtb.write_misses 276027 # DTB write misses +system.cpu1.dtb.flush_tlb 1099 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21005 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55258 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8900 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 494 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 53264 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 214 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9173 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55921 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 104662002 # DTB read accesses -system.cpu1.dtb.write_accesses 81300621 # DTB write accesses +system.cpu1.dtb.perms_faults 54344 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 102440309 # DTB read accesses +system.cpu1.dtb.write_accesses 78769846 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 185076123 # DTB hits -system.cpu1.dtb.misses 886500 # DTB misses -system.cpu1.dtb.accesses 185962623 # DTB accesses +system.cpu1.dtb.hits 180323491 # DTB hits +system.cpu1.dtb.misses 886664 # DTB misses +system.cpu1.dtb.accesses 181210155 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1497,391 +1514,379 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 108383 # Table walker walks requested -system.cpu1.itb.walker.walksLong 108383 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3055 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 74203 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 15086 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 93297 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1942.152481 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 12371.477981 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 92174 98.80% 98.80% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 584 0.63% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 102 0.11% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 130 0.14% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 211 0.23% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 45 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 16 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 93297 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 92344 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 29998.852118 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25024.825336 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 23447.205445 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47315 51.24% 51.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 42742 46.29% 97.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 660 0.71% 98.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 85 0.09% 98.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 956 1.04% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 338 0.37% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 49 0.05% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 41 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 83 0.09% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 32 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 14 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 20 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 92344 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 303371540184 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 1.809423 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -245466797852 -80.91% -80.91% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 548762837036 180.89% 99.98% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 65136000 0.02% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 8157000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 1504000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 507000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 155000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 42000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 303371540184 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 74203 96.05% 96.05% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3055 3.95% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 77258 # Table walker page sizes translated +system.cpu1.itb.walker.walks 102782 # Table walker walks requested +system.cpu1.itb.walker.walksLong 102782 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2883 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68745 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14394 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 88388 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1935.822736 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 12537.694172 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 87864 99.41% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 223 0.25% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 254 0.29% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 12 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 88388 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 29627.804515 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24484.599023 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24553.065811 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 83801 97.42% 97.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 633 0.74% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1356 1.58% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.07% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 124 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 13 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 285462324712 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 1.863931 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -246539938456 -86.37% -86.37% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 531932332168 186.34% 99.98% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 61889000 0.02% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 6735500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 960500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 221000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 125000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 285462324712 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 68745 95.98% 95.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2883 4.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71628 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 108383 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 108383 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 102782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 102782 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 77258 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 77258 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 185641 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 94245746 # ITB inst hits -system.cpu1.itb.inst_misses 108383 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71628 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71628 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174410 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 91967963 # ITB inst hits +system.cpu1.itb.inst_misses 102782 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1101 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1099 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21005 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 41537 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 494 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 39701 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202136 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 205263 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 94354129 # ITB inst accesses -system.cpu1.itb.hits 94245746 # DTB hits -system.cpu1.itb.misses 108383 # DTB misses -system.cpu1.itb.accesses 94354129 # DTB accesses -system.cpu1.numCycles 688244310 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 92070745 # ITB inst accesses +system.cpu1.itb.hits 91967963 # DTB hits +system.cpu1.itb.misses 102782 # DTB misses +system.cpu1.itb.accesses 92070745 # DTB accesses +system.cpu1.numCycles 688789566 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 242823548 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 582789507 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 130968102 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 80836710 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 401946219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13110617 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2820679 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23345 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 5607 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5329468 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 177594 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 4339 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 94019463 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3524085 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 43192 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 659685833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.033819 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.287421 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 239433402 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 569353182 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 128216560 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 79511671 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 405943168 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 12894098 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2616962 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 5725 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5490519 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 162267 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 4008 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 91740705 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3476633 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 41341 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 660128083 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.009568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.262441 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 515917584 78.21% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18016869 2.73% 80.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18269669 2.77% 83.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13353344 2.02% 85.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 27714525 4.20% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8994456 1.36% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9703502 1.47% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8398741 1.27% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39317143 5.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 519338149 78.67% 78.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 17657421 2.67% 81.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 17720975 2.68% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13023211 1.97% 86.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 27851950 4.22% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 8753673 1.33% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9450814 1.43% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8261049 1.25% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 38070841 5.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 659685833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.190293 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.846777 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 197914756 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 338110902 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105437320 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13046087 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5174542 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19519920 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1400536 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 636170059 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4304353 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5174542 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 205322358 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31076264 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 254971917 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 110916625 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 52221607 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 621253009 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 123804 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2084188 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1933644 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 33372173 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3863 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 594055023 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 953160447 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 734477449 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 779699 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 499665654 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 94389369 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14450095 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12489155 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 72603024 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 100339444 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 85180632 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13386925 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14275413 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 590006738 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14504084 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 589818158 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 830847 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 79048188 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 50610611 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352346 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 659685833 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.894089 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.635498 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 660128083 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.186148 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.826600 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 194262443 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 345472686 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 102025852 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13293227 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5071579 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19043746 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1394530 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 620472933 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4297557 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5071579 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 201685746 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31240093 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 261429717 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 107754222 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 52944105 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 605820743 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 130951 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2142931 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 2140614 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 33385135 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3753 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 580698698 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 936110112 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 716711881 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 767618 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 488837378 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 91861315 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14967870 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13038182 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 74719709 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 97839319 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 82555667 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13435403 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14269542 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 574617477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15094560 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 575613551 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 822312 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 77207090 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 49700091 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 361677 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 660128083 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.871973 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.612023 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 430142670 65.20% 65.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 95209085 14.43% 79.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43103455 6.53% 86.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 30774369 4.67% 90.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 22787863 3.45% 94.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16081687 2.44% 96.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10870686 1.65% 98.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6433091 0.98% 99.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4282927 0.65% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 433148093 65.62% 65.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 96441838 14.61% 80.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 42095455 6.38% 86.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 30017553 4.55% 91.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 22180461 3.36% 94.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 15486932 2.35% 96.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10578992 1.60% 98.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6132384 0.93% 99.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4046375 0.61% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 659685833 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 660128083 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2991282 25.77% 25.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 24682 0.21% 25.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 3126 0.03% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4685148 40.36% 66.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3902762 33.62% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2899692 25.45% 25.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 23212 0.20% 25.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2493 0.02% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4727772 41.50% 67.18% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3739545 32.82% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 399989408 67.82% 67.82% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1473233 0.25% 68.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67059 0.01% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 153 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 4 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 70210 0.01% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 106137364 17.99% 86.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82080680 13.92% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 87 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 390631647 67.86% 67.86% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1449252 0.25% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 67728 0.01% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 81 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 18 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 4 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 58665 0.01% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 103885376 18.05% 86.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 79520645 13.81% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 589818158 # Type of FU issued -system.cpu1.iq.rate 0.856990 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11607000 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019679 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1850695958 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 683728270 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 568714201 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1064038 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 529691 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 473676 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 600857355 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 567803 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4685307 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 575613551 # Type of FU issued +system.cpu1.iq.rate 0.835689 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11392715 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019792 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1822546817 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 667071123 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 554642407 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1023395 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 508279 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 454369 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 586459289 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 546890 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4569014 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 15994035 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 20483 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 710355 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8709901 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 15724428 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 20010 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 670978 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8558712 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3868542 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 7450104 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3761249 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7804669 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5174542 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 16661499 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12204142 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 604643269 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1738208 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 100339444 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 85180632 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12202242 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 236266 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 11879435 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 710355 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2616920 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2284300 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4901220 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 583187166 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 104040866 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5756605 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5071579 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 16680640 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12329901 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 589846063 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1702837 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 97839319 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 82555667 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12741950 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 233925 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 12007104 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 670978 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2558274 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2229598 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4787872 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 569204299 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 101821264 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5535672 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 132447 # number of nop insts executed -system.cpu1.iew.exec_refs 185065127 # number of memory reference insts executed -system.cpu1.iew.exec_branches 108200674 # Number of branches executed -system.cpu1.iew.exec_stores 81024261 # Number of stores executed -system.cpu1.iew.exec_rate 0.847355 # Inst execution rate -system.cpu1.iew.wb_sent 570418733 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 569187877 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 281309683 # num instructions producing a value -system.cpu1.iew.wb_consumers 488305636 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.827014 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.576093 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 79095788 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14151738 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4369211 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 646199938 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.813158 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.817106 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 134026 # number of nop insts executed +system.cpu1.iew.exec_refs 180319145 # number of memory reference insts executed +system.cpu1.iew.exec_branches 105773243 # Number of branches executed +system.cpu1.iew.exec_stores 78497881 # Number of stores executed +system.cpu1.iew.exec_rate 0.826383 # Inst execution rate +system.cpu1.iew.wb_sent 556304876 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 555096776 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 274163162 # num instructions producing a value +system.cpu1.iew.wb_consumers 476408431 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.805902 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575479 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 77255744 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14732883 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4271292 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 646929445 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.792211 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.788945 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 455330275 70.46% 70.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 92773758 14.36% 84.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 32833911 5.08% 89.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15287498 2.37% 92.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10781023 1.67% 93.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6487132 1.00% 94.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6078607 0.94% 95.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3894706 0.60% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22733028 3.52% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 457763793 70.76% 70.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 93973346 14.53% 85.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 32152826 4.97% 90.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 14713797 2.27% 92.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10604817 1.64% 94.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6244010 0.97% 95.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5818154 0.90% 96.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3733305 0.58% 96.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 21925397 3.39% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 646199938 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 447366409 # Number of instructions committed -system.cpu1.commit.committedOps 525462634 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 646929445 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 436316971 # Number of instructions committed +system.cpu1.commit.committedOps 512504942 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 160816140 # Number of memory references committed -system.cpu1.commit.loads 84345409 # Number of loads committed -system.cpu1.commit.membars 3627931 # Number of memory barriers committed -system.cpu1.commit.branches 99847042 # Number of branches committed -system.cpu1.commit.fp_insts 454333 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 482598910 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13134163 # Number of function calls committed. +system.cpu1.commit.refs 156111845 # Number of memory references committed +system.cpu1.commit.loads 82114890 # Number of loads committed +system.cpu1.commit.membars 3660763 # Number of memory barriers committed +system.cpu1.commit.branches 97634182 # Number of branches committed +system.cpu1.commit.fp_insts 435169 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 470255893 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12926033 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 363400914 69.16% 69.16% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1135062 0.22% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50467 0.01% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 60009 0.01% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84345409 16.05% 85.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76470731 14.55% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 355174724 69.30% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1118155 0.22% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50641 0.01% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 49535 0.01% 69.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82114890 16.02% 85.56% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 73996955 14.44% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 525462634 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22733028 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1224126418 # The number of ROB reads -system.cpu1.rob.rob_writes 1222625233 # The number of ROB writes -system.cpu1.timesIdled 4106530 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 28558477 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 48790405544 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 447366409 # Number of Instructions Simulated -system.cpu1.committedOps 525462634 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.538435 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.538435 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.650011 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.650011 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 687757037 # number of integer regfile reads -system.cpu1.int_regfile_writes 406838676 # number of integer regfile writes -system.cpu1.fp_regfile_reads 842941 # number of floating regfile reads -system.cpu1.fp_regfile_writes 528902 # number of floating regfile writes -system.cpu1.cc_regfile_reads 124631004 # number of cc regfile reads -system.cpu1.cc_regfile_writes 125817612 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1199807572 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14264439 # number of misc regfile writes +system.cpu1.commit.op_class_0::total 512504942 # Class of committed instruction +system.cpu1.commit.bw_lim_events 21925397 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1210740079 # The number of ROB reads +system.cpu1.rob.rob_writes 1192741700 # The number of ROB writes +system.cpu1.timesIdled 4053845 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 28661483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 52418384154 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 436316971 # Number of Instructions Simulated +system.cpu1.committedOps 512504942 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.578645 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.578645 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.633455 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.633455 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 671693836 # number of integer regfile reads +system.cpu1.int_regfile_writes 396256302 # number of integer regfile writes +system.cpu1.fp_regfile_reads 829382 # number of floating regfile reads +system.cpu1.fp_regfile_writes 475398 # number of floating regfile writes +system.cpu1.cc_regfile_reads 122695419 # number of cc regfile reads +system.cpu1.cc_regfile_writes 123792123 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1193620211 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14812328 # number of misc regfile writes system.iobus.trans_dist::ReadReq 40298 # Transaction distribution system.iobus.trans_dist::ReadResp 40298 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1924,7 +1929,7 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47828500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 47816000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1946,11 +1951,11 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25445500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25477500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 40141500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 40153500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565650665 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567153724 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -1959,16 +1964,16 @@ system.iobus.respLayer3.utilization 0.0 # La system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.418706 # Cycle average of tags in use +system.iocache.tags.tagsinuse 10.431703 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13100979262000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.907316 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.511389 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.369207 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.281962 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651169 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13100979259000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.538083 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.893621 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221130 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430851 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651981 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1988,18 +1993,18 @@ system.iocache.overall_misses::realview.ethernet 40 system.iocache.overall_misses::realview.ide 8813 # number of overall misses system.iocache.overall_misses::total 8853 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1684461016 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1689547016 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1703214286 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1708300286 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13867464649 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13867464649 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13410969438 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13410969438 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1684461016 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1689898016 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1703214286 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1708651286 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1684461016 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1689898016 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1703214286 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1708651286 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) @@ -2027,23 +2032,23 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191133.667990 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190909.267345 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 193261.577896 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 193028.280904 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130010.731353 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130010.731353 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125730.981756 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125730.981756 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191133.667990 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190884.221846 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 193261.577896 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 193002.517339 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191133.667990 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190884.221846 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36071 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 193261.577896 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 193002.517339 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 35415 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3608 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3508 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.997506 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.095496 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2063,18 +2068,18 @@ system.iocache.overall_mshr_misses::realview.ethernet 40 system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1243811016 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1247047016 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1262564286 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1265800286 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8534264649 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8534264649 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072705642 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8072705642 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1243811016 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1247248016 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1262564286 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1266001286 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1243811016 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1247248016 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1262564286 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1266001286 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2089,311 +2094,311 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141133.667990 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140909.267345 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143261.577896 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 143028.280904 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80010.731353 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80010.731353 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75683.507481 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75683.507481 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141133.667990 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140884.221846 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 143261.577896 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 143002.517339 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141133.667990 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140884.221846 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 143261.577896 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 143002.517339 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1326476 # number of replacements -system.l2c.tags.tagsinuse 65296.669801 # Cycle average of tags in use -system.l2c.tags.total_refs 49454623 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1388892 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 35.607249 # Average number of references to valid blocks. +system.l2c.tags.replacements 1326374 # number of replacements +system.l2c.tags.tagsinuse 65265.362084 # Cycle average of tags in use +system.l2c.tags.total_refs 49524083 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1389631 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 35.638298 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 22398666000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35546.103483 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 178.339981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 269.475913 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3715.302647 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10815.708045 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 174.213795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 257.428239 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3587.286900 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10752.810798 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.542390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002721 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056691 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.165035 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002658 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003928 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.164075 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996348 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 319 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62097 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 35423.869586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 183.395025 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 263.757590 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3339.523943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11653.727077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 182.196722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 269.878356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3963.200555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9985.813228 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.540525 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002798 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004025 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.177822 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002780 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004118 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.060474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.152371 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995870 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 308 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62949 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 533 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2767 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53561 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004868 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.947525 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 439122291 # Number of tag accesses -system.l2c.tags.data_accesses 439122291 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 514243 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 181851 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 527161 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 198547 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1421802 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8003169 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8003169 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15970717 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15970717 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5001 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4885 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9886 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1023::4 307 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2748 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5097 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54406 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.960526 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 439713882 # Number of tag accesses +system.l2c.tags.data_accesses 439713882 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 520227 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 197797 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 519049 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 183181 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1420254 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8006090 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8006090 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 15999481 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 15999481 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 4949 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4988 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9937 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 822179 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 770643 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1592822 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 7938357 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 7943580 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15881937 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3437833 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3369062 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6806895 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 367734 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 352789 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 720523 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 514243 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 181851 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7938357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4260012 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 527161 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 198547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7943580 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4139705 # number of demand (read+write) hits -system.l2c.demand_hits::total 25703456 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 514243 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 181851 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7938357 # number of overall hits -system.l2c.overall_hits::cpu0.data 4260012 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 527161 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 198547 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7943580 # number of overall hits -system.l2c.overall_hits::cpu1.data 4139705 # number of overall hits -system.l2c.overall_hits::total 25703456 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2145 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2004 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2360 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2181 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8690 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18258 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17747 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36005 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 795643 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 798642 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1594285 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 8034471 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 7876086 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 15910557 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3408054 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3401749 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6809803 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 357336 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 365120 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 722456 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 520227 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 197797 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 8034471 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4203697 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 519049 # 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number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2402,298 +2407,294 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1119014 # number of writebacks -system.l2c.writebacks::total 1119014 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 33 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 1 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010769 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004442 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.010701 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006021 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6520057498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13944779496 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004266 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010717 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004314 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011764 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006159 # mshr miss rate for ReadReq accesses system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.784986 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784155 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.784576 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785432 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781295 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.783375 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.240450 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.242800 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.241589 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005488 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006094 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005791 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041395 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.042882 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042132 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.395041 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.433008 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.414246 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004131 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010769 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005488 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.087546 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004442 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.010701 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006094 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.087721 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034117 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004131 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010769 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005488 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.087546 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004442 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.010701 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006094 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.087721 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034117 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 127829.676071 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70763.281849 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70751.310081 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70757.380919 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71250 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71125 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139392.773852 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139774.479890 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 139578.674506 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125469.445522 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125584.780871 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125530.164611 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131080.893745 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130493.219474 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130784.609938 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145245.877268 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145055.017575 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145144.961780 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125469.445522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136373.840007 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125584.780871 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136254.946515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 135135.772667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125469.445522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136373.840007 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125584.780871 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136254.946515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 135135.772667 # average overall mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.363636 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.249238 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.234077 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.241719 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005135 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006478 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005800 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.040698 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.044075 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042388 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.400718 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.425034 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.413259 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004266 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010717 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005135 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.088613 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011764 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.087132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034199 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004266 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010717 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005135 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.088613 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011764 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.087132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034199 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 129000.227448 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67991.057629 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67991.105000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67991.081119 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69250 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70250 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139439.219057 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139575.693355 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 139504.762779 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125238.213543 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125970.169055 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125643.181140 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130826.925373 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130488.236882 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130650.692885 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145334.302216 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145079.841747 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145199.328106 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125238.213543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136392.628753 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125970.169055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136020.568810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 135062.582465 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125238.213543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136392.628753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125970.169055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136020.568810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 135062.582465 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167572.516701 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169190.865353 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176976.360342 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149581.013880 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176241.949758 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169926.263903 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172679.442604 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175186.169638 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149571.674391 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176579.940245 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169749.909256 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172666.844654 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 171719.761610 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 172787.806528 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173321.915512 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 158423.602545 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 172410.754370 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 158412.999228 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54324 # Transaction distribution -system.membus.trans_dist::ReadResp 463697 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1225644 # Transaction distribution -system.membus.trans_dist::CleanEvict 212879 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36939 # Transaction distribution +system.membus.trans_dist::ReadReq 54329 # Transaction distribution +system.membus.trans_dist::ReadResp 466235 # Transaction distribution +system.membus.trans_dist::WriteReq 33699 # Transaction distribution +system.membus.trans_dist::WriteResp 33699 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1224424 # Transaction distribution +system.membus.trans_dist::CleanEvict 216307 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36790 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36943 # Transaction distribution -system.membus.trans_dist::ReadExReq 1016012 # Transaction distribution -system.membus.trans_dist::ReadExResp 1016012 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 409373 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 1016209 # Transaction distribution +system.membus.trans_dist::ReadExResp 1016209 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 411906 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4278076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4407714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4749732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6874 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4246337 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4375991 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237825 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237825 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4613816 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163572972 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 163744670 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 170997854 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2815 # Total snoops (count) -system.membus.snoop_fanout::samples 3097878 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163669548 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 163841278 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7262720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 171103998 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2667 # Total snoops (count) +system.membus.snoop_fanout::samples 3100373 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3097878 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3100373 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3097878 # Request fanout histogram -system.membus.reqLayer0.occupancy 113853500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3100373 # Request fanout histogram +system.membus.reqLayer0.occupancy 113885000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5460502 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5470002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8296545910 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8294790249 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7735775396 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7676329675 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227455723 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44628309 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2710,11 +2711,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2747,64 +2748,64 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 53686542 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 27275171 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 4479 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2151 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2151 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 53748943 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 27300315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 4554 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2137 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2137 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 2028951 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25110801 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9228831 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15970717 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2648270 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45894 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45906 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2100210 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2100210 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15974768 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7115167 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1336742 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1230078 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47961225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31535681 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 914731 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2490388 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 82902025 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2045811904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1101659806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3076664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8367272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3158915646 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2102692 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 30077408 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027456 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.163407 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2032183 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25147760 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33699 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33699 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9230552 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16002915 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2655847 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45875 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45886 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2102499 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2102499 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16003573 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7120105 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1337967 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1231303 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48051162 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31561925 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 916568 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2490426 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 83020081 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2049724352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1102308286 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3082904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8350216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3163465758 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2107044 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 30117798 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027021 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.162144 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 29251611 97.25% 97.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 825797 2.75% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 29303991 97.30% 97.30% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 813807 2.70% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30077408 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 51459246454 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30117798 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 51529807954 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1450396 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1428891 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24008829328 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24051879645 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14504682071 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14516066687 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 530598551 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 531626613 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1447405469 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1449630863 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16329 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16333 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |