diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt | 4565 |
1 files changed, 2287 insertions, 2278 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index ad76c447e..d85138b4f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,158 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.284902 # Number of seconds simulated -sim_ticks 51284901790000 # Number of ticks simulated -final_tick 51284901790000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.317219 # Number of seconds simulated +sim_ticks 51317219225000 # Number of ticks simulated +final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166610 # Simulator instruction rate (inst/s) -host_op_rate 195762 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9559915430 # Simulator tick rate (ticks/s) -host_mem_usage 696216 # Number of bytes of host memory used -host_seconds 5364.58 # Real time elapsed on the host -sim_insts 893791087 # Number of instructions simulated -sim_ops 1050181412 # Number of ops (including micro ops) simulated +host_inst_rate 190793 # Simulator instruction rate (inst/s) +host_op_rate 224183 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10734613908 # Simulator tick rate (ticks/s) +host_mem_usage 694152 # Number of bytes of host memory used +host_seconds 4780.54 # Real time elapsed on the host +sim_insts 912094204 # Number of instructions simulated +sim_ops 1071714405 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 151616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3547392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 26803872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 164672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 152640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3783872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 26210856 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417152 # Number of bytes read from this memory -system.physmem.bytes_read::total 61363464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3547392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3783872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7331264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79575360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 79595940 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2369 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 55428 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 418819 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2573 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2385 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59123 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 409549 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6518 # Number of read requests responded to by this memory -system.physmem.num_reads::total 958817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1243365 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1245938 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 69170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 522646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 73781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 511083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1196521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 73781 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 142952 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1551633 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1552035 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1551633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 522647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 73781 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 511484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2748556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 958817 # Number of read requests accepted -system.physmem.writeReqs 1245938 # Number of write requests accepted -system.physmem.readBursts 958817 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1245938 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61319744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44544 # Total number of bytes read from write queue -system.physmem.bytesWritten 79596352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61363464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 79595940 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 696 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2241 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu0.dtb.walker 178240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 158592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3667840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 28126168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 173888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 153280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3614336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 28857840 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory +system.physmem.bytes_read::total 65359176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3667840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3614336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7282176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83655232 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory +system.physmem.bytes_written::total 83675812 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2785 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 57310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 439479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56474 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 450909 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1021250 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1307113 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1309686 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 71474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 548084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 562342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1273631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 71474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1630159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1630560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1630159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 71474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 548485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 562342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2904191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1021250 # Number of read requests accepted +system.physmem.writeReqs 1309686 # Number of write requests accepted +system.physmem.readBursts 1021250 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1309686 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 65325376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 34624 # Total number of bytes read from write queue +system.physmem.bytesWritten 83676352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 65359176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 83675812 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2238 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56014 # Per bank write bursts -system.physmem.perBankRdBursts::1 61765 # Per bank write bursts -system.physmem.perBankRdBursts::2 56852 # Per bank write bursts -system.physmem.perBankRdBursts::3 54266 # Per bank write bursts -system.physmem.perBankRdBursts::4 57300 # Per bank write bursts -system.physmem.perBankRdBursts::5 65586 # Per bank write bursts -system.physmem.perBankRdBursts::6 58254 # Per bank write bursts -system.physmem.perBankRdBursts::7 56988 # Per bank write bursts -system.physmem.perBankRdBursts::8 55394 # Per bank write bursts -system.physmem.perBankRdBursts::9 83577 # Per bank write bursts -system.physmem.perBankRdBursts::10 57993 # Per bank write bursts -system.physmem.perBankRdBursts::11 64464 # Per bank write bursts -system.physmem.perBankRdBursts::12 57098 # Per bank write bursts -system.physmem.perBankRdBursts::13 62288 # Per bank write bursts -system.physmem.perBankRdBursts::14 55335 # Per bank write bursts -system.physmem.perBankRdBursts::15 54947 # Per bank write bursts -system.physmem.perBankWrBursts::0 75753 # Per bank write bursts -system.physmem.perBankWrBursts::1 78600 # Per bank write bursts -system.physmem.perBankWrBursts::2 75987 # Per bank write bursts -system.physmem.perBankWrBursts::3 76409 # Per bank write bursts -system.physmem.perBankWrBursts::4 77268 # Per bank write bursts -system.physmem.perBankWrBursts::5 81844 # Per bank write bursts -system.physmem.perBankWrBursts::6 76609 # Per bank write bursts -system.physmem.perBankWrBursts::7 77405 # Per bank write bursts -system.physmem.perBankWrBursts::8 75535 # Per bank write bursts -system.physmem.perBankWrBursts::9 81820 # Per bank write bursts -system.physmem.perBankWrBursts::10 76863 # Per bank write bursts -system.physmem.perBankWrBursts::11 81595 # Per bank write bursts -system.physmem.perBankWrBursts::12 75866 # Per bank write bursts -system.physmem.perBankWrBursts::13 80975 # Per bank write bursts -system.physmem.perBankWrBursts::14 75599 # Per bank write bursts -system.physmem.perBankWrBursts::15 75565 # Per bank write bursts +system.physmem.perBankRdBursts::0 59538 # Per bank write bursts +system.physmem.perBankRdBursts::1 65186 # Per bank write bursts +system.physmem.perBankRdBursts::2 59192 # Per bank write bursts +system.physmem.perBankRdBursts::3 61503 # Per bank write bursts +system.physmem.perBankRdBursts::4 61968 # Per bank write bursts +system.physmem.perBankRdBursts::5 71297 # Per bank write bursts +system.physmem.perBankRdBursts::6 63621 # Per bank write bursts +system.physmem.perBankRdBursts::7 62505 # Per bank write bursts +system.physmem.perBankRdBursts::8 57971 # Per bank write bursts +system.physmem.perBankRdBursts::9 85989 # Per bank write bursts +system.physmem.perBankRdBursts::10 63150 # Per bank write bursts +system.physmem.perBankRdBursts::11 64998 # Per bank write bursts +system.physmem.perBankRdBursts::12 58754 # Per bank write bursts +system.physmem.perBankRdBursts::13 64690 # Per bank write bursts +system.physmem.perBankRdBursts::14 59967 # Per bank write bursts +system.physmem.perBankRdBursts::15 60380 # Per bank write bursts +system.physmem.perBankWrBursts::0 78521 # Per bank write bursts +system.physmem.perBankWrBursts::1 82873 # Per bank write bursts +system.physmem.perBankWrBursts::2 79926 # Per bank write bursts +system.physmem.perBankWrBursts::3 82832 # Per bank write bursts +system.physmem.perBankWrBursts::4 82609 # Per bank write bursts +system.physmem.perBankWrBursts::5 88110 # Per bank write bursts +system.physmem.perBankWrBursts::6 81518 # Per bank write bursts +system.physmem.perBankWrBursts::7 82656 # Per bank write bursts +system.physmem.perBankWrBursts::8 78895 # Per bank write bursts +system.physmem.perBankWrBursts::9 84228 # Per bank write bursts +system.physmem.perBankWrBursts::10 80757 # Per bank write bursts +system.physmem.perBankWrBursts::11 83094 # Per bank write bursts +system.physmem.perBankWrBursts::12 78112 # Per bank write bursts +system.physmem.perBankWrBursts::13 83897 # Per bank write bursts +system.physmem.perBankWrBursts::14 79365 # Per bank write bursts +system.physmem.perBankWrBursts::15 80050 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 53 # Number of times write queue was full causing retry -system.physmem.totGap 51284900546000 # Total gap between requests +system.physmem.numWrRetry 115 # Number of times write queue was full causing retry +system.physmem.totGap 51317218019000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 958802 # Read request sizes (log2) +system.physmem.readPktSize::6 1021235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1243365 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 542154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 273293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 94311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1098 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1307113 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 561294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 302542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 104557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -165,216 +162,216 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 66664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 70454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 71905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 72565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 73989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 82526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 89703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 76639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 77053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 72033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 68023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 139 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 555731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 253.568320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.645025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 292.798773 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 244526 44.00% 44.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 138101 24.85% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53162 9.57% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26648 4.80% 83.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19957 3.59% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11140 2.00% 88.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10224 1.84% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6833 1.23% 91.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 45140 8.12% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 555731 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 64596 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.832281 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 53.413760 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 64590 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7680-8191 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8704-9215 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 64596 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 64596 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.253406 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.362319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.482686 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 110 0.17% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 65 0.10% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 55177 85.42% 85.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6740 10.43% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 705 1.09% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 447 0.69% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 541 0.84% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 101 0.16% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 328 0.51% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 148 0.23% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 164 0.25% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 17 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 64596 # Writes before turning the bus around for reads -system.physmem.totQLat 25254361125 # Total ticks spent queuing -system.physmem.totMemAccLat 43219129875 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4790605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26358.22 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 41729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 74771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 78166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 83727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 87147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 84488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 87764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 90437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 81373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 72156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 67158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 578062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 257.760143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.645909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 296.380743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251223 43.46% 43.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 144003 24.91% 68.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55356 9.58% 77.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27668 4.79% 82.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20975 3.63% 86.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11890 2.06% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10828 1.87% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7399 1.28% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 48720 8.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 578062 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61477 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.602941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.801588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 61469 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61477 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61477 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.267189 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.511196 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.879627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 57149 92.96% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 2185 3.55% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1043 1.70% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 635 1.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 196 0.32% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 105 0.17% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 30 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 57 0.09% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 29 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 5 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-895 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1504-1535 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61477 # Writes before turning the bus around for reads +system.physmem.totQLat 27580144715 # Total ticks spent queuing +system.physmem.totMemAccLat 46718438465 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5103545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27020.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45108.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45770.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.83 # Average write queue length when enqueuing -system.physmem.readRowHits 736278 # Number of row buffer hits during reads -system.physmem.writeRowHits 909804 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 23261042.86 # Average gap between requests -system.physmem.pageHitRate 74.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2087694000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1139118750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3642795000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4016790000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3349680278880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1234735113780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29687838385500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34283140175910 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.484113 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49388248138285 # Time in different power states -system.physmem_0.memoryStateTime::REF 1712515480000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.54 # Average write queue length when enqueuing +system.physmem.readRowHits 791160 # Number of row buffer hits during reads +system.physmem.writeRowHits 958928 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.34 # Row buffer hit rate for writes +system.physmem.avgGap 22015713.01 # Average gap between requests +system.physmem.pageHitRate 75.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2219328720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1210943250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3937471200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4270611600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1232390071935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29709283194000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34305102423585 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.491159 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49423935419086 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713594480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184135332965 # Time in different power states +system.physmem_0.memoryStateTime::ACT 179688951414 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2113632360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1153271625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3830509800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4042340640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3349680278880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1240634967750 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29682663075000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34284118076055 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.503181 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49379589334828 # Time in different power states -system.physmem_1.memoryStateTime::REF 1712515480000 # Time in different power states +system.physmem_1.actEnergy 2150820000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1173562500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4024012200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4201619040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1230344610120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29711077467000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34304762893740 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.484542 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49426892036602 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713594480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 192796355672 # Time in different power states +system.physmem_1.memoryStateTime::ACT 176725372148 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 1024 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 2148 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 1088 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 1024 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 2112 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 17 # Number of read requests responded to by this memory +system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 21 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 20 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 42 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 21 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 20 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 41 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 21 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 20 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 42 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131701737 # Number of BP lookups -system.cpu0.branchPred.condPredicted 88290011 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5749928 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 88871773 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 60662484 # Number of BTB hits +system.cpu0.branchPred.lookups 133997601 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89911686 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5854244 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 89985465 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61739918 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 68.258438 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16943081 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 189225 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4992924 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2589273 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 2403651 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 412581 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 68.610990 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17379215 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 192773 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4943112 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2622279 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 2320833 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 406549 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -405,91 +402,93 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 895264 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 895264 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17123 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90441 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 554296 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 340968 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2750.470719 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 16351.798354 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 338087 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1498 0.44% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 976 0.29% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 136 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 169 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 39 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 931838 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 931838 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17645 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95375 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 582006 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 349832 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2584.187553 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14750.130751 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 347090 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1907 0.55% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 488 0.14% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 130 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 123 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 48 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 340968 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 416487 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22961.536615 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18398.217426 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 19575.689133 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 407358 97.81% 97.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6820 1.64% 99.45% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1636 0.39% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 111 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 329 0.08% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 154 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 63 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 416487 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 342294024144 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.109470 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.721232 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 341240531644 99.69% 99.69% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 582822500 0.17% 99.86% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 199579000 0.06% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 117924500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 46760000 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 24862000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 28899000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 44321000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 7892500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 388000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 22500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 10500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 342294024144 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90442 84.08% 84.08% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17123 15.92% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 107565 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 895264 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 349832 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 445532 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23200.793658 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 19017.924437 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16422.337995 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 338631 76.01% 76.01% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 97435 21.87% 97.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 7291 1.64% 99.51% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1212 0.27% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 239 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 222 0.05% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 191 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 178 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 71 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 21 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 14 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 445532 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 361726794756 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.119484 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.718354 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 360638415756 99.70% 99.70% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 594419500 0.16% 99.86% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 206814500 0.06% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 128366500 0.04% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 51460000 0.01% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 27618000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 28344500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 44148500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6546000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 549000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 65000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 32000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 15500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 361726794756 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95376 84.39% 84.39% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17645 15.61% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 113021 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 931838 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 895264 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107565 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 931838 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113021 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107565 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1002829 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113021 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1044859 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 104837372 # DTB read hits -system.cpu0.dtb.read_misses 616098 # DTB read misses -system.cpu0.dtb.write_hits 80671443 # DTB write hits -system.cpu0.dtb.write_misses 279166 # DTB write misses -system.cpu0.dtb.flush_tlb 1102 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 105631864 # DTB read hits +system.cpu0.dtb.read_misses 640489 # DTB read misses +system.cpu0.dtb.write_hits 81680668 # DTB write hits +system.cpu0.dtb.write_misses 291349 # DTB write misses +system.cpu0.dtb.flush_tlb 1081 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21868 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55634 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 233 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9003 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 55450 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9899 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56722 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105453470 # DTB read accesses -system.cpu0.dtb.write_accesses 80950609 # DTB write accesses +system.cpu0.dtb.perms_faults 56099 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106272353 # DTB read accesses +system.cpu0.dtb.write_accesses 81972017 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 185508815 # DTB hits -system.cpu0.dtb.misses 895264 # DTB misses -system.cpu0.dtb.accesses 186404079 # DTB accesses +system.cpu0.dtb.hits 187312532 # DTB hits +system.cpu0.dtb.misses 931838 # DTB misses +system.cpu0.dtb.accesses 188244370 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -519,838 +518,837 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 102402 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102402 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3079 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69849 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14173 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88229 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1559.917941 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 11109.318329 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 87313 98.96% 98.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 469 0.53% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 83 0.09% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 147 0.17% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 141 0.16% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 43 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88229 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 87101 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28953.462073 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24215.206372 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 22576.849397 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 85266 97.89% 97.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 483 0.55% 98.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1148 1.32% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.08% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 97 0.11% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 24 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 102509 # Table walker walks requested +system.cpu0.itb.walker.walksLong 102509 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2958 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69563 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14385 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 88124 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1419.845899 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9093.034945 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 87142 98.89% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 616 0.70% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 206 0.23% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 105 0.12% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 24 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 88124 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 86906 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28693.715048 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24359.274514 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18506.887432 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 84671 97.43% 97.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1946 2.24% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 187 0.22% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 65 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 87101 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 630054255476 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.901585 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.298241 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 62069607016 9.85% 9.85% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 567926877960 90.14% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 53229500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 3926000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 600500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 14500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 630054255476 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 69849 95.78% 95.78% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3079 4.22% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72928 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 86906 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 610832410424 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.899859 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.300566 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 61230050100 10.02% 10.02% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 549548390324 89.97% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 48170500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 4945000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 599000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 205000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 50500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 610832410424 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 69563 95.92% 95.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2958 4.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72521 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102402 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102402 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102509 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72928 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72928 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 175330 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 93547159 # ITB inst hits -system.cpu0.itb.inst_misses 102402 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 175030 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 94735666 # ITB inst hits +system.cpu0.itb.inst_misses 102509 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1102 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1081 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21868 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41100 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40899 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 189115 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 193621 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 93649561 # ITB inst accesses -system.cpu0.itb.hits 93547159 # DTB hits -system.cpu0.itb.misses 102402 # DTB misses -system.cpu0.itb.accesses 93649561 # DTB accesses -system.cpu0.numCycles 688011025 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94838175 # ITB inst accesses +system.cpu0.itb.hits 94735666 # DTB hits +system.cpu0.itb.misses 102509 # DTB misses +system.cpu0.itb.accesses 94838175 # DTB accesses +system.cpu0.numCycles 677363519 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 243601869 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 585571838 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 131701737 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 80194838 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 401370000 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13146214 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2578790 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 20091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 3656 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 4829637 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 164032 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 3268 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 93342305 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3584098 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 39018 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 659144176 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.038197 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.295091 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 248081332 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 593905796 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 133997601 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81741412 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 389608891 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13373506 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2523552 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 22024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2940 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 4870394 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 168493 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2299 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94525599 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3651769 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 39552 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 651966408 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.065387 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.317537 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 515420904 78.20% 78.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 17940395 2.72% 80.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18023461 2.73% 83.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13220348 2.01% 85.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 27959766 4.24% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8806264 1.34% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9588960 1.45% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8203319 1.24% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39980759 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 506080688 77.62% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18214646 2.79% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18100947 2.78% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13291875 2.04% 85.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28751599 4.41% 89.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8986592 1.38% 91.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9770458 1.50% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8414345 1.29% 93.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 40355258 6.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 659144176 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.191424 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.851108 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 197499187 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 338466010 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 104398182 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13546805 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5231982 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19379138 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1360316 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 638255296 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4185441 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5231982 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 205063449 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 27153307 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 262923483 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 110249317 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 48520379 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 622996110 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 132355 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2247994 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1861879 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 28960972 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3803 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 595426650 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 956549851 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 734166245 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 794435 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 500270864 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 95155781 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15187791 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13237681 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 75403173 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100496845 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 84720468 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13599194 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14388955 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 590484103 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15298411 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 591681421 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 857551 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 80930976 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 50447616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 351888 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 659144176 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.897651 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.636567 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 651966408 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.197822 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.876790 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 201025214 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 326077447 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105614620 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13934386 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5312657 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19632987 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1393622 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 647334053 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4303710 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5312657 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 208746840 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 23221789 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 263564774 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111697152 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 39420825 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 631864038 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 81982 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1845422 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1714455 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 19477575 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3876 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 604366839 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 973584661 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 745191594 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 824988 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 507520310 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96846524 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15772416 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13809695 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 77902092 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 101804436 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85844339 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13951597 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14791131 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 598600479 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15906116 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 599443694 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 871420 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 82277994 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 51785989 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 367722 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 651966408 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.919440 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.646692 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 427475761 64.85% 64.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 97836885 14.84% 79.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 42770645 6.49% 86.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30584958 4.64% 90.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22743510 3.45% 94.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 15987914 2.43% 96.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10968411 1.66% 98.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6384440 0.97% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4391652 0.67% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 416000229 63.81% 63.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 100627614 15.43% 79.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43369864 6.65% 85.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31012057 4.76% 90.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22935032 3.52% 94.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16054599 2.46% 96.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11112799 1.70% 98.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6483448 0.99% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4370766 0.67% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 659144176 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 651966408 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2986555 25.26% 25.26% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 23747 0.20% 25.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2157 0.02% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4879643 41.27% 66.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3932744 33.26% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3017859 25.71% 25.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 24275 0.21% 25.92% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 3125 0.03% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4815194 41.03% 66.98% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3875781 33.02% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 139 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 401347935 67.83% 67.83% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1444621 0.24% 68.08% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 64829 0.01% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 116 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 56174 0.01% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 107054227 18.09% 86.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 81713380 13.81% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 50 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 407248355 67.94% 67.94% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1425936 0.24% 68.18% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 67925 0.01% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 173 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 60970 0.01% 68.20% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.20% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.20% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.20% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 107889592 18.00% 86.20% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82750693 13.80% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 591681421 # Type of FU issued -system.cpu0.iq.rate 0.859988 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11824846 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019985 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1854198838 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 686917057 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 569115204 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 990577 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 508872 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 439153 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 602977632 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 528496 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4632250 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 599443694 # Type of FU issued +system.cpu0.iq.rate 0.884966 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11736234 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019579 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1862428500 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 696963642 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 577071065 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1032950 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 531195 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 457217 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 610628639 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 551239 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4761086 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16643333 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 19794 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 724475 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8465055 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16972106 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20586 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 721660 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8682994 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3918685 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8300346 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 4003221 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7891299 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5231982 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15925349 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 9030114 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 605926435 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1719706 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100496845 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 84720468 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12946615 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 222991 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 8727203 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 724475 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2456659 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2686981 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5143640 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 584799722 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 104827609 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5998636 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5312657 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14923194 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6733387 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 614655210 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1737208 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 101804436 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85844339 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13513919 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 247440 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6392978 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 721660 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2504975 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2708374 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5213349 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 592463883 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105622287 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6061529 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 143921 # number of nop insts executed -system.cpu0.iew.exec_refs 185499348 # number of memory reference insts executed -system.cpu0.iew.exec_branches 108059724 # Number of branches executed -system.cpu0.iew.exec_stores 80671739 # Number of stores executed -system.cpu0.iew.exec_rate 0.849986 # Inst execution rate -system.cpu0.iew.wb_sent 570956210 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 569554357 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 281415896 # num instructions producing a value -system.cpu0.iew.wb_consumers 488383708 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.827827 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576219 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 80977867 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14946523 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4408529 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 645374166 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.813252 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.811592 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 148615 # number of nop insts executed +system.cpu0.iew.exec_refs 187306165 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109885900 # Number of branches executed +system.cpu0.iew.exec_stores 81683878 # Number of stores executed +system.cpu0.iew.exec_rate 0.874662 # Inst execution rate +system.cpu0.iew.wb_sent 578962486 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 577528282 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 284712169 # num instructions producing a value +system.cpu0.iew.wb_consumers 495210168 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.852612 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.574932 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 82335465 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15538394 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4479878 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 637982242 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.834237 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.825466 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 452622252 70.13% 70.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 95504432 14.80% 84.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32341034 5.01% 89.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15221107 2.36% 92.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10764054 1.67% 93.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6526900 1.01% 94.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6016149 0.93% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3811802 0.59% 96.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22566436 3.50% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 441101470 69.14% 69.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 98311443 15.41% 84.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33085662 5.19% 89.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15424273 2.42% 92.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10896564 1.71% 93.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6486229 1.02% 94.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6026213 0.94% 95.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3904773 0.61% 96.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22745615 3.57% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 645374166 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 446835848 # Number of instructions committed -system.cpu0.commit.committedOps 524851533 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 637982242 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 452758888 # Number of instructions committed +system.cpu0.commit.committedOps 532228596 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 160108924 # Number of memory references committed -system.cpu0.commit.loads 83853511 # Number of loads committed -system.cpu0.commit.membars 3685792 # Number of memory barriers committed -system.cpu0.commit.branches 99662639 # Number of branches committed -system.cpu0.commit.fp_insts 420768 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 481718978 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13112301 # Number of function calls committed. +system.cpu0.commit.refs 161993674 # Number of memory references committed +system.cpu0.commit.loads 84832329 # Number of loads committed +system.cpu0.commit.membars 3784982 # Number of memory barriers committed +system.cpu0.commit.branches 101373358 # Number of branches committed +system.cpu0.commit.fp_insts 437523 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 488401874 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13443378 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 363528180 69.26% 69.26% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1118140 0.21% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48609 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 47680 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 83853511 15.98% 85.47% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 76255413 14.53% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 369014830 69.33% 69.33% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1117216 0.21% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 51029 0.01% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 51847 0.01% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84832329 15.94% 85.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77161345 14.50% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 524851533 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22566436 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1224636916 # The number of ROB reads -system.cpu0.rob.rob_writes 1225450764 # The number of ROB writes -system.cpu0.timesIdled 4112135 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28866849 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 54222947414 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 446835848 # Number of Instructions Simulated -system.cpu0.committedOps 524851533 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.539740 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.539740 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.649460 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.649460 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 688252111 # number of integer regfile reads -system.cpu0.int_regfile_writes 407094655 # number of integer regfile writes -system.cpu0.fp_regfile_reads 800302 # number of floating regfile reads -system.cpu0.fp_regfile_writes 473448 # number of floating regfile writes -system.cpu0.cc_regfile_reads 125192637 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126303504 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1203085849 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15043668 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10538852 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.973177 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 302937432 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10539364 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.743426 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 2695088500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 218.644895 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 293.328283 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.427041 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.572907 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 532228596 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22745615 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1225734406 # The number of ROB reads +system.cpu0.rob.rob_writes 1243135976 # The number of ROB writes +system.cpu0.timesIdled 4186507 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25397111 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 54288384692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 452758888 # Number of Instructions Simulated +system.cpu0.committedOps 532228596 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.496080 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.496080 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.668413 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.668413 # 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Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 302.186929 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 209.796481 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.590209 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.409759 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1336210971 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1336210971 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79968247 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80371614 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 160339861 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67069375 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67205589 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134274964 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199346 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 203477 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 402823 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 140986 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 183532 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 324518 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1741209 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1760714 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3501923 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2021774 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2019563 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4041337 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147178608 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 147760735 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 294939343 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147377954 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 147964212 # number of overall hits -system.cpu0.dcache.overall_hits::total 295342166 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6393063 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6235592 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12628655 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6405631 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6317446 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 12723077 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 674803 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 616721 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1291524 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 612571 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 127047892293 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 253037416547 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139976221754 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 138284454293 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 278260676047 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3092079500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3139092000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6231171500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3092079500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3139092000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6231171500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033016 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032774 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032895 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014709 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014531 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014620 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754211 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741430 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.748024 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.808618 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.768735 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787960 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060879 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058477 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059678 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4673731 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 4602629 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 9276360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5318127 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 5271545 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 10589672 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17867 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15813 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18974 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14723 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 36841 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30536 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45309693000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 45038920000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90348613000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40408833272 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 40500038516 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 80908871788 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10386373000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12065937500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22452310500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14266559663 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12400788300 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26667347963 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1747255500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1706730500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3453986000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 76000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 231000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 307000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99985085935 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97939746816 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 197924832751 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 110371458935 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110005684316 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 220377143251 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3393465500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2870779500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264245000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3393465500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2870779500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264245000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033347 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032797 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033069 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015025 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014517 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014768 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749949 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754197 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752107 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.784969 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.790040 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787378 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059303 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059305 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059304 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028280 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028142 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028211 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032210 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031759 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031984 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17440.928372 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17553.568824 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17497.120977 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47241.114431 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47759.959237 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47499.037457 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21214.691344 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.571002 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19901.389209 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 41362.237585 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42090.985634 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41730.490538 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14340.927979 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14896.880609 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14613.437986 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 51642.857143 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 32178.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27742.276658 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28050.685104 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27896.273460 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26914.777522 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26917.494210 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26916.127539 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183484.423214 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186561.987400 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185022.017341 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95056.088413 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 90087.300904 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92486.292932 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 16323462 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.933155 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 169414196 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16323974 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.378245 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19400599500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 237.111231 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 274.821924 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.463108 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.536762 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027835 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028304 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032576 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031710 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032139 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15558.354354 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15453.188309 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15505.750602 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36229.083866 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36833.050507 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36528.911241 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16117.997318 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18038.045883 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17095.945594 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22080.390242 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21070.676241 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21599.080521 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13706.329720 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13625.611732 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13666.325073 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12666.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 33000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23615.384615 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21392.991153 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21279.087847 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21336.476026 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20753.821587 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20867.826096 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20810.573099 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189929.227067 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181545.532157 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.022565 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92111.112619 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94012.951926 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.047182 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 16477862 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.835978 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 172394682 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16478374 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.461875 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12245675500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 287.122432 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 224.713546 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.560786 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.438894 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999680 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 203303412 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 203303412 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 84627850 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 84786346 # 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number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 20638 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103445364915 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103197184413 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 206642549328 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103445364915 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103197184413 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 206642549328 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103445364915 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103197184413 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 206642549328 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 974276500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 641521000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1615797500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 974276500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 641521000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1615797500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086673 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086673 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086673 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12540.028305 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065 # average overall mshr uncacheable latency +system.cpu1.branchPred.lookups 135004521 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90686520 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5841333 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91602372 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 61971036 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.902325 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17136106 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 189382 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4973679 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2647071 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 2326608 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 405619 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 67.652218 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17264827 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 189835 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 5144550 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2721808 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 2422742 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 415682 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1380,94 +1378,98 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 905143 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 905143 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17108 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91252 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 560527 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 344616 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2714.976960 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 16407.674532 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 341711 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1475 0.43% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 1008 0.29% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 155 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 28 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 24 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 38 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 344616 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 422123 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23405.519244 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.136881 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20434.088485 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 412646 97.75% 97.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6891 1.63% 99.39% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1818 0.43% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 156 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 358 0.08% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 124 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 77 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 40 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::786432-851967 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 422123 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 367737970920 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.152186 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.727251 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 366665366920 99.71% 99.71% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 581252000 0.16% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 209708000 0.06% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 124789500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 48258000 0.01% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 27968500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 30956000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 41073500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 7796500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 589000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 122000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 17500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 21000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::56-59 5000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::60-63 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 367737970920 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 91252 84.21% 84.21% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17108 15.79% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 108360 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 905143 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 920636 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 920636 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17624 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92524 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 572462 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 348174 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2542.994307 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15098.255497 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 345444 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1949 0.56% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.12% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 137 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 118 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 24 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 58 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::720896-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 348174 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 432733 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23053.791830 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18897.650182 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16323.118118 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 333564 77.08% 77.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 89713 20.73% 97.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7384 1.71% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1176 0.27% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 238 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 198 0.05% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 173 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 170 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 52 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 27 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 432733 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 314249886000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.018496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.687233 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 313186458000 99.66% 99.66% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 582171000 0.19% 99.85% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 205657500 0.07% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 123171000 0.04% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 50673000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 26248000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 27458500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 40663500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6954500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 344500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 34000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 16000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 30000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::52-55 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::56-59 2500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 314249886000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92524 84.00% 84.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17624 16.00% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 110148 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 920636 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 905143 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108360 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 920636 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 110148 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108360 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1013503 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 110148 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1030784 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 104254499 # DTB read hits -system.cpu1.dtb.read_misses 630275 # DTB read misses -system.cpu1.dtb.write_hits 80849259 # DTB write hits -system.cpu1.dtb.write_misses 274868 # DTB write misses -system.cpu1.dtb.flush_tlb 1096 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 107706385 # DTB read hits +system.cpu1.dtb.read_misses 633869 # DTB read misses +system.cpu1.dtb.write_hits 83022369 # DTB write hits +system.cpu1.dtb.write_misses 286767 # DTB write misses +system.cpu1.dtb.flush_tlb 1089 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 20902 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 53828 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 197 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9278 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 55426 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9714 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 53866 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 104884774 # DTB read accesses -system.cpu1.dtb.write_accesses 81124127 # DTB write accesses +system.cpu1.dtb.perms_faults 57000 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 108340254 # DTB read accesses +system.cpu1.dtb.write_accesses 83309136 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 185103758 # DTB hits -system.cpu1.dtb.misses 905143 # DTB misses -system.cpu1.dtb.accesses 186008901 # DTB accesses +system.cpu1.dtb.hits 190728754 # DTB hits +system.cpu1.dtb.misses 920636 # DTB misses +system.cpu1.dtb.accesses 191649390 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1497,387 +1499,389 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 101154 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101154 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3005 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68686 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14200 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 86954 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1608.292890 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 11331.097997 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 85986 98.89% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 520 0.60% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 66 0.08% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 164 0.19% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 145 0.17% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 40 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 11 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 101988 # Table walker walks requested +system.cpu1.itb.walker.walksLong 101988 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3087 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69367 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14377 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 87611 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1414.069010 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8744.624659 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 86637 98.89% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 608 0.69% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 209 0.24% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 111 0.13% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 21 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 86954 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 85891 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 29748.012015 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24412.003991 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 25999.467191 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 83578 97.31% 97.31% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 495 0.58% 97.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1521 1.77% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 97 0.11% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 134 0.16% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 37 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 24 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 85891 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 612540191292 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.893340 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.309134 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 65404482540 10.68% 10.68% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 547076306252 89.31% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 50127000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 7455500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 1506000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 91500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 196000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 612540191292 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 68686 95.81% 95.81% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3005 4.19% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 71691 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 87611 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86831 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28749.490389 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24437.163786 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18363.738628 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 45615 52.53% 52.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 39084 45.01% 97.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 938 1.08% 98.62% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.06% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.11% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 11 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 11 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86831 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 606307709128 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.900370 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.299888 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 60468146000 9.97% 9.97% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 545785217128 90.02% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 47888000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5793500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 658000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 606307709128 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 69367 95.74% 95.74% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3087 4.26% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72454 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101154 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101154 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101988 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101988 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71691 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71691 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 172845 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 93866720 # ITB inst hits -system.cpu1.itb.inst_misses 101154 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72454 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72454 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174442 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 95828100 # ITB inst hits +system.cpu1.itb.inst_misses 101988 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1096 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1089 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 20902 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 39904 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40809 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 187991 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 188352 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 93967874 # ITB inst accesses -system.cpu1.itb.hits 93866720 # DTB hits -system.cpu1.itb.misses 101154 # DTB misses -system.cpu1.itb.accesses 93967874 # DTB accesses -system.cpu1.numCycles 688149644 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 95930088 # ITB inst accesses +system.cpu1.itb.hits 95828100 # DTB hits +system.cpu1.itb.misses 101988 # DTB misses +system.cpu1.itb.accesses 95930088 # DTB accesses +system.cpu1.numCycles 668684774 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 246774526 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 586387121 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 132207984 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 80391400 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 398002232 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13247809 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2526813 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23208 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 3339 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 4746787 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 172822 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 4142 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 93657492 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3619612 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 39280 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 658877500 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.040777 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.297556 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 248375133 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 600185967 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 135004521 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81957671 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 381222161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13317970 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2536848 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 21164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2785 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 4727264 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 160612 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2602 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 95618947 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3633834 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39185 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 643707284 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.089618 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.340143 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 514943270 78.15% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 17992448 2.73% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 17938734 2.72% 83.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13188969 2.00% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 27941093 4.24% 89.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8949077 1.36% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9653002 1.47% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8287474 1.26% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39983433 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 496523035 77.13% 77.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18305041 2.84% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18509005 2.88% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13552167 2.11% 84.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28450532 4.42% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9097899 1.41% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9820940 1.53% 92.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8391092 1.30% 93.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 41057573 6.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 658877500 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.192121 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.852122 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 200321379 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 334897766 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105062974 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13347316 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5245962 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19411078 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1397694 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 639286066 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4311897 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5245962 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 207822387 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 28109229 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 259552504 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 110777742 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 47367249 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 624073748 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 113090 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1957012 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1963484 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 28046902 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3748 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 596057640 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 957465344 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 735885626 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 888832 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 500042308 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 96015332 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14940728 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12988345 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 74317967 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 100818071 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 84975729 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13584844 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14513721 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 591824868 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15016632 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 591532545 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 864332 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 81511621 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 51286616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 358770 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 658877500 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.897788 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.636922 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 643707284 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.201896 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.897562 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 201561818 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 315815468 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 107257676 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13770315 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5299898 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19801436 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1379430 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 654914208 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4252969 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5299898 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 209252042 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22880216 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 253975050 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 113199216 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39098550 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 639470628 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 86957 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2174171 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1609351 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19507965 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3945 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 611072160 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 980685418 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 753664877 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 843607 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 514110066 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 96962094 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15327241 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13321250 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76568402 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 103346770 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 87233341 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13784187 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14730689 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 606543686 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15379714 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 607376538 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 875474 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 82437591 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 51624950 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 357944 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 643707284 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.943560 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.668311 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 427630752 64.90% 64.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 97159571 14.75% 79.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 42910564 6.51% 86.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 30776221 4.67% 90.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 22686133 3.44% 94.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 15935700 2.42% 96.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10990898 1.67% 98.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6446525 0.98% 99.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4341136 0.66% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 406849245 63.20% 63.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 99415625 15.44% 78.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43745607 6.80% 85.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31472621 4.89% 90.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23315391 3.62% 93.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16399031 2.55% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11324350 1.76% 98.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6634295 1.03% 99.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4551119 0.71% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 658877500 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 643707284 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2999770 25.98% 25.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 25009 0.22% 26.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 3249 0.03% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4684166 40.56% 66.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3835188 33.21% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3079713 25.38% 25.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 23466 0.19% 25.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2047 0.02% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4953216 40.82% 66.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 4075474 33.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 401605558 67.89% 67.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1412010 0.24% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67658 0.01% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 191 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 72305 0.01% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 106483903 18.00% 86.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 81890872 13.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 65 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 411722588 67.79% 67.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1463458 0.24% 68.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 65529 0.01% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 206 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 66963 0.01% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 109966089 18.11% 86.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 84091577 13.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 591532545 # Type of FU issued -system.cpu1.iq.rate 0.859599 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11547382 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019521 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1853248239 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 688458824 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 569767413 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1106065 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 569050 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 490960 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 602490208 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 589717 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4719123 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 607376538 # Type of FU issued +system.cpu1.iq.rate 0.908315 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 12133916 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019978 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1870398622 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 704521244 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 584421121 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1071128 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 544645 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 476254 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 618939378 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 571011 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4788717 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16759885 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 20137 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 685641 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8616382 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16961682 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 19758 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 716289 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8689454 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3886436 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 7425204 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3983377 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8390309 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5245962 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 16637308 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 9398313 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 606988228 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1717377 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 100818071 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 84975729 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12705052 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 239734 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9069380 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 685641 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2485685 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2694157 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5179842 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 584642052 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 104243442 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5998727 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5299898 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14473954 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6659801 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 622069689 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1729386 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 103346770 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 87233341 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13033934 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 237234 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6338314 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 716289 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2501247 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2722291 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5223538 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 600362187 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 107695161 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6106837 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 146728 # number of nop insts executed -system.cpu1.iew.exec_refs 185095226 # number of memory reference insts executed -system.cpu1.iew.exec_branches 108396618 # Number of branches executed -system.cpu1.iew.exec_stores 80851784 # Number of stores executed -system.cpu1.iew.exec_rate 0.849586 # Inst execution rate -system.cpu1.iew.wb_sent 571674985 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 570258373 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 281283764 # num instructions producing a value -system.cpu1.iew.wb_consumers 489058083 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.828684 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575154 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 81573069 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14657862 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4448279 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 645042111 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.814412 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.812297 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 146289 # number of nop insts executed +system.cpu1.iew.exec_refs 190717674 # number of memory reference insts executed +system.cpu1.iew.exec_branches 110987821 # Number of branches executed +system.cpu1.iew.exec_stores 83022513 # Number of stores executed +system.cpu1.iew.exec_rate 0.897825 # Inst execution rate +system.cpu1.iew.wb_sent 586317808 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 584897375 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 289057464 # num instructions producing a value +system.cpu1.iew.wb_consumers 502211172 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.874698 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575570 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 82490328 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15021770 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4481976 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 629716363 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.856712 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.853018 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 452426770 70.14% 70.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 94787874 14.69% 84.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 32819397 5.09% 89.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15329214 2.38% 92.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10832611 1.68% 93.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6451723 1.00% 94.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5988175 0.93% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3853316 0.60% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22553031 3.50% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 432763054 68.72% 68.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 96847267 15.38% 84.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33152549 5.26% 89.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15677479 2.49% 91.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11079326 1.76% 93.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6740057 1.07% 94.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6209892 0.99% 95.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3949846 0.63% 96.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 23296893 3.70% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 645042111 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 446955239 # Number of instructions committed -system.cpu1.commit.committedOps 525329879 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 629716363 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 459335316 # Number of instructions committed +system.cpu1.commit.committedOps 539485809 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 160417533 # Number of memory references committed -system.cpu1.commit.loads 84058186 # Number of loads committed -system.cpu1.commit.membars 3661350 # Number of memory barriers committed -system.cpu1.commit.branches 99963573 # Number of branches committed -system.cpu1.commit.fp_insts 470740 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 482339888 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13268232 # Number of function calls committed. +system.cpu1.commit.refs 164928975 # Number of memory references committed +system.cpu1.commit.loads 86385088 # Number of loads committed +system.cpu1.commit.membars 3716704 # Number of memory barriers committed +system.cpu1.commit.branches 102438773 # Number of branches committed +system.cpu1.commit.fp_insts 458507 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 495134645 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13388221 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 363697714 69.23% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1101230 0.21% 69.44% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50710 0.01% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 62650 0.01% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84058186 16.00% 85.46% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76359347 14.54% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 373316618 69.20% 69.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1132929 0.21% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 49236 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 58009 0.01% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 86385088 16.01% 85.44% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78543887 14.56% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 525329879 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22553031 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1225507013 # The number of ROB reads -system.cpu1.rob.rob_writes 1227667180 # The number of ROB writes -system.cpu1.timesIdled 4198522 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 29272144 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 46970319294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 446955239 # Number of Instructions Simulated -system.cpu1.committedOps 525329879 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.539639 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.539639 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.649503 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.649503 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 688608688 # number of integer regfile reads -system.cpu1.int_regfile_writes 407764370 # number of integer regfile writes -system.cpu1.fp_regfile_reads 881042 # number of floating regfile reads -system.cpu1.fp_regfile_writes 529972 # number of floating regfile writes -system.cpu1.cc_regfile_reads 124702473 # number of cc regfile reads -system.cpu1.cc_regfile_writes 125859602 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1202737772 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14790646 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40305 # Transaction distribution -system.iobus.trans_dist::ReadResp 40305 # Transaction distribution +system.cpu1.commit.op_class_0::total 539485809 # Class of committed instruction +system.cpu1.commit.bw_lim_events 23296893 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1224452307 # The number of ROB reads +system.cpu1.rob.rob_writes 1257969342 # The number of ROB writes +system.cpu1.timesIdled 4181395 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 24977490 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46999639814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 459335316 # Number of Instructions Simulated +system.cpu1.committedOps 539485809 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.455766 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.455766 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.686924 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.686924 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 706650375 # number of integer regfile reads +system.cpu1.int_regfile_writes 418043743 # number of integer regfile writes +system.cpu1.fp_regfile_reads 853513 # number of floating regfile reads +system.cpu1.fp_regfile_writes 519324 # number of floating regfile writes +system.cpu1.cc_regfile_reads 128705619 # number of cc regfile reads +system.cpu1.cc_regfile_writes 129852515 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1200738028 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15156718 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1894,11 +1898,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1913,16 +1917,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47810500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47815500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 348000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 346000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1932,7 +1936,7 @@ system.iobus.reqLayer10.occupancy 10000 # La system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1940,73 +1944,73 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25726500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25701500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 40136500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 40146500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566999378 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568673363 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147728000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.419655 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.425589 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13096612113000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.546608 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.873047 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221663 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429565 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651228 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13089213782000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544365 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.881224 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221523 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430077 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651599 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115484 # number of demand (read+write) misses -system.iocache.demand_misses::total 115524 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115476 # number of demand (read+write) misses +system.iocache.demand_misses::total 115516 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115484 # number of overall misses -system.iocache.overall_misses::total 115524 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1649759369 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1654845369 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115476 # number of overall misses +system.iocache.overall_misses::total 115516 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5146000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1631213114 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1636359114 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13415597009 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13415597009 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15065356378 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15070793378 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15065356378 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15070793378 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12815787249 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12815787249 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5497000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14447000363 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14452497363 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5497000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14447000363 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14452497363 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115484 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115524 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115476 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115516 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115484 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115524 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115476 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115516 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2020,53 +2024,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187047.547506 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186840.393926 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185112.700182 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184920.229856 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125774.366319 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125774.366319 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130454.057514 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130455.951820 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130454.057514 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130455.951820 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33085 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120151.009235 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120151.009235 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 137425 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125112.515695 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 137425 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125112.515695 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31781 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3398 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3407 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.736610 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.328148 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8820 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8857 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115484 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115524 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115476 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115516 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115484 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115524 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1208759369 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1211995369 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115476 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115516 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3296000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1190613114 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1193909114 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077336951 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8077336951 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9286096320 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9289533320 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9286096320 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9289533320 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7475677012 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7475677012 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3497000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8666290126 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8669787126 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3497000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8666290126 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8669787126 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2080,589 +2084,594 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137047.547506 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136840.393926 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89081.081081 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12035.721839 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 188.618634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 273.886836 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3763.840034 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9974.897420 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.537800 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002462 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004048 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.052122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.183651 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002878 # 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Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2400888500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35689.019526 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.312182 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 256.355195 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4109.760843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 10213.253541 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 166.614140 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 239.422394 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3052.672621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11431.636266 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.544571 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 309 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 509 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2809 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 5038 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54135 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005753 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.955185 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 445845701 # Number of tag accesses -system.l2c.tags.data_accesses 445845701 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 522213 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 182395 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 8045447 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4274356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 532310 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 179240 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8184125 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4203560 # number of demand (read+write) hits -system.l2c.demand_hits::total 26123646 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 522213 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 182395 # number of overall hits -system.l2c.overall_hits::cpu0.inst 8045447 # number of overall hits -system.l2c.overall_hits::cpu0.data 4274356 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 532310 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 179240 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8184125 # number of overall hits -system.l2c.overall_hits::cpu1.data 4203560 # number of overall hits -system.l2c.overall_hits::total 26123646 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2376 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2075 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2579 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2408 # number of ReadReq misses -system.l2c.ReadReq_misses::total 9438 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18580 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17819 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36399 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 4 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 261621 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 263338 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 524959 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 42503 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 51451 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 93954 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 157952 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 146755 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 304707 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 247445 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 260841 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 508286 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2376 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2075 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 42503 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 419573 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2579 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2408 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 51451 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 410093 # number of demand (read+write) misses -system.l2c.demand_misses::total 933058 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2376 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2075 # number of overall misses -system.l2c.overall_misses::cpu0.inst 42503 # number of overall misses -system.l2c.overall_misses::cpu0.data 419573 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2579 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2408 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034482 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 127702.826866 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67993.299247 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68001.150457 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67997.142779 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69125 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69125 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140871.038586 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 140600.346714 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 140735.249970 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125198.239942 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125863.572409 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125562.592552 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131859.126889 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129652.622097 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130796.418389 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70089.561317 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69667.464087 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69872.950465 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125198.239942 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137478.571334 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125863.572409 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136682.806073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 135830.548449 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125198.239942 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137478.571334 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125863.572409 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136682.806073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 135830.548449 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112200.316431 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170980.180394 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112191.987513 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174056.876263 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149593.183366 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112200.316431 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 88578.130284 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112191.987513 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84048.816186 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92324.958248 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 54323 # Transaction distribution -system.membus.trans_dist::ReadResp 471198 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1243365 # Transaction distribution -system.membus.trans_dist::CleanEvict 218846 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37171 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.780666 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783455 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.782055 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.261389 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.266869 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.264109 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005435 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005878 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005656 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041594 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.043961 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042782 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.441504 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.390532 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.417207 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005056 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013284 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005435 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.092152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012848 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005878 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.094378 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036182 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005056 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013284 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005435 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.092152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012848 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005878 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.094378 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036182 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78893.350072 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19004.014441 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19028.007793 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19015.984879 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 72000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92332.559725 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92674.455243 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 92504.000491 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76094.883362 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80750.347127 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82691.860604 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81751.288869 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20825.027872 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20919.196314 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20867.046041 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177423.826048 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169041.073800 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.203929 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86046.293532 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87537.545848 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 81110.850412 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3192252 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1599225 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2999 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 54318 # Transaction distribution +system.membus.trans_dist::ReadResp 482453 # Transaction distribution +system.membus.trans_dist::WriteReq 33697 # Transaction distribution +system.membus.trans_dist::WriteResp 33697 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1307113 # Transaction distribution +system.membus.trans_dist::CleanEvict 222137 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37798 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 524316 # Transaction distribution -system.membus.trans_dist::ReadExResp 524316 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 416875 # Transaction distribution -system.membus.trans_dist::InvalidateReq 614824 # Transaction distribution +system.membus.trans_dist::ReadExReq 575301 # Transaction distribution +system.membus.trans_dist::ReadExResp 575301 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 428135 # Transaction distribution +system.membus.trans_dist::InvalidateReq 621651 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3802484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3932122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237507 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237507 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4169629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4001476 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4131122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4368798 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 133717932 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 133889630 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7241472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7241472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 141131102 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3009 # Total snoops (count) -system.membus.snoop_fanout::samples 3143476 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 141781676 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 141953450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7253312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149206762 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2813 # Total snoops (count) +system.membus.snoop_fanout::samples 1750905 # Request fanout histogram +system.membus.snoop_fanout::mean 0.020034 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.140117 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3143476 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1715827 98.00% 98.00% # Request fanout histogram +system.membus.snoop_fanout::1 35078 2.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3143476 # Request fanout histogram -system.membus.reqLayer0.occupancy 114116000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1750905 # Request fanout histogram +system.membus.reqLayer0.occupancy 114103000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5372500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5413500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8328651016 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8735804910 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5128575160 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5454823379 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44638442 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44601796 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2716,64 +2725,64 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 54578445 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 27714706 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 5543 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2124 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2124 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 55407066 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 28133350 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 5182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1867 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1867 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 2026220 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25543991 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9308329 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 16323462 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2693882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46501 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2114895 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2114895 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16324325 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7201544 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1338457 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1231793 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49012603 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31846136 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 876413 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2521080 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 84256232 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2090728512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1112078430 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2928944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8475824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3214211710 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2126745 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 30549096 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.026641 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.161031 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2058891 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25917963 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9449679 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16477862 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2759760 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 47359 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 47372 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2180704 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2180704 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16478635 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7382055 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1266688 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1234652 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49475900 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32614875 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 885296 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2587313 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 85563384 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2110504128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140051882 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2983576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8760712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3262300298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1987088 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 30865453 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.026594 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.160894 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 29735242 97.34% 97.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 813854 2.66% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 30044617 97.34% 97.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 820836 2.66% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30549096 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 52321567856 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30865453 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 53089488175 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1445388 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1406902 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24533352992 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24765766555 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14657364738 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 15040405076 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 510704141 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 512773114 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1464609307 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1495395971 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16351 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16437 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |