diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt | 4525 |
1 files changed, 2258 insertions, 2267 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index b5baf9b71..576c749c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.317219 # Number of seconds simulated -sim_ticks 51317219225000 # Number of ticks simulated -final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.317224 # Number of seconds simulated +sim_ticks 51317223946000 # Number of ticks simulated +final_tick 51317223946000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237803 # Simulator instruction rate (inst/s) -host_op_rate 279419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13379498708 # Simulator tick rate (ticks/s) -host_mem_usage 700916 # Number of bytes of host memory used -host_seconds 3835.51 # Real time elapsed on the host -sim_insts 912094204 # Number of instructions simulated -sim_ops 1071714405 # Number of ops (including micro ops) simulated +host_inst_rate 160482 # Simulator instruction rate (inst/s) +host_op_rate 188578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9038049637 # Simulator tick rate (ticks/s) +host_mem_usage 694112 # Number of bytes of host memory used +host_seconds 5677.91 # Real time elapsed on the host +sim_insts 911201050 # Number of instructions simulated +sim_ops 1070728401 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 178240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 158592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3667840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 28126168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 173888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 153280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3614336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 28857840 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory -system.physmem.bytes_read::total 65359176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3667840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3614336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7282176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83655232 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 175488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 146560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3612352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 27482328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 187136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 157760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3726080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 29409648 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 423552 # Number of bytes read from this memory +system.physmem.bytes_read::total 65320904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3612352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3726080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7338432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83980672 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 83675812 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 57310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 439479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56474 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 450909 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1021250 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1307113 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 84001252 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 56443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 429419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2924 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2465 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 459531 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6618 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1020652 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1312198 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1309686 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 71474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 548084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 562342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1273631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 71474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1630159 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1314771 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 70393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 535538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 72609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 573095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1272885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 70393 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 72609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 143001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1636501 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1630560 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1630159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 71474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 548485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 562342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2904191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1021250 # Number of read requests accepted -system.physmem.writeReqs 1309686 # Number of write requests accepted -system.physmem.readBursts 1021250 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1309686 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 65325376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 34624 # Total number of bytes read from write queue -system.physmem.bytesWritten 83676352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 65359176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 83675812 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2238 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1636902 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1636501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 70393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 535939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 72609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 573095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2909786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1020652 # Number of read requests accepted +system.physmem.writeReqs 1314771 # Number of write requests accepted +system.physmem.readBursts 1020652 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1314771 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 65284928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36800 # Total number of bytes read from write queue +system.physmem.bytesWritten 84000896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 65320904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 84001252 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 575 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2239 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 59538 # Per bank write bursts -system.physmem.perBankRdBursts::1 65186 # Per bank write bursts -system.physmem.perBankRdBursts::2 59192 # Per bank write bursts -system.physmem.perBankRdBursts::3 61503 # Per bank write bursts -system.physmem.perBankRdBursts::4 61968 # Per bank write bursts -system.physmem.perBankRdBursts::5 71297 # Per bank write bursts -system.physmem.perBankRdBursts::6 63621 # Per bank write bursts -system.physmem.perBankRdBursts::7 62505 # Per bank write bursts -system.physmem.perBankRdBursts::8 57971 # Per bank write bursts -system.physmem.perBankRdBursts::9 85989 # Per bank write bursts -system.physmem.perBankRdBursts::10 63150 # Per bank write bursts -system.physmem.perBankRdBursts::11 64998 # Per bank write bursts -system.physmem.perBankRdBursts::12 58754 # Per bank write bursts -system.physmem.perBankRdBursts::13 64690 # Per bank write bursts -system.physmem.perBankRdBursts::14 59967 # Per bank write bursts -system.physmem.perBankRdBursts::15 60380 # Per bank write bursts -system.physmem.perBankWrBursts::0 78521 # Per bank write bursts -system.physmem.perBankWrBursts::1 82873 # Per bank write bursts -system.physmem.perBankWrBursts::2 79926 # Per bank write bursts -system.physmem.perBankWrBursts::3 82832 # Per bank write bursts -system.physmem.perBankWrBursts::4 82609 # Per bank write bursts -system.physmem.perBankWrBursts::5 88110 # Per bank write bursts -system.physmem.perBankWrBursts::6 81518 # Per bank write bursts -system.physmem.perBankWrBursts::7 82656 # Per bank write bursts -system.physmem.perBankWrBursts::8 78895 # Per bank write bursts -system.physmem.perBankWrBursts::9 84228 # Per bank write bursts -system.physmem.perBankWrBursts::10 80757 # Per bank write bursts -system.physmem.perBankWrBursts::11 83094 # Per bank write bursts -system.physmem.perBankWrBursts::12 78112 # Per bank write bursts -system.physmem.perBankWrBursts::13 83897 # Per bank write bursts -system.physmem.perBankWrBursts::14 79365 # Per bank write bursts -system.physmem.perBankWrBursts::15 80050 # Per bank write bursts +system.physmem.perBankRdBursts::0 60738 # Per bank write bursts +system.physmem.perBankRdBursts::1 63324 # Per bank write bursts +system.physmem.perBankRdBursts::2 61558 # Per bank write bursts +system.physmem.perBankRdBursts::3 59296 # Per bank write bursts +system.physmem.perBankRdBursts::4 63003 # Per bank write bursts +system.physmem.perBankRdBursts::5 70930 # Per bank write bursts +system.physmem.perBankRdBursts::6 62473 # Per bank write bursts +system.physmem.perBankRdBursts::7 61273 # Per bank write bursts +system.physmem.perBankRdBursts::8 57204 # Per bank write bursts +system.physmem.perBankRdBursts::9 83606 # Per bank write bursts +system.physmem.perBankRdBursts::10 64602 # Per bank write bursts +system.physmem.perBankRdBursts::11 64452 # Per bank write bursts +system.physmem.perBankRdBursts::12 60809 # Per bank write bursts +system.physmem.perBankRdBursts::13 66792 # Per bank write bursts +system.physmem.perBankRdBursts::14 61061 # Per bank write bursts +system.physmem.perBankRdBursts::15 58956 # Per bank write bursts +system.physmem.perBankWrBursts::0 80045 # Per bank write bursts +system.physmem.perBankWrBursts::1 81301 # Per bank write bursts +system.physmem.perBankWrBursts::2 81272 # Per bank write bursts +system.physmem.perBankWrBursts::3 81440 # Per bank write bursts +system.physmem.perBankWrBursts::4 83523 # Per bank write bursts +system.physmem.perBankWrBursts::5 87218 # Per bank write bursts +system.physmem.perBankWrBursts::6 82653 # Per bank write bursts +system.physmem.perBankWrBursts::7 82595 # Per bank write bursts +system.physmem.perBankWrBursts::8 79330 # Per bank write bursts +system.physmem.perBankWrBursts::9 83624 # Per bank write bursts +system.physmem.perBankWrBursts::10 82850 # Per bank write bursts +system.physmem.perBankWrBursts::11 84015 # Per bank write bursts +system.physmem.perBankWrBursts::12 79570 # Per bank write bursts +system.physmem.perBankWrBursts::13 84630 # Per bank write bursts +system.physmem.perBankWrBursts::14 79832 # Per bank write bursts +system.physmem.perBankWrBursts::15 78616 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 115 # Number of times write queue was full causing retry -system.physmem.totGap 51317218019000 # Total gap between requests +system.physmem.numWrRetry 119 # Number of times write queue was full causing retry +system.physmem.totGap 51317222751500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1021235 # Read request sizes (log2) +system.physmem.readPktSize::6 1020637 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1307113 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 561294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 302542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 104557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1312198 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 562832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 301764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 103549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -163,109 +163,109 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 739 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 21632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 41729 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 578062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 257.760143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.645909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 296.380743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251223 43.46% 43.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 144003 24.91% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55356 9.58% 77.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27668 4.79% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20975 3.63% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11890 2.06% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10828 1.87% 90.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7399 1.28% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 48720 8.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 578062 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61477 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.602941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.801588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 61469 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 738 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 298 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 586236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.650755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.083309 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.038467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 256952 43.83% 43.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146727 25.03% 68.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55530 9.47% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27689 4.72% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21119 3.60% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11926 2.03% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10672 1.82% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7426 1.27% 91.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 48195 8.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 586236 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.539767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.609404 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 61664 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61477 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.267189 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.511196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.879627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 57149 92.96% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 2185 3.55% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1043 1.70% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 635 1.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 196 0.32% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 105 0.17% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 30 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61671 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61671 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.282515 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.526147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.873212 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 57372 93.03% 93.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 2142 3.47% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 1045 1.69% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 638 1.03% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 205 0.33% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 106 0.17% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 28 0.05% 99.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-255 57 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 29 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 30 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 4 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::352-383 11 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::384-415 7 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads @@ -281,58 +281,58 @@ system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Wr system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::1504-1535 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61477 # Writes before turning the bus around for reads -system.physmem.totQLat 27580144715 # Total ticks spent queuing -system.physmem.totMemAccLat 46718438465 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5103545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27020.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61671 # Writes before turning the bus around for reads +system.physmem.totQLat 27430760765 # Total ticks spent queuing +system.physmem.totMemAccLat 46557204515 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5100385000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26890.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45770.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45640.87 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.64 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.54 # Average write queue length when enqueuing -system.physmem.readRowHits 791160 # Number of row buffer hits during reads -system.physmem.writeRowHits 958928 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.34 # Row buffer hit rate for writes -system.physmem.avgGap 22015713.01 # Average gap between requests -system.physmem.pageHitRate 75.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2219328720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1210943250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3937471200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4270611600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1232390071935 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29709283194000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34305102423585 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.491159 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49423935419086 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713594480000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.21 # Average write queue length when enqueuing +system.physmem.readRowHits 787981 # Number of row buffer hits during reads +system.physmem.writeRowHits 958372 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes +system.physmem.avgGap 21973416.70 # Average gap between requests +system.physmem.pageHitRate 74.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2249478000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1227393750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3920233200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4277104560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351791311440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1233069997860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29708691447750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34305226966560 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.493484 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49422945373021 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713594740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 179688951414 # Time in different power states +system.physmem_0.memoryStateTime::ACT 180683706479 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2150820000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1173562500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4024012200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4201619040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1230344610120 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29711077467000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34304762893740 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.484542 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49426892036602 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713594480000 # Time in different power states +system.physmem_1.actEnergy 2182466160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1190829750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4036320600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4227986160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351791311440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1230809355630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29710674459000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34304912728740 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.487361 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49426230251457 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713594740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 176725372148 # Time in different power states +system.physmem_1.memoryStateTime::ACT 177398580543 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory @@ -355,30 +355,30 @@ system.realview.nvmem.bw_total::cpu0.inst 15 # T system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 133997601 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89911686 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5854244 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 89985465 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61739918 # Number of BTB hits +system.cpu0.branchPred.lookups 134105303 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90165699 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5786352 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 89882943 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61723151 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 68.610990 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17379215 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 192773 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4943112 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2622279 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 2320833 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 406549 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 68.670594 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17198111 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190210 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5005537 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2645934 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 2359603 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 409587 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -408,95 +408,95 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 931838 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 931838 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17645 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95375 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 582006 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 349832 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2584.187553 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14750.130751 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 347090 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1907 0.55% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 488 0.14% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 130 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 123 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 48 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 349832 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 445532 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23200.793658 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 19017.924437 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16422.337995 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 338631 76.01% 76.01% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 97435 21.87% 97.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 7291 1.64% 99.51% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1212 0.27% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 239 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 222 0.05% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 191 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 178 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 71 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 21 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 14 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 445532 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 361726794756 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.119484 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.718354 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 360638415756 99.70% 99.70% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 594419500 0.16% 99.86% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 206814500 0.06% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 128366500 0.04% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 51460000 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 27618000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 28344500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 44148500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 6546000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 549000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 65000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 32000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 15500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 361726794756 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95376 84.39% 84.39% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17645 15.61% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 113021 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 931838 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 899770 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 899770 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17075 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93436 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 556454 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 343316 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2623.475166 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14944.534863 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-32767 334883 97.54% 97.54% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-65535 5615 1.64% 99.18% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-98303 1161 0.34% 99.52% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-131071 826 0.24% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-163839 305 0.09% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::163840-196607 149 0.04% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-229375 96 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::229376-262143 57 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-294911 86 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::294912-327679 45 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-360447 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::360448-393215 18 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-425983 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::425984-458751 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 343316 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 426919 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23051.464095 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18844.709714 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16480.973938 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 417565 97.81% 97.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8400 1.97% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 455 0.11% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 392 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 68 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 426919 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 352898234664 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.139794 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.715758 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 351858805164 99.71% 99.71% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 566388500 0.16% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 206550000 0.06% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 120953500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 47115000 0.01% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 25743000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 26226000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 38984000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6924500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 487500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 24000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 352898234664 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 93436 84.55% 84.55% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17075 15.45% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 110511 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 899770 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 931838 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113021 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 899770 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110511 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113021 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1044859 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110511 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1010281 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 105631864 # DTB read hits -system.cpu0.dtb.read_misses 640489 # DTB read misses -system.cpu0.dtb.write_hits 81680668 # DTB write hits -system.cpu0.dtb.write_misses 291349 # DTB write misses +system.cpu0.dtb.read_hits 105998610 # DTB read hits +system.cpu0.dtb.read_misses 619021 # DTB read misses +system.cpu0.dtb.write_hits 82262350 # DTB write hits +system.cpu0.dtb.write_misses 280749 # DTB write misses system.cpu0.dtb.flush_tlb 1081 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55386 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9899 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22329 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 55918 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 189 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9571 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56099 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106272353 # DTB read accesses -system.cpu0.dtb.write_accesses 81972017 # DTB write accesses +system.cpu0.dtb.perms_faults 57075 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106617631 # DTB read accesses +system.cpu0.dtb.write_accesses 82543099 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 187312532 # DTB hits -system.cpu0.dtb.misses 931838 # DTB misses -system.cpu0.dtb.accesses 188244370 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 188260960 # DTB hits +system.cpu0.dtb.misses 899770 # DTB misses +system.cpu0.dtb.accesses 189160730 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,860 +526,859 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 102509 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102509 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2958 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69563 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14385 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88124 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1419.845899 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 9093.034945 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 87142 98.89% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 616 0.70% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 206 0.23% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 105 0.12% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 24 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 102467 # Table walker walks requested +system.cpu0.itb.walker.walksLong 102467 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2998 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69670 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14196 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 88271 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1375.933206 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8810.022108 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 87313 98.91% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 590 0.67% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 225 0.25% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 97 0.11% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 16 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88124 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 86906 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28693.715048 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24359.274514 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18506.887432 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 84671 97.43% 97.43% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1946 2.24% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 187 0.22% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 65 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 88271 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 86864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28386.103564 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24197.471815 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17986.515042 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 84889 97.73% 97.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1706 1.96% 99.69% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 161 0.19% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 62 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 31 0.04% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 86906 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 610832410424 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.899859 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.300566 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 61230050100 10.02% 10.02% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 549548390324 89.97% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 48170500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 4945000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 599000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 205000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 50500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 610832410424 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 69563 95.92% 95.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2958 4.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72521 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 86864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 606302699128 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.904496 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.294288 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 57963600068 9.56% 9.56% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 548286629060 90.43% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 47140500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 4566000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 404000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 270000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 89500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 606302699128 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 69670 95.87% 95.87% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2998 4.13% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72668 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102509 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102509 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102467 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102467 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72521 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72521 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 175030 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 94735666 # ITB inst hits -system.cpu0.itb.inst_misses 102509 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72668 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72668 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 175135 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 94697092 # ITB inst hits +system.cpu0.itb.inst_misses 102467 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1081 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40835 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22329 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41669 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 193621 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 188921 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94838175 # ITB inst accesses -system.cpu0.itb.hits 94735666 # DTB hits -system.cpu0.itb.misses 102509 # DTB misses -system.cpu0.itb.accesses 94838175 # DTB accesses -system.cpu0.numPwrStateTransitions 16108 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 8054 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3370274965.000869 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 64926982226.426781 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3593 44.61% 44.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.18% 99.79% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.04% 99.84% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988782302928 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 8054 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 24173024656883 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 27144194568117 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 677363519 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94799559 # ITB inst accesses +system.cpu0.itb.hits 94697092 # DTB hits +system.cpu0.itb.misses 102467 # DTB misses +system.cpu0.itb.accesses 94799559 # DTB accesses +system.cpu0.numPwrStateTransitions 15974 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 7987 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2945663211.345562 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 55329339473.705994 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3525 44.13% 44.13% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.64% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1988782294428 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 7987 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 27790211876983 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 23527012069017 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 671968082 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 248081332 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 593905796 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 133997601 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81741412 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 389608891 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13373506 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2523552 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 22024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2940 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 4870394 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 168493 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 2299 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94525599 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3651769 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 39552 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 651966408 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.065387 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.317537 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 245522731 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 595240198 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 134105303 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81567196 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 387351290 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13225502 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2523731 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 22012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 3023 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 4782962 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 167694 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2395 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94491838 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3604496 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 39400 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 646988319 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.075576 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.327336 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 506080688 77.62% 77.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18214646 2.79% 80.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18100947 2.78% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13291875 2.04% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28751599 4.41% 89.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8986592 1.38% 91.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9770458 1.50% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8414345 1.29% 93.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 40355258 6.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 500985180 77.43% 77.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18129867 2.80% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18167874 2.81% 83.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13357518 2.06% 85.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28640593 4.43% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8987633 1.39% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9763680 1.51% 92.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8383348 1.30% 93.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 40572626 6.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 651966408 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.197822 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.876790 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 201025214 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 326077447 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105614620 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13934386 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5312657 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19632987 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1393622 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 647334053 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4303710 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5312657 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 208746840 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 23221789 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 263564774 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111697152 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 39420825 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 631864038 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 81982 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1845422 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1714455 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 19477575 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3876 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 604366839 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 973584661 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 745191594 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 824988 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 507520310 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 96846524 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15772416 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13809695 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 77902092 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 101804436 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85844339 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13951597 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14791131 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 598600479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15906116 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 599443694 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 871420 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 82277994 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 51785989 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 367722 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 651966408 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.919440 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.646692 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 646988319 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.199571 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.885816 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 199030326 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 322925985 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105893213 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13875278 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5261155 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19621820 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1370848 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 649217042 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4232345 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5261155 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 206721651 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 22515587 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 261202094 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111943526 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 39341608 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 633848526 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 79662 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1830943 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1627304 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 19580203 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3993 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 606139321 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 975790571 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 747374109 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 852582 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 509962376 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96176945 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15656160 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13698263 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 77451785 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 102163876 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86418656 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13880040 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14667641 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 600742993 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15759066 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 601574255 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 855603 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 81711782 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 51353600 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 357908 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 646988319 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.929807 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.657116 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 416000229 63.81% 63.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 100627614 15.43% 79.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43369864 6.65% 85.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31012057 4.76% 90.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22935032 3.52% 94.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16054599 2.46% 96.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 11112799 1.70% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6483448 0.99% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4370766 0.67% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 411195381 63.56% 63.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 99990691 15.45% 79.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43358439 6.70% 85.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31042131 4.80% 90.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23015507 3.56% 94.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16185943 2.50% 96.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11141665 1.72% 98.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6569936 1.02% 99.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4488626 0.69% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 651966408 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 646988319 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3017859 25.71% 25.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 24275 0.21% 25.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 3125 0.03% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4815194 41.03% 66.98% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3875781 33.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2994179 25.40% 25.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 22123 0.19% 25.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2181 0.02% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4797008 40.69% 66.30% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3972728 33.70% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 50 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 407248355 67.94% 67.94% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1425936 0.24% 68.18% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 67925 0.01% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 173 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 60970 0.01% 68.20% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.20% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.20% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.20% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 107889592 18.00% 86.20% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82750693 13.80% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 408493998 67.90% 67.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1413538 0.23% 68.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 65279 0.01% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 146 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 55915 0.01% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108222779 17.99% 86.15% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83322549 13.85% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 599443694 # Type of FU issued -system.cpu0.iq.rate 0.884966 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11736234 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019579 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1862428500 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 696963642 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 577071065 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1032950 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 531195 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 457217 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 610628639 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 551239 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4761086 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 601574255 # Type of FU issued +system.cpu0.iq.rate 0.895242 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11788219 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019596 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1861718464 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 698381981 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 579322691 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1062187 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 541590 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 470908 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 612794722 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 567701 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4798771 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16972106 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 20586 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 721660 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8682994 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16823750 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20061 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 720899 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8636995 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 4003221 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7891299 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 4014042 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7828481 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5312657 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14923194 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6733387 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 614655210 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1737208 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 101804436 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85844339 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13513919 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 247440 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6392978 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 721660 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2504975 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2708374 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5213349 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 592463883 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 105622287 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 6061529 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5261155 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14418671 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6592888 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 616647515 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1731555 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 102163876 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86418656 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13404445 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 244099 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6259110 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 720899 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2467872 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2697760 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5165632 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 594649792 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105987908 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6038347 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 148615 # number of nop insts executed -system.cpu0.iew.exec_refs 187306165 # number of memory reference insts executed -system.cpu0.iew.exec_branches 109885900 # Number of branches executed -system.cpu0.iew.exec_stores 81683878 # Number of stores executed -system.cpu0.iew.exec_rate 0.874662 # Inst execution rate -system.cpu0.iew.wb_sent 578962486 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 577528282 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 284712169 # num instructions producing a value -system.cpu0.iew.wb_consumers 495210168 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.852612 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574932 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 82335465 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15538394 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4479878 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 637982242 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.834237 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.825466 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 145456 # number of nop insts executed +system.cpu0.iew.exec_refs 188253040 # number of memory reference insts executed +system.cpu0.iew.exec_branches 110177692 # Number of branches executed +system.cpu0.iew.exec_stores 82265132 # Number of stores executed +system.cpu0.iew.exec_rate 0.884938 # Inst execution rate +system.cpu0.iew.wb_sent 581218511 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 579793599 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 286101590 # num instructions producing a value +system.cpu0.iew.wb_consumers 497649201 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.862829 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.574906 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 81765486 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15401158 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4434486 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 633109401 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.844704 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.839642 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 441101470 69.14% 69.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 98311443 15.41% 84.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33085662 5.19% 89.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15424273 2.42% 92.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10896564 1.71% 93.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6486229 1.02% 94.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6026213 0.94% 95.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3904773 0.61% 96.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22745615 3.57% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 436470478 68.94% 68.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 97716674 15.43% 84.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 32967148 5.21% 89.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15484157 2.45% 92.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10846506 1.71% 93.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6530507 1.03% 94.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6073156 0.96% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3956859 0.62% 96.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 23063916 3.64% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 637982242 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 452758888 # Number of instructions committed -system.cpu0.commit.committedOps 532228596 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 633109401 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 455072762 # Number of instructions committed +system.cpu0.commit.committedOps 534790277 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 161993674 # Number of memory references committed -system.cpu0.commit.loads 84832329 # Number of loads committed -system.cpu0.commit.membars 3784982 # Number of memory barriers committed -system.cpu0.commit.branches 101373358 # Number of branches committed -system.cpu0.commit.fp_insts 437523 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 488401874 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13443378 # Number of function calls committed. +system.cpu0.commit.refs 163121787 # Number of memory references committed +system.cpu0.commit.loads 85340126 # Number of loads committed +system.cpu0.commit.membars 3736581 # Number of memory barriers committed +system.cpu0.commit.branches 101711661 # Number of branches committed +system.cpu0.commit.fp_insts 451530 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 490677146 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13330927 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 369014830 69.33% 69.33% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1117216 0.21% 69.54% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 51029 0.01% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 51847 0.01% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84832329 15.94% 85.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77161345 14.50% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 370465668 69.27% 69.27% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1106577 0.21% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48950 0.01% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 47295 0.01% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 85340126 15.96% 85.46% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77781661 14.54% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 532228596 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22745615 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1225734406 # The number of ROB reads -system.cpu0.rob.rob_writes 1243135976 # The number of ROB writes -system.cpu0.timesIdled 4186507 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25397111 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 54288384692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 452758888 # Number of Instructions Simulated -system.cpu0.committedOps 532228596 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.496080 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.496080 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.668413 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.668413 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 697890382 # number of integer regfile reads -system.cpu0.int_regfile_writes 412518994 # number of integer regfile writes -system.cpu0.fp_regfile_reads 828341 # number of floating regfile reads -system.cpu0.fp_regfile_writes 487008 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127089396 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128258211 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1206144502 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15679564 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 10794532 # number of replacements +system.cpu0.commit.op_class_0::total 534790277 # Class of committed instruction +system.cpu0.commit.bw_lim_events 23063916 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1222566942 # The number of ROB reads +system.cpu0.rob.rob_writes 1247016110 # The number of ROB writes +system.cpu0.timesIdled 4124153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24979763 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 47054019698 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 455072762 # Number of Instructions Simulated +system.cpu0.committedOps 534790277 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.476617 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.476617 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.677224 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.677224 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 700310786 # number of integer regfile reads +system.cpu0.int_regfile_writes 414023994 # number of integer regfile writes +system.cpu0.fp_regfile_reads 859135 # number of floating regfile reads +system.cpu0.fp_regfile_writes 476716 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127822251 # number of cc regfile reads +system.cpu0.cc_regfile_writes 129020802 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1202374377 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15553504 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 10794591 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 308661870 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10795044 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.592924 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 308312311 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10795103 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.560386 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1667914500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 302.186929 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 209.796481 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.590209 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.409759 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 290.025597 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 221.957813 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.566456 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.433511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1362392595 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1362392595 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80965730 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 82351460 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 163317190 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67604275 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 69208699 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 136812974 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205804 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202560 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 408364 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173367 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153044 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 326411 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1817125 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1785316 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3602441 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2093741 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2052340 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4146081 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148743372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 151713203 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 300456575 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148949176 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 151915763 # number of overall hits -system.cpu0.dcache.overall_hits::total 300864939 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6366558 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6514512 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12881070 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6631964 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6534144 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13166108 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 653449 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 684365 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1337814 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 649747 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 591897 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1241644 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 332470 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 326805 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 659275 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 7 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1361016734 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1361016734 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 81465542 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 81638403 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 163103945 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 68252369 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 68428120 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 136680489 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200713 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 207163 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 407876 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 171912 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153997 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 325909 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1802432 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1798763 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3601195 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2076413 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2068312 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4144725 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 149889823 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 150220520 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 300110343 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150090536 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 150427683 # number of overall hits +system.cpu0.dcache.overall_hits::total 300518219 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6267923 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 6604970 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 12872893 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6633530 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 6545682 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 13179212 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 651993 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 686156 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1338149 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 638733 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 602965 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1241698 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 328325 # 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number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 99225424000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 198000471500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 232617199289 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 234560003141 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 467177202430 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 15059699162 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 13113954300 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 28173653462 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4294097000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4198180000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 8492277000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 82000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 238000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 320000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 346451945951 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 346899381441 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 693351327392 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 346451945951 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 346899381441 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 693351327392 # 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number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 36841 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30536 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 37557 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 29820 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45309693000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 45038920000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90348613000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40408833272 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 40500038516 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 80908871788 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10386373000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12065937500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22452310500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14266559663 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12400788300 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26667347963 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1747255500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1706730500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3453986000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 76000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 231000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 307000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99985085935 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97939746816 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 197924832751 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 110371458935 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110005684316 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 220377143251 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3393465500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2870779500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264245000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3393465500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2870779500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264245000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033347 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032797 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033069 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015025 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014517 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014768 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749949 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754197 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752107 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.784969 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.790040 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787378 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059303 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059305 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059304 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44005676000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 46542154500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90547830500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40688703147 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 39847716140 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 80536419287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10144598500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12204187000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22348785500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14171149455 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12627536592 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26798686047 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1695865500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1763125500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3458991000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 102000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 209000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 311000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 98865528602 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 99017407232 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 197882935834 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109010127102 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111221594232 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 220231721334 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3418077000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2846181000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264258000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3418077000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2846181000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264258000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033421 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033112 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014724 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014779 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753975 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.750041 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751962 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.783661 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.791897 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787638 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059090 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059762 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059426 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027835 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028304 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032576 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031710 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032139 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15558.354354 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15453.188309 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15505.750602 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36229.083866 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36833.050507 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36528.911241 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16117.997318 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18038.045883 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17095.945594 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22080.390242 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21070.676241 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21599.080521 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13706.329720 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13625.611732 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13666.325073 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12666.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 33000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23615.384615 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21392.991153 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21279.087847 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21336.476026 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20753.821587 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20867.826096 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20810.573099 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189929.227067 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181545.532157 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.022565 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92111.112619 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94012.951926 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.047182 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 16477862 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.835978 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 172394682 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16478374 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.461875 # Average number of references to valid blocks. +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028292 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028374 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028333 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032059 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032284 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032172 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15292.051279 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15781.275844 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15539.665883 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36627.781061 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36097.509754 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36363.480884 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15778.968268 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18214.497646 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17021.874869 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22307.250693 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21065.696074 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21704.490253 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13469.191546 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13852.663875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13661.965211 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 41800 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23923.076923 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21381.767256 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21282.495717 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21331.977898 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20697.825412 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20896.282918 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20797.577151 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189325.191093 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182143.926789 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.408551 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91010.384216 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95445.372233 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.240126 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 16455853 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.958473 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 172258590 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16456365 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.467597 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 12245675500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 287.122432 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 224.713546 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.560786 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.438894 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999680 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.034812 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.923660 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535224 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.464695 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 206602499 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 206602499 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 85625549 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 86769133 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 172394682 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 85625549 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 86769133 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 172394682 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 85625549 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086630 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086630 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12545.099403 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12545.099403 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12545.099403 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 135004521 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90686520 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5841333 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91602372 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 61971036 # Number of BTB hits +system.cpu1.branchPred.lookups 134713045 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90294354 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5910949 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91937142 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 61863845 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.652218 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17264827 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 189835 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 5144550 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2721808 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 2422742 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 415682 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 67.289284 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17423003 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 191945 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 5099062 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2694305 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 2404757 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 414905 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1409,100 +1408,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 920636 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 920636 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17624 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92524 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 572462 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 348174 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2542.994307 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 15098.255497 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 345444 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1949 0.56% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.12% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 137 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 118 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 24 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 58 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::720896-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 348174 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 432733 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23053.791830 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18897.650182 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16323.118118 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 333564 77.08% 77.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 89713 20.73% 97.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7384 1.71% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1176 0.27% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 238 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 198 0.05% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 173 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 170 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 52 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 27 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 432733 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 314249886000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.018496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.687233 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 313186458000 99.66% 99.66% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 582171000 0.19% 99.85% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 205657500 0.07% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 123171000 0.04% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 50673000 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 26248000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 27458500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 40663500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 6954500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 344500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 34000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 16000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 30000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::56-59 2500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 314249886000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 92524 84.00% 84.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17624 16.00% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 110148 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 920636 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 940458 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 940458 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17835 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93375 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 588116 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 352342 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2605.512542 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15403.554578 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 349554 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1910 0.54% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 467 0.13% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 147 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 145 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 66 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 352342 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 440653 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22932.098499 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18696.328712 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16830.741238 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 430922 97.79% 97.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 8564 1.94% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 599 0.14% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 434 0.10% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 89 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 36 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 440653 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 323076797592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.107209 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.744323 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 321987662592 99.66% 99.66% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 587014500 0.18% 99.84% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 213123500 0.07% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 130553500 0.04% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 52805000 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 28221000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 26598000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 43358000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6987500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 426000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 21000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 16500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 323076797592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 93376 83.96% 83.96% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17835 16.04% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 111211 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 940458 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 920636 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 110148 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 940458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 111211 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 110148 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1030784 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 111211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1051669 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 107706385 # DTB read hits -system.cpu1.dtb.read_misses 633869 # DTB read misses -system.cpu1.dtb.write_hits 83022369 # DTB write hits -system.cpu1.dtb.write_misses 286767 # DTB write misses -system.cpu1.dtb.flush_tlb 1089 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 107105213 # DTB read hits +system.cpu1.dtb.read_misses 647862 # DTB read misses +system.cpu1.dtb.write_hits 82338491 # DTB write hits +system.cpu1.dtb.write_misses 292596 # DTB write misses +system.cpu1.dtb.flush_tlb 1087 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55362 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9714 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21707 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 54922 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 184 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9726 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 57000 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 108340254 # DTB read accesses -system.cpu1.dtb.write_accesses 83309136 # DTB write accesses +system.cpu1.dtb.perms_faults 55049 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 107753075 # DTB read accesses +system.cpu1.dtb.write_accesses 82631087 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 190728754 # DTB hits -system.cpu1.dtb.misses 920636 # DTB misses -system.cpu1.dtb.accesses 191649390 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 189443704 # DTB hits +system.cpu1.dtb.misses 940458 # DTB misses +system.cpu1.dtb.accesses 190384162 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1532,408 +1520,410 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 101988 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101988 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3087 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69367 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14377 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 87611 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1414.069010 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8744.624659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 86637 98.89% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 608 0.69% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 209 0.24% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 111 0.13% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 21 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 101953 # Table walker walks requested +system.cpu1.itb.walker.walksLong 101953 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3135 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69070 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14166 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 87787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1451.501931 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 9077.444806 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 86783 98.86% 98.86% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 614 0.70% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 230 0.26% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 110 0.13% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 22 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 87611 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 86831 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28749.490389 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24437.163786 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18363.738628 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 45615 52.53% 52.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 39084 45.01% 97.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 938 1.08% 98.62% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.06% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.11% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 11 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 11 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 86831 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 606307709128 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.900370 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.299888 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 60468146000 9.97% 9.97% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 545785217128 90.02% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 47888000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 5793500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 658000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 6500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 606307709128 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 69367 95.74% 95.74% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3087 4.26% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72454 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::total 87787 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86371 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28729.370969 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24395.132531 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18742.067885 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47141 54.58% 54.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 37044 42.89% 97.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 924 1.07% 98.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 961 1.11% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 89 0.10% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 13 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86371 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 610837012424 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.919047 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.273178 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 49510897620 8.11% 8.11% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 561270328804 91.89% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 50540500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 4377500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 769000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 99000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 610837012424 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 69070 95.66% 95.66% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3135 4.34% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72205 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101988 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101988 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101953 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101953 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72454 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72454 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 174442 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 95828100 # ITB inst hits -system.cpu1.itb.inst_misses 101988 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72205 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72205 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174158 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 95706620 # ITB inst hits +system.cpu1.itb.inst_misses 101953 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1089 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1087 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40745 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21707 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 39902 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 188352 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 192638 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95930088 # ITB inst accesses -system.cpu1.itb.hits 95828100 # DTB hits -system.cpu1.itb.misses 101988 # DTB misses -system.cpu1.itb.accesses 95930088 # DTB accesses -system.cpu1.numPwrStateTransitions 16766 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8383 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 2803271183.603841 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 54004965145.463799 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3515 41.93% 41.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.84% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 1988782222956 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8383 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 27817396892849 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 23499822332151 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 668684774 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 95808573 # ITB inst accesses +system.cpu1.itb.hits 95706620 # DTB hits +system.cpu1.itb.misses 101953 # DTB misses +system.cpu1.itb.accesses 95808573 # DTB accesses +system.cpu1.numPwrStateTransitions 16900 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8450 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3209165135.406272 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 63386513065.949989 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3583 42.40% 42.40% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.38% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.04% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 1988782300428 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8450 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 24199778551817 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 27117445394183 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 673200080 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 248375133 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 600185967 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 135004521 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 81957671 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 381222161 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13317970 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2536848 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 21164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2785 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 4727264 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 160612 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 2602 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95618947 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3633834 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 39185 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 643707284 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.089618 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.340143 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 250326293 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 598056519 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 134713045 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81981153 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 383149579 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13468488 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2515216 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 21179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 3210 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 4838435 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 163101 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2842 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 95493345 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3679546 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39276 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647753829 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.079477 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.330780 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 496523035 77.13% 77.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18305041 2.84% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18509005 2.88% 82.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13552167 2.11% 84.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28450532 4.42% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9097899 1.41% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9820940 1.53% 92.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8391092 1.30% 93.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 41057573 6.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 500909169 77.33% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18369194 2.84% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18392289 2.84% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13444419 2.08% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28522776 4.40% 89.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9079206 1.40% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9809102 1.51% 92.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8415106 1.30% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 40812568 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 643707284 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.201896 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.897562 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 201561818 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 315815468 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 107257676 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13770315 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5299898 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19801436 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1379430 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 654914208 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4252969 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5299898 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 209252042 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22880216 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 253975050 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 113199216 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 39098550 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 639470628 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 86957 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2174171 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1609351 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19507965 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3945 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 611072160 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 980685418 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 753664877 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 843607 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 514110066 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 96962094 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15327241 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13321250 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76568402 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 103346770 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 87233341 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13784187 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14730689 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 606543686 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15379714 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 607376538 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 875474 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 82437591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 51624950 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 357944 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 643707284 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.943560 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.668311 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 647753829 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.200108 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.888379 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 203038997 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 318780583 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 106758002 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13823689 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5350357 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19769330 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1403755 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 652115787 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4334955 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5350357 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 210763548 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 23644830 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 256196843 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 112721527 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39074336 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 636556128 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 84527 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2214646 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1724456 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19278197 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3720 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 608321142 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 977030287 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 750414618 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 813643 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 510669806 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 97651331 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15437965 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13428690 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76999253 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 102745060 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 86542127 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13847171 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14669306 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 603448531 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15520984 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 604287606 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 888730 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 83031386 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52028805 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 367516 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647753829 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.932897 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.658052 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 406849245 63.20% 63.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 99415625 15.44% 78.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43745607 6.80% 85.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31472621 4.89% 90.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23315391 3.62% 93.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16399031 2.55% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 11324350 1.76% 98.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6634295 1.03% 99.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4551119 0.71% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 411149730 63.47% 63.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 99844018 15.41% 78.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43674585 6.74% 85.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31388880 4.85% 90.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23216755 3.58% 94.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16246972 2.51% 96.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11234988 1.73% 98.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6567238 1.01% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4430663 0.68% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 643707284 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647753829 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3079713 25.38% 25.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 23466 0.19% 25.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2047 0.02% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4953216 40.82% 66.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 4075474 33.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3092955 25.56% 25.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 25896 0.21% 25.78% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 3078 0.03% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4978648 41.15% 66.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3998858 33.05% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 65 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 411722588 67.79% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1463458 0.24% 68.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 65529 0.01% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 206 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 66963 0.01% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 109966089 18.11% 86.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 84091577 13.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 54 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 409873437 67.83% 67.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1473632 0.24% 68.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 67911 0.01% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 190 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 71982 0.01% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 109389956 18.10% 86.20% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 83410380 13.80% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 607376538 # Type of FU issued -system.cpu1.iq.rate 0.908315 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 12133916 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019978 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1870398622 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 704521244 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 584421121 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1071128 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 544645 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 476254 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 618939378 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 571011 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4788717 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 604287606 # Type of FU issued +system.cpu1.iq.rate 0.897634 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 12099435 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020023 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1868279780 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 702174546 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 581222842 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1037426 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 531508 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 461103 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 615834413 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 552574 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4729905 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16961682 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 19758 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 716289 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8689454 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 17106229 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 20767 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 716806 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8739633 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3983377 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8390309 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3947805 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8490514 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5299898 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14473954 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 6659801 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 622069689 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1729386 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 103346770 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 87233341 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13033934 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 237234 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6338314 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 716289 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2501247 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2722291 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5223538 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 600362187 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 107695161 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6106837 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5350357 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 15089845 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6765703 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 619117650 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1756443 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 102745060 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 86542127 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13138616 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 241917 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6436383 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 716806 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2534366 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2735696 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5270062 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 597242145 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 107094882 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6118047 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 146289 # number of nop insts executed -system.cpu1.iew.exec_refs 190717674 # number of memory reference insts executed -system.cpu1.iew.exec_branches 110987821 # Number of branches executed -system.cpu1.iew.exec_stores 83022513 # Number of stores executed -system.cpu1.iew.exec_rate 0.897825 # Inst execution rate -system.cpu1.iew.wb_sent 586317808 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 584897375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 289057464 # num instructions producing a value -system.cpu1.iew.wb_consumers 502211172 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.874698 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575570 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 82490328 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15021770 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4481976 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 629716363 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.856712 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.853018 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 148135 # number of nop insts executed +system.cpu1.iew.exec_refs 189434078 # number of memory reference insts executed +system.cpu1.iew.exec_branches 110489810 # Number of branches executed +system.cpu1.iew.exec_stores 82339196 # Number of stores executed +system.cpu1.iew.exec_rate 0.887169 # Inst execution rate +system.cpu1.iew.wb_sent 583107932 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 581683945 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 287154690 # num instructions producing a value +system.cpu1.iew.wb_consumers 498859903 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.864058 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575622 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 83090114 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15153468 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4526792 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 633652727 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.845792 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.838559 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 432763054 68.72% 68.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 96847267 15.38% 84.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33152549 5.26% 89.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15677479 2.49% 91.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11079326 1.76% 93.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6740057 1.07% 94.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6209892 0.99% 95.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3949846 0.63% 96.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 23296893 3.70% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 436801872 68.93% 68.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 97306167 15.36% 84.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33196725 5.24% 89.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15570610 2.46% 91.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11096620 1.75% 93.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6694600 1.06% 94.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6152090 0.97% 95.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3917687 0.62% 96.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22916356 3.62% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 629716363 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 459335316 # Number of instructions committed -system.cpu1.commit.committedOps 539485809 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 633652727 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 456128288 # Number of instructions committed +system.cpu1.commit.committedOps 535938124 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 164928975 # Number of memory references committed -system.cpu1.commit.loads 86385088 # Number of loads committed -system.cpu1.commit.membars 3716704 # Number of memory barriers committed -system.cpu1.commit.branches 102438773 # Number of branches committed -system.cpu1.commit.fp_insts 458507 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 495134645 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13388221 # Number of function calls committed. +system.cpu1.commit.refs 163441324 # Number of memory references committed +system.cpu1.commit.loads 85638830 # Number of loads committed +system.cpu1.commit.membars 3762780 # Number of memory barriers committed +system.cpu1.commit.branches 101898340 # Number of branches committed +system.cpu1.commit.fp_insts 443284 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 491997101 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13483818 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 373316618 69.20% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1132929 0.21% 69.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49236 0.01% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 58009 0.01% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 86385088 16.01% 85.44% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 78543887 14.56% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 371242424 69.27% 69.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1140857 0.21% 69.48% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50916 0.01% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 62561 0.01% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85638830 15.98% 85.48% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77802494 14.52% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 539485809 # Class of committed instruction -system.cpu1.commit.bw_lim_events 23296893 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1224452307 # The number of ROB reads -system.cpu1.rob.rob_writes 1257969342 # The number of ROB writes -system.cpu1.timesIdled 4181395 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 24977490 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 46999639814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 459335316 # Number of Instructions Simulated -system.cpu1.committedOps 539485809 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.455766 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.455766 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.686924 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.686924 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 706650375 # number of integer regfile reads -system.cpu1.int_regfile_writes 418043743 # number of integer regfile writes -system.cpu1.fp_regfile_reads 853513 # number of floating regfile reads -system.cpu1.fp_regfile_writes 519324 # number of floating regfile writes -system.cpu1.cc_regfile_reads 128705619 # number of cc regfile reads -system.cpu1.cc_regfile_writes 129852515 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1200738028 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15156718 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40297 # Transaction distribution -system.iobus.trans_dist::ReadResp 40297 # Transaction distribution +system.cpu1.commit.op_class_0::total 535938124 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22916356 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1225792229 # The number of ROB reads +system.cpu1.rob.rob_writes 1252182686 # The number of ROB writes +system.cpu1.timesIdled 4237640 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 25446251 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 54234885938 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 456128288 # Number of Instructions Simulated +system.cpu1.committedOps 535938124 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.475901 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.475901 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.677552 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.677552 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 703163553 # number of integer regfile reads +system.cpu1.int_regfile_writes 415853151 # number of integer regfile writes +system.cpu1.fp_regfile_reads 819685 # number of floating regfile reads +system.cpu1.fp_regfile_writes 527216 # number of floating regfile writes +system.cpu1.cc_regfile_reads 127646217 # number of cc regfile reads +system.cpu1.cc_regfile_writes 128772606 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1202681898 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15276931 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40295 # Transaction distribution +system.iobus.trans_dist::ReadResp 40295 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1950,11 +1940,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1969,102 +1959,102 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47815500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47814500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 346000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 345500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25701500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25714000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 40146500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 40142500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568673363 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568747115 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.425589 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115455 # number of replacements +system.iocache.tags.tagsinuse 10.425592 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089213782000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544365 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.881224 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13089208185000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544364 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.881227 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221523 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.430077 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.651599 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039641 # Number of tag accesses -system.iocache.tags.data_accesses 1039641 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039623 # Number of tag accesses +system.iocache.tags.data_accesses 1039623 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115476 # number of demand (read+write) misses -system.iocache.demand_misses::total 115516 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115474 # number of demand (read+write) misses +system.iocache.demand_misses::total 115514 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115476 # number of overall misses -system.iocache.overall_misses::total 115516 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5146000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1631213114 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1636359114 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115474 # number of overall misses +system.iocache.overall_misses::total 115514 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1644992106 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1650077606 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12815787249 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12815787249 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5497000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14447000363 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14452497363 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5497000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14447000363 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14452497363 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12805896509 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12805896509 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14450888615 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14456325115 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14450888615 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14456325115 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115476 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115516 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115474 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115514 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115476 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115516 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115474 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115514 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2078,53 +2068,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185112.700182 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184920.229856 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186718.740749 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186512.671640 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120151.009235 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120151.009235 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 137425 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125112.515695 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 137425 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125112.515695 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31781 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120058.281229 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120058.281229 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125144.089709 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125147.818576 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125144.089709 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125147.818576 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32488 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3407 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3420 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.328148 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.499415 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115476 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115516 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115474 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115514 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115476 # 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Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 452419027 # Number of tag accesses +system.l2c.tags.data_accesses 452419027 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 530836 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 183475 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 545490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 182908 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1442709 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8255712 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8255712 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 16452135 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 16452135 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 5154 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5091 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10245 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 811378 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 793383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1604761 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 8214123 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 8170809 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 16384932 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3524231 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3539730 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 7063961 # 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mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041594 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.043961 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042782 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.441504 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.390532 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.417207 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005056 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013284 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005435 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.092152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012848 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005878 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.094378 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.036182 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005056 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013284 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005435 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.092152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012848 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005878 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.094378 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.036182 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 78893.350072 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19004.014441 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19028.007793 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19015.984879 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 72000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92332.559725 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92674.455243 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 92504.000491 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76094.883362 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80750.347127 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82691.860604 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81751.288869 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20825.027872 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20919.196314 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20867.046041 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.266360 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.259869 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.263126 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005417 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006009 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005717 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.038076 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.047568 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042887 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.453026 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.390687 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.422761 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012326 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005417 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.090839 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005332 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.013295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.095347 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036211 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012326 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005417 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.090839 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005332 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.013295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.095347 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036211 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 79614.673064 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19006.364274 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19001.533742 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19003.946341 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 74000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92131.695733 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92289.048897 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 92209.119710 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76171.553698 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80764.461337 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82677.046081 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81839.627062 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20804.352231 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20903.544980 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20848.855624 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88468.255214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 88572.896818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87260.977881 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88468.255214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 88572.896818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87260.977881 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177423.826048 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176820.593774 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169041.073800 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.203929 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169639.415077 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.691796 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86046.293532 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84999.307719 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87537.545848 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 81110.850412 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3192252 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1599225 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2999 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88892.873910 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.151497 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3206101 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1605959 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3062 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54318 # Transaction distribution -system.membus.trans_dist::ReadResp 482453 # Transaction distribution +system.membus.trans_dist::ReadResp 484167 # Transaction distribution system.membus.trans_dist::WriteReq 33697 # Transaction distribution system.membus.trans_dist::WriteResp 33697 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1307113 # Transaction distribution -system.membus.trans_dist::CleanEvict 222137 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37798 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1312198 # Transaction distribution +system.membus.trans_dist::CleanEvict 224447 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37872 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 575301 # Transaction distribution -system.membus.trans_dist::ReadExResp 575301 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 428135 # Transaction distribution -system.membus.trans_dist::InvalidateReq 621651 # Transaction distribution +system.membus.trans_dist::ReadExReq 573072 # Transaction distribution +system.membus.trans_dist::ReadExResp 573072 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 429849 # Transaction distribution +system.membus.trans_dist::InvalidateReq 628542 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4001476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4131122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237676 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237676 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4368798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4014812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4144458 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4382045 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 141781676 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 141953450 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 149206762 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2813 # Total snoops (count) -system.membus.snoop_fanout::samples 1750905 # Request fanout histogram -system.membus.snoop_fanout::mean 0.020034 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.140117 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142074284 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 142246058 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7247872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7247872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149493930 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2896 # Total snoops (count) +system.membus.snoopTraffic 184832 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1757355 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019576 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.138538 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1715827 98.00% 98.00% # Request fanout histogram -system.membus.snoop_fanout::1 35078 2.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1722953 98.04% 98.04% # Request fanout histogram +system.membus.snoop_fanout::1 34402 1.96% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1750905 # Request fanout histogram -system.membus.reqLayer0.occupancy 114103000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1757355 # Request fanout histogram +system.membus.reqLayer0.occupancy 114108500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5413500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5404000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8735804910 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8771663634 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5454823379 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5453450415 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44601796 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44589202 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2787,85 +2777,86 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 55407066 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 28133350 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 5182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1867 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1867 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 55371072 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 28119352 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 4995 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 2058891 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25917963 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 2053309 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25890690 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9449679 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 16477862 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2759760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 47359 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9461280 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16455852 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2755609 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 47371 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 47372 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2180704 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2180704 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16478635 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7382055 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1266688 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1234652 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49475900 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32614875 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 885296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2587313 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 85563384 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2110504128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140051882 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2983576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8760712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3262300298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1987088 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 30865453 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.026594 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.160894 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 47384 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2180359 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2180359 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16456589 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7382467 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1266004 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1234707 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49409857 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32615082 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 883766 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2568418 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 85477123 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2107688320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140469546 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2969568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8655976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3259783410 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2003011 # Total snoops (count) +system.toL2Bus.snoopTraffic 81599088 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 30844610 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.026862 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.161680 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 30044617 97.34% 97.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 820836 2.66% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 30016066 97.31% 97.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 828544 2.69% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30865453 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 53089488175 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30844610 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 53049239176 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1406902 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1413407 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24765766555 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24732629203 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 15040405076 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 15040354777 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 512773114 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 512966184 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1495395971 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1489584962 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16437 # number of quiesce instructions executed |