diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index b739037f9..b5baf9b71 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.317219 # Nu sim_ticks 51317219225000 # Number of ticks simulated final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203116 # Simulator instruction rate (inst/s) -host_op_rate 238662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11427931870 # Simulator tick rate (ticks/s) -host_mem_usage 741344 # Number of bytes of host memory used -host_seconds 4490.51 # Real time elapsed on the host +host_inst_rate 237803 # Simulator instruction rate (inst/s) +host_op_rate 279419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13379498708 # Simulator tick rate (ticks/s) +host_mem_usage 700916 # Number of bytes of host memory used +host_seconds 3835.51 # Real time elapsed on the host sim_insts 912094204 # Number of instructions simulated sim_ops 1071714405 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -485,7 +485,7 @@ system.cpu0.dtb.flush_tlb 1081 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55450 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 55386 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 9899 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -592,7 +592,7 @@ system.cpu0.itb.flush_tlb 1081 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40899 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 40835 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1491,7 +1491,7 @@ system.cpu1.dtb.flush_tlb 1089 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55426 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 55362 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 9714 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1603,7 +1603,7 @@ system.cpu1.itb.flush_tlb 1089 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40809 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 40745 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |