diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 272c6e9a4..e35d19105 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.821000 # Nu sim_ticks 51820999867500 # Number of ticks simulated final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1076689 # Simulator instruction rate (inst/s) -host_op_rate 1265246 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62402323103 # Simulator tick rate (ticks/s) -host_mem_usage 722120 # Number of bytes of host memory used -host_seconds 830.43 # Real time elapsed on the host +host_inst_rate 622691 # Simulator instruction rate (inst/s) +host_op_rate 731741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36089691928 # Simulator tick rate (ticks/s) +host_mem_usage 680680 # Number of bytes of host memory used +host_seconds 1435.89 # Real time elapsed on the host sim_insts 894119248 # Number of instructions simulated sim_ops 1050702892 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -457,7 +457,7 @@ system.cpu0.dtb.flush_tlb 51828 # Nu system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 73288 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 73224 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 4644 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -543,7 +543,7 @@ system.cpu0.itb.flush_tlb 51828 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 53811 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 53747 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1158,7 +1158,7 @@ system.cpu1.dtb.flush_tlb 51822 # Nu system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 74029 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 73965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 4498 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -1250,7 +1250,7 @@ system.cpu1.itb.flush_tlb 51822 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 53985 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 53921 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |