diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | 3032 |
1 files changed, 1637 insertions, 1395 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 549c3e2c6..b93c1aabd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.781932 # Number of seconds simulated -sim_ticks 51781931516000 # Number of ticks simulated -final_tick 51781931516000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.861398 # Number of seconds simulated +sim_ticks 51861397612000 # Number of ticks simulated +final_tick 51861397612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 513884 # Simulator instruction rate (inst/s) -host_op_rate 603881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31103019215 # Simulator tick rate (ticks/s) -host_mem_usage 672564 # Number of bytes of host memory used -host_seconds 1664.85 # Real time elapsed on the host -sim_insts 855540358 # Number of instructions simulated -sim_ops 1005371984 # Number of ops (including micro ops) simulated +host_inst_rate 682840 # Simulator instruction rate (inst/s) +host_op_rate 802417 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40752483757 # Simulator tick rate (ticks/s) +host_mem_usage 728928 # Number of bytes of host memory used +host_seconds 1272.59 # Real time elapsed on the host +sim_insts 868978236 # Number of instructions simulated +sim_ops 1021151568 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 107200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 102528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2434152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20994800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 96832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 103680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2545804 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 20458904 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 379200 # Number of bytes read from this memory -system.physmem.bytes_read::total 47223100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2434152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2545804 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4979956 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68447104 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 110912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 113344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2519016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 22396080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 118144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 113984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2612108 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 22226264 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 390656 # Number of bytes read from this memory +system.physmem.bytes_read::total 50600508 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2519016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2612108 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5131124 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71823424 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 68467684 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1602 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 65448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 328047 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1513 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1620 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 52771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 319680 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 5925 # Number of read requests responded to by this memory -system.physmem.num_reads::total 778281 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1069486 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 71844004 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 66774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 349942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 53807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 347295 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6104 # Number of read requests responded to by this memory +system.physmem.num_reads::total 831053 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1122241 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1072059 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 47008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 405446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 395097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 911961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 47008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 96172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1321834 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1124814 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 48572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 431845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 428570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 975687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 48572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 98939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1384911 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1322231 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1321834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 47008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 405447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 395495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2234192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 778281 # Number of read requests accepted -system.physmem.writeReqs 1672780 # Number of write requests accepted -system.physmem.readBursts 778281 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1672780 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49778368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31616 # Total number of bytes read from write queue -system.physmem.bytesWritten 106609920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 47223100 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 106913828 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 494 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6998 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 34417 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 49121 # Per bank write bursts -system.physmem.perBankRdBursts::1 48968 # Per bank write bursts -system.physmem.perBankRdBursts::2 43998 # Per bank write bursts -system.physmem.perBankRdBursts::3 44044 # Per bank write bursts -system.physmem.perBankRdBursts::4 46923 # Per bank write bursts -system.physmem.perBankRdBursts::5 50978 # Per bank write bursts -system.physmem.perBankRdBursts::6 43709 # Per bank write bursts -system.physmem.perBankRdBursts::7 43367 # Per bank write bursts -system.physmem.perBankRdBursts::8 43043 # Per bank write bursts -system.physmem.perBankRdBursts::9 89491 # Per bank write bursts -system.physmem.perBankRdBursts::10 47224 # Per bank write bursts -system.physmem.perBankRdBursts::11 49584 # Per bank write bursts -system.physmem.perBankRdBursts::12 42821 # Per bank write bursts -system.physmem.perBankRdBursts::13 45810 # Per bank write bursts -system.physmem.perBankRdBursts::14 42383 # Per bank write bursts -system.physmem.perBankRdBursts::15 46323 # Per bank write bursts -system.physmem.perBankWrBursts::0 104557 # Per bank write bursts -system.physmem.perBankWrBursts::1 105414 # Per bank write bursts -system.physmem.perBankWrBursts::2 105583 # Per bank write bursts -system.physmem.perBankWrBursts::3 103819 # Per bank write bursts -system.physmem.perBankWrBursts::4 104348 # Per bank write bursts -system.physmem.perBankWrBursts::5 108141 # Per bank write bursts -system.physmem.perBankWrBursts::6 101114 # Per bank write bursts -system.physmem.perBankWrBursts::7 100245 # Per bank write bursts -system.physmem.perBankWrBursts::8 99850 # Per bank write bursts -system.physmem.perBankWrBursts::9 106510 # Per bank write bursts -system.physmem.perBankWrBursts::10 102540 # Per bank write bursts -system.physmem.perBankWrBursts::11 107777 # Per bank write bursts -system.physmem.perBankWrBursts::12 103459 # Per bank write bursts -system.physmem.perBankWrBursts::13 105336 # Per bank write bursts -system.physmem.perBankWrBursts::14 101779 # Per bank write bursts -system.physmem.perBankWrBursts::15 105308 # Per bank write bursts +system.physmem.bw_write::total 1385308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1384911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 48572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 431845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 428967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2360995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 831053 # Number of read requests accepted +system.physmem.writeReqs 1733697 # Number of write requests accepted +system.physmem.readBursts 831053 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1733697 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 53155264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 32128 # Total number of bytes read from write queue +system.physmem.bytesWritten 110517504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 50600508 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 110812516 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 502 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6857 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35215 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 52772 # Per bank write bursts +system.physmem.perBankRdBursts::1 58055 # Per bank write bursts +system.physmem.perBankRdBursts::2 48746 # Per bank write bursts +system.physmem.perBankRdBursts::3 51625 # Per bank write bursts +system.physmem.perBankRdBursts::4 50901 # Per bank write bursts +system.physmem.perBankRdBursts::5 53731 # Per bank write bursts +system.physmem.perBankRdBursts::6 47545 # Per bank write bursts +system.physmem.perBankRdBursts::7 46576 # Per bank write bursts +system.physmem.perBankRdBursts::8 47759 # Per bank write bursts +system.physmem.perBankRdBursts::9 90120 # Per bank write bursts +system.physmem.perBankRdBursts::10 47452 # Per bank write bursts +system.physmem.perBankRdBursts::11 51057 # Per bank write bursts +system.physmem.perBankRdBursts::12 47939 # Per bank write bursts +system.physmem.perBankRdBursts::13 45720 # Per bank write bursts +system.physmem.perBankRdBursts::14 43868 # Per bank write bursts +system.physmem.perBankRdBursts::15 46685 # Per bank write bursts +system.physmem.perBankWrBursts::0 110572 # Per bank write bursts +system.physmem.perBankWrBursts::1 116599 # Per bank write bursts +system.physmem.perBankWrBursts::2 110707 # Per bank write bursts +system.physmem.perBankWrBursts::3 112437 # Per bank write bursts +system.physmem.perBankWrBursts::4 109828 # Per bank write bursts +system.physmem.perBankWrBursts::5 113045 # Per bank write bursts +system.physmem.perBankWrBursts::6 105073 # Per bank write bursts +system.physmem.perBankWrBursts::7 102356 # Per bank write bursts +system.physmem.perBankWrBursts::8 103784 # Per bank write bursts +system.physmem.perBankWrBursts::9 107644 # Per bank write bursts +system.physmem.perBankWrBursts::10 104570 # Per bank write bursts +system.physmem.perBankWrBursts::11 108123 # Per bank write bursts +system.physmem.perBankWrBursts::12 106842 # Per bank write bursts +system.physmem.perBankWrBursts::13 106503 # Per bank write bursts +system.physmem.perBankWrBursts::14 103411 # Per bank write bursts +system.physmem.perBankWrBursts::15 105342 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 51781928959500 # Total gap between requests +system.physmem.totGap 51861395055500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 735165 # Read request sizes (log2) +system.physmem.readPktSize::6 787937 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1670207 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 745946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 26414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 204 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1731124 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 797504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 46 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -165,178 +165,207 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 55685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 67964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 89945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 92025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 95463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 110001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 113998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 99922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 100596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 98621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 96222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 93100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 89862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 88090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 83497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 82653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 82465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 81037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 531423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.281520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.194093 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.137010 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 219913 41.38% 41.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 131435 24.73% 66.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44338 8.34% 74.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23886 4.49% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15966 3.00% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10709 2.02% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7995 1.50% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7287 1.37% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 69894 13.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 531423 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 80476 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 9.664621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 89.984802 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 80471 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 57139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 70145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 93845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 95924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 98521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 113672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 117695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 104272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 102286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 99994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 96711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 93700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 91898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 87418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 86273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 85861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 84522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 799 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 563789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 290.307984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.321614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.078407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 235457 41.76% 41.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 139953 24.82% 66.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 46694 8.28% 74.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25357 4.50% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16838 2.99% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11479 2.04% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8496 1.51% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7843 1.39% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71672 12.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 563789 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 84234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 9.859653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 88.079162 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 84229 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::5120-6143 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 80476 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 80476 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.699090 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.496721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.527834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 200 0.25% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 177 0.22% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 72247 89.77% 90.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 4200 5.22% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1327 1.65% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 446 0.55% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 582 0.72% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 137 0.17% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 223 0.28% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 119 0.15% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 159 0.20% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 60 0.07% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 172 0.21% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 43 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 70 0.09% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 53 0.07% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 161 0.20% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 11 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 23 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 15 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 80476 # Writes before turning the bus around for reads -system.physmem.totQLat 9983720499 # Total ticks spent queuing -system.physmem.totMemAccLat 24567226749 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3888935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12836.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 84234 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 84234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.500463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.372295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.059087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 108 0.13% 0.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 80 0.09% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 54 0.06% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 121 0.14% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 46153 54.79% 55.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 30225 35.88% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2462 2.92% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1364 1.62% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 933 1.11% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 416 0.49% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 269 0.32% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 164 0.19% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 538 0.64% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 68 0.08% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 77 0.09% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 53 0.06% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 0.19% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 54 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 29 0.03% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 79 0.09% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 145 0.17% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 43 0.05% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 17 0.02% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 33 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 176 0.21% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 15 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 19 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 61 0.07% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 20 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 40 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 24 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 103 0.12% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 13 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 10 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 9 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 10 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 84234 # Writes before turning the bus around for reads +system.physmem.totQLat 10578626250 # Total ticks spent queuing +system.physmem.totMemAccLat 26151457500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4152755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12736.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31586.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31486.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.17 # Average write queue length when enqueuing -system.physmem.readRowHits 580589 # Number of row buffer hits during reads -system.physmem.writeRowHits 1331554 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes -system.physmem.avgGap 21126332.21 # Average gap between requests -system.physmem.pageHitRate 78.25 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49696712332000 # Time in different power states -system.physmem.memoryStateTime::REF 1729112320000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 356106481500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2031447600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 1986110280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1108428750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1083691125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2894642400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3172057200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5399272080 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5394982320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3382143697920 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3382143697920 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1286313063165 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1285469654400 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29940811051500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29941550883750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34620701603415 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34620801076995 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.586590 # Core power per rank (mW) -system.physmem.averagePower::1 668.588511 # Core power per rank (mW) +system.physmem.avgWrQLen 12.05 # Average write queue length when enqueuing +system.physmem.readRowHits 620179 # Number of row buffer hits during reads +system.physmem.writeRowHits 1373418 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.53 # Row buffer hit rate for writes +system.physmem.avgGap 20220838.31 # Average gap between requests +system.physmem.pageHitRate 77.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2224749240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1213900875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3197578800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5706398160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3387334061280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1303736226660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29973207455250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34676620370265 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.640359 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49862520204500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1731765880000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 267111145000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2037495600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1111728750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3280680000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5483499120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3387334061280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1287848520900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29987144039250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34674240024900 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.594461 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49885777301500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1731765880000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243849706000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -360,6 +389,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -381,27 +418,76 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 125209 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 125209 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 19669 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90325 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 125193 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 125193 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 125193 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 110010 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22089.371421 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18317.414501 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13164.465309 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 107059 97.32% 97.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2114 1.92% 99.24% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 606 0.55% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 110 0.10% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 25 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 28 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 110010 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 3295703864 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.071233 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -234762296 -7.12% -7.12% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 3530466160 107.12% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 3295703864 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90326 82.12% 82.12% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 19669 17.88% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 109995 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125209 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125209 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109995 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109995 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 235204 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 80391901 # DTB read hits -system.cpu0.dtb.read_misses 93388 # DTB read misses -system.cpu0.dtb.write_hits 73043030 # DTB write hits -system.cpu0.dtb.write_misses 28813 # DTB write misses -system.cpu0.dtb.flush_tlb 51784 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 81853035 # DTB read hits +system.cpu0.dtb.read_misses 95759 # DTB read misses +system.cpu0.dtb.write_hits 74321037 # DTB write hits +system.cpu0.dtb.write_misses 29450 # DTB write misses +system.cpu0.dtb.flush_tlb 51862 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 20238 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 70641 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 20132 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 528 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 71205 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4105 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4306 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9619 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 80485289 # DTB read accesses -system.cpu0.dtb.write_accesses 73071843 # DTB write accesses +system.cpu0.dtb.perms_faults 9531 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81948794 # DTB read accesses +system.cpu0.dtb.write_accesses 74350487 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 153434931 # DTB hits -system.cpu0.dtb.misses 122201 # DTB misses -system.cpu0.dtb.accesses 153557132 # DTB accesses +system.cpu0.dtb.hits 156174072 # DTB hits +system.cpu0.dtb.misses 125209 # DTB misses +system.cpu0.dtb.accesses 156299281 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -423,242 +509,284 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 427471663 # ITB inst hits -system.cpu0.itb.inst_misses 76376 # ITB inst misses +system.cpu0.itb.walker.walks 77027 # Table walker walks requested +system.cpu0.itb.walker.walksLong 77027 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4349 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67368 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 77027 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 77027 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 77027 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 71717 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25312.366663 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21958.347721 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 14763.140629 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 66172 92.27% 92.27% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 4523 6.31% 98.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 706 0.98% 99.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 175 0.24% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 37 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 34 0.05% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 34 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 71717 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -294463796 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -294463796 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -294463796 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 67368 93.94% 93.94% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4349 6.06% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 71717 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 77027 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 77027 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71717 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71717 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 148744 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 434570813 # ITB inst hits +system.cpu0.itb.inst_misses 77027 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51784 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51862 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 20238 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 52019 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 20132 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 528 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 52030 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 427548039 # ITB inst accesses -system.cpu0.itb.hits 427471663 # DTB hits -system.cpu0.itb.misses 76376 # DTB misses -system.cpu0.itb.accesses 427548039 # DTB accesses -system.cpu0.numCycles 51782412762 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 434647840 # ITB inst accesses +system.cpu0.itb.hits 434570813 # DTB hits +system.cpu0.itb.misses 77027 # DTB misses +system.cpu0.itb.accesses 434647840 # DTB accesses +system.cpu0.numCycles 51862348340 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 427217866 # Number of instructions committed -system.cpu0.committedOps 502133426 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 461356318 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 442453 # Number of float alu accesses -system.cpu0.num_func_calls 25480565 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64997329 # number of instructions that are conditional controls -system.cpu0.num_int_insts 461356318 # number of integer instructions -system.cpu0.num_fp_insts 442453 # number of float instructions -system.cpu0.num_int_register_reads 669433821 # number of times the integer registers were read -system.cpu0.num_int_register_writes 365789159 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 711452 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 379824 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 111391626 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 111077654 # number of times the CC registers were written -system.cpu0.num_mem_refs 153423964 # number of memory refs -system.cpu0.num_load_insts 80387324 # Number of load instructions -system.cpu0.num_store_insts 73036640 # Number of store instructions -system.cpu0.num_idle_cycles 50249111943.842865 # Number of idle cycles -system.cpu0.num_busy_cycles 1533300818.157139 # Number of busy cycles -system.cpu0.not_idle_fraction 0.029610 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.970390 # Percentage of idle cycles -system.cpu0.Branches 95379703 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 347836061 69.23% 69.23% # Class of executed instruction -system.cpu0.op_class::IntMult 1052847 0.21% 69.44% # Class of executed instruction -system.cpu0.op_class::IntDiv 47944 0.01% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 6 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 5 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 9 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 55653 0.01% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::MemRead 80387324 16.00% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 73036640 14.54% 100.00% # Class of executed instruction +system.cpu0.committedInsts 434316413 # Number of instructions committed +system.cpu0.committedOps 510251172 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 468762245 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 455279 # Number of float alu accesses +system.cpu0.num_func_calls 25833192 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 66107864 # number of instructions that are conditional controls +system.cpu0.num_int_insts 468762245 # number of integer instructions +system.cpu0.num_fp_insts 455279 # number of float instructions +system.cpu0.num_int_register_reads 680505745 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371520195 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 735714 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 382992 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113236512 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 112912982 # number of times the CC registers were written +system.cpu0.num_mem_refs 156164016 # number of memory refs +system.cpu0.num_load_insts 81849666 # Number of load instructions +system.cpu0.num_store_insts 74314350 # Number of store instructions +system.cpu0.num_idle_cycles 50300563806.190483 # Number of idle cycles +system.cpu0.num_busy_cycles 1561784533.809517 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030114 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969886 # Percentage of idle cycles +system.cpu0.Branches 96959859 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 353181248 69.18% 69.18% # Class of executed instruction +system.cpu0.op_class::IntMult 1084077 0.21% 69.39% # Class of executed instruction +system.cpu0.op_class::IntDiv 49491 0.01% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 6 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 8 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 12 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 55978 0.01% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu0.op_class::MemRead 81849666 16.03% 85.44% # Class of executed instruction +system.cpu0.op_class::MemWrite 74314350 14.56% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 502416489 # Class of executed instruction +system.cpu0.op_class::total 510534837 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16160 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 9666641 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.969685 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 297154926 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9667153 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.738618 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 16221 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 9866178 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.969728 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 301750178 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9866690 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.582716 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 3092948250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 283.466253 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 228.503431 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.553645 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.446296 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 290.086465 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 221.883263 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.566575 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.433366 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1237347722 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1237347722 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75260834 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 75246301 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 150507135 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69349664 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 69346777 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 138696441 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190562 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191577 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 382139 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171619 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 160816 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 332435 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1711920 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1739353 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3451273 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1857030 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1885244 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3742274 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 144610498 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 144593078 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 289203576 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 144801060 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 144784655 # number of overall hits -system.cpu0.dcache.overall_hits::total 289585715 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2479823 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2539735 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 5019558 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1027548 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1051512 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2079060 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 586953 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 604316 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1191269 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 612872 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 613029 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1225901 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145963 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 146688 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 292651 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1256728908 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1256728908 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 76588751 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 76163346 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 152752097 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 70555546 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 70327464 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 140883010 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190561 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 196148 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 386709 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 172423 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 161036 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 333459 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1750003 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1777885 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3527888 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1897893 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1924897 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3822790 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 147144297 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 146490810 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 293635107 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147334858 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 146686958 # number of overall hits +system.cpu0.dcache.overall_hits::total 294021816 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2557843 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2571612 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 5129455 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1050273 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1078042 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2128315 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 601274 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 625393 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1226667 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 620770 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 607819 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1228589 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148787 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 147781 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 296568 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3507371 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 3591247 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7098618 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4094324 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 4195563 # number of overall misses -system.cpu0.dcache.overall_misses::total 8289887 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38409075253 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 39279047002 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 77688122255 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27659575882 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 27687644531 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 55347220413 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 13571753508 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13540403000 # 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mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060022 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058193 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059101 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023586 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024141 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023864 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028067 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027736 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13394.918697 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13394.866508 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13394.892286 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24765.081360 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24231.470524 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24495.276732 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15205.350384 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14475.269232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14835.001560 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20144.515481 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20087.703844 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20116.106025 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12043.832219 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12110.444407 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12077.162836 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16706.170665 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16546.772122 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16625.525428 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16490.328154 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16247.490009 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16367.421162 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023843 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024214 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024028 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027685 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028224 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027954 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13410.508275 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13497.816624 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13454.282609 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25707.961856 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24993.058039 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25345.926006 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14876.429802 # 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average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 48749.500000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16968.705506 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16871.714483 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16919.934166 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16668.928151 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16555.340246 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16611.696325 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # 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mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015777 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015710 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.015744 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11382.722942 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11409.278707 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11395.990199 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11382.722942 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11409.278707 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11395.990199 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11382.722942 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11409.278707 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11395.990199 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015807 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015883 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015845 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015807 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015883 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015845 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015807 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015883 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015845 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11388.745063 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11408.881139 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11398.841529 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11388.745063 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11408.881139 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11398.841529 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11388.745063 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11408.881139 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11398.841529 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -925,6 +1057,14 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -946,27 +1086,81 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 127972 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 127972 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 19780 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92740 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 127956 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.265716 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 71.272998 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 127954 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 127956 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 112536 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22019.187193 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18129.081838 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13444.450617 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 109487 97.29% 97.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2144 1.91% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 659 0.59% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 117 0.10% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 32 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 27 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 112536 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 6637919892 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.174468 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1158102796 -17.45% -17.45% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 7796022688 117.45% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 6637919892 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92740 82.42% 82.42% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 19780 17.58% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 112520 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 127972 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 127972 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 112520 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 112520 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 240492 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80485889 # DTB read hits -system.cpu1.dtb.read_misses 94650 # DTB read misses -system.cpu1.dtb.write_hits 73083689 # DTB write hits -system.cpu1.dtb.write_misses 28922 # DTB write misses -system.cpu1.dtb.flush_tlb 51788 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 81500118 # DTB read hits +system.cpu1.dtb.read_misses 97955 # DTB read misses +system.cpu1.dtb.write_hits 74126007 # DTB write hits +system.cpu1.dtb.write_misses 30017 # DTB write misses +system.cpu1.dtb.flush_tlb 51868 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 19698 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 69957 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 20724 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 72099 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4240 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4473 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9564 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80580539 # DTB read accesses -system.cpu1.dtb.write_accesses 73112611 # DTB write accesses +system.cpu1.dtb.perms_faults 9907 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 81598073 # DTB read accesses +system.cpu1.dtb.write_accesses 74156024 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 153569578 # DTB hits -system.cpu1.dtb.misses 123572 # DTB misses -system.cpu1.dtb.accesses 153693150 # DTB accesses +system.cpu1.dtb.hits 155626125 # DTB hits +system.cpu1.dtb.misses 127972 # DTB misses +system.cpu1.dtb.accesses 155754097 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -988,91 +1182,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 428597912 # ITB inst hits -system.cpu1.itb.inst_misses 76336 # ITB inst misses +system.cpu1.itb.walker.walks 77421 # Table walker walks requested +system.cpu1.itb.walker.walksLong 77421 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4271 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67596 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 77421 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 77421 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 77421 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71867 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24990.746796 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21538.641816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14943.355403 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 66410 92.41% 92.41% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 4449 6.19% 98.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 690 0.96% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 184 0.26% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 29 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 30 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 19 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71867 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1257793296 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1257793296 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1257793296 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 67596 94.06% 94.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4271 5.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71867 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71867 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71867 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 149288 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 434944325 # ITB inst hits +system.cpu1.itb.inst_misses 77421 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51788 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51868 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 19698 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 51781 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 20724 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 53256 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 428674248 # ITB inst accesses -system.cpu1.itb.hits 428597912 # DTB hits -system.cpu1.itb.misses 76336 # DTB misses -system.cpu1.itb.accesses 428674248 # DTB accesses -system.cpu1.numCycles 51781450270 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 435021746 # ITB inst accesses +system.cpu1.itb.hits 434944325 # DTB hits +system.cpu1.itb.misses 77421 # DTB misses +system.cpu1.itb.accesses 435021746 # DTB accesses +system.cpu1.numCycles 51860446884 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 428322492 # Number of instructions committed -system.cpu1.committedOps 503238558 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 462373470 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 457847 # Number of float alu accesses -system.cpu1.num_func_calls 25589000 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 65138542 # number of instructions that are conditional controls -system.cpu1.num_int_insts 462373470 # number of integer instructions -system.cpu1.num_fp_insts 457847 # number of float instructions -system.cpu1.num_int_register_reads 672243876 # number of times the integer registers were read -system.cpu1.num_int_register_writes 366665103 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 741025 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 381476 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 111687570 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 111401234 # number of times the CC registers were written -system.cpu1.num_mem_refs 153562143 # number of memory refs -system.cpu1.num_load_insts 80482788 # Number of load instructions -system.cpu1.num_store_insts 73079355 # Number of store instructions -system.cpu1.num_idle_cycles 50246687172.676186 # Number of idle cycles -system.cpu1.num_busy_cycles 1534763097.323812 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029639 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970361 # Percentage of idle cycles -system.cpu1.Branches 95580848 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 348749586 69.26% 69.26% # Class of executed instruction -system.cpu1.op_class::IntMult 1110324 0.22% 69.48% # Class of executed instruction -system.cpu1.op_class::IntDiv 49704 0.01% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 2 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 8 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 12 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 56056 0.01% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::MemRead 80482788 15.98% 85.49% # Class of executed instruction -system.cpu1.op_class::MemWrite 73079355 14.51% 100.00% # Class of executed instruction +system.cpu1.committedInsts 434661823 # Number of instructions committed +system.cpu1.committedOps 510900396 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 469262912 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 444776 # Number of float alu accesses +system.cpu1.num_func_calls 25944068 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66238146 # number of instructions that are conditional controls +system.cpu1.num_int_insts 469262912 # number of integer instructions +system.cpu1.num_fp_insts 444776 # number of float instructions +system.cpu1.num_int_register_reads 683773696 # number of times the integer registers were read +system.cpu1.num_int_register_writes 372368162 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 716331 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 377944 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113908068 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113630972 # number of times the CC registers were written +system.cpu1.num_mem_refs 155618629 # number of memory refs +system.cpu1.num_load_insts 81496317 # Number of load instructions +system.cpu1.num_store_insts 74122312 # Number of store instructions +system.cpu1.num_idle_cycles 50297346072.144875 # Number of idle cycles +system.cpu1.num_busy_cycles 1563100811.855124 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030141 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969859 # Percentage of idle cycles +system.cpu1.Branches 97056682 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 354376144 69.32% 69.32% # Class of executed instruction +system.cpu1.op_class::IntMult 1097996 0.21% 69.54% # Class of executed instruction +system.cpu1.op_class::IntDiv 48675 0.01% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 2 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 5 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 9 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 55297 0.01% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::MemRead 81496317 15.94% 85.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 74122312 14.50% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 503527836 # Class of executed instruction +system.cpu1.op_class::total 511196757 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40424 # Transaction distribution -system.iobus.trans_dist::ReadResp 40424 # Transaction distribution +system.iobus.trans_dist::ReadReq 40404 # Transaction distribution +system.iobus.trans_dist::ReadResp 40404 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1092,11 +1326,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354314 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1113,11 +1347,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7493014 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1146,71 +1380,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042410724 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042408857 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179081273 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179045538 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115504 # number of replacements -system.iocache.tags.tagsinuse 10.454717 # Cycle average of tags in use +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.461673 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115520 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13154373196000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.509635 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.945082 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219352 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434068 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653420 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13154364038000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.508099 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.953575 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219256 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434598 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653855 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040055 # Number of tag accesses -system.iocache.tags.data_accesses 1040055 # Number of data accesses +system.iocache.tags.tag_accesses 1039875 # Number of tag accesses +system.iocache.tags.data_accesses 1039875 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8858 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8895 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8858 # number of demand (read+write) misses -system.iocache.demand_misses::total 8898 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses +system.iocache.demand_misses::total 8878 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8858 # number of overall misses -system.iocache.overall_misses::total 8898 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1913667012 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1919146012 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8838 # number of overall misses +system.iocache.overall_misses::total 8878 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1903038512 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1908523512 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28832566439 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28832566439 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1913667012 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1919485012 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1913667012 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1919485012 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28811758807 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28811758807 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1903038512 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1908862512 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1903038512 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1908862512 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8858 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8895 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8858 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8898 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8858 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8898 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1224,55 +1458,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 216038.271845 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 215755.594379 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 215324.565739 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 215044.902761 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270312.068167 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270312.068167 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 216038.271845 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 215720.949876 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 216038.271845 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 215720.949876 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223529 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270116.991740 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270116.991740 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 215324.565739 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 215010.420365 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 215324.565739 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 215010.420365 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 222004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27514 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27403 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.124191 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.101449 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61631.926724 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62011.141139 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61674.155916 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62097.232927 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62053.720068 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.218133 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.206101 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.212038 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010658 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.081762 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007885 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.010840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005783 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.079958 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033735 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010658 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.081762 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007885 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.010840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005783 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.079958 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033735 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63348.777770 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63438.076824 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63067.648467 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 21579.704516 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 21598.571767 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21588.947374 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.762387 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.754287 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.761269 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61075.907990 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60985.278209 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61031.289289 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61909.009377 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61919.698834 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61930.149616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61909.009377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61919.698834 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61930.149616 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1755,57 +1997,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 417721 # Transaction distribution -system.membus.trans_dist::ReadResp 417721 # Transaction distribution -system.membus.trans_dist::WriteReq 33871 # Transaction distribution -system.membus.trans_dist::WriteResp 33871 # Transaction distribution -system.membus.trans_dist::Writeback 1069486 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 600721 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 600721 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34423 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34424 # Transaction distribution -system.membus.trans_dist::ReadExReq 397977 # Transaction distribution -system.membus.trans_dist::ReadExResp 397977 # Transaction distribution +system.membus.trans_dist::ReadReq 431429 # Transaction distribution +system.membus.trans_dist::ReadResp 431429 # Transaction distribution +system.membus.trans_dist::WriteReq 33873 # Transaction distribution +system.membus.trans_dist::WriteResp 33873 # Transaction distribution +system.membus.trans_dist::Writeback 1122241 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 608883 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 608883 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35220 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35222 # Transaction distribution +system.membus.trans_dist::ReadExReq 436846 # Transaction distribution +system.membus.trans_dist::ReadExResp 436846 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3570318 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3700502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 334782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4035284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3746179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3876375 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 334941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4211316 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 140106848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 140277172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14030080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14030080 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 154307252 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3630 # Total snoops (count) -system.membus.snoop_fanout::samples 2443419 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147371488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 147541836 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14041536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14041536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 161583372 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3431 # Total snoops (count) +system.membus.snoop_fanout::samples 2557707 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2443419 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2557707 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2443419 # Request fanout histogram -system.membus.reqLayer0.occupancy 107392500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2557707 # Request fanout histogram +system.membus.reqLayer0.occupancy 107352000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5575997 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5560499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16318205493 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 16960886493 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7697194309 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8211852015 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186789727 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186625462 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1849,55 +2091,55 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 21137473 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21129474 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33871 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33871 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7479557 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1332565 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1225901 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43231 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43232 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2014651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2014651 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27041508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27036574 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 774452 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1144323 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 55996857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 862740756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1097639072 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2601008 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3569856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 1966550692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 492520 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 31930568 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003619 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.060051 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 21612149 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21604161 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33873 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33873 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7621991 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1335253 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1228589 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 44226 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44228 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2062852 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2062852 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27641812 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27580079 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 784917 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1183820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 57190628 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 881950484 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1119524728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2643752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3719680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2007838644 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 494311 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 32599559 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003544 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.059428 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 31815006 99.64% 99.64% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115562 0.36% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 32484017 99.65% 99.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 31930568 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 50801737999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 32599559 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 51716744749 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 4033500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 3993000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 60715950506 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 62067119757 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 38798201181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 39696027226 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 449711000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 454863250 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 698488000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 719296500 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |