diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | 3137 |
1 files changed, 1564 insertions, 1573 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index c78f46d36..61bf9a286 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.771790 # Number of seconds simulated -sim_ticks 51771790334500 # Number of ticks simulated -final_tick 51771790334500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.771755 # Number of seconds simulated +sim_ticks 51771755296500 # Number of ticks simulated +final_tick 51771755296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 629815 # Simulator instruction rate (inst/s) -host_op_rate 740156 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39468336741 # Simulator tick rate (ticks/s) -host_mem_usage 677148 # Number of bytes of host memory used -host_seconds 1311.73 # Real time elapsed on the host -sim_insts 826146401 # Number of instructions simulated -sim_ops 970885096 # Number of ops (including micro ops) simulated +host_inst_rate 629134 # Simulator instruction rate (inst/s) +host_op_rate 739361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39432920775 # Simulator tick rate (ticks/s) +host_mem_usage 676920 # Number of bytes of host memory used +host_seconds 1312.91 # Real time elapsed on the host +sim_insts 825994487 # Number of instructions simulated +sim_ops 970712321 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 64192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 68416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2225432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 31926704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 62336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 66048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2388572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 32205016 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 391616 # Number of bytes read from this memory -system.physmem.bytes_read::total 69398332 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2225432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2388572 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4614004 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 60462464 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 69120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 72384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2314776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 32049840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 60480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 66688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2364572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 32106392 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 391424 # Number of bytes read from this memory +system.physmem.bytes_read::total 69495676 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2314776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2364572 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4679348 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 60509440 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 15860 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4720 # Number of bytes written to this memory -system.physmem.bytes_written::total 60483044 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 55433 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 498858 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 974 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 57068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 503213 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1124769 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 944726 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 60530020 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 56829 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 500782 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1042 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 501672 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6116 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1126290 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 945460 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1983 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 590 # Number of write requests responded to by this memory -system.physmem.num_writes::total 947299 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 42985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 616681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 46137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 622057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1340466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 42985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 46137 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1167865 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 948033 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 44711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 619060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 620153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1342347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 44711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90384 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1168773 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1168263 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1167865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 42985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 616988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 46137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 622148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2508729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1124769 # Number of read requests accepted -system.physmem.writeReqs 947299 # Number of write requests accepted -system.physmem.readBursts 1124769 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 947299 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 71946624 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 38592 # Total number of bytes read from write queue -system.physmem.bytesWritten 60482240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 69398332 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 60483044 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 603 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1169171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1168773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 44711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 619367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 620244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2511518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1126290 # Number of read requests accepted +system.physmem.writeReqs 948033 # Number of write requests accepted +system.physmem.readBursts 1126290 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 948033 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72036608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 45952 # Total number of bytes read from write queue +system.physmem.bytesWritten 60529408 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69495676 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 60530020 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 718 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 292556 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71523 # Per bank write bursts -system.physmem.perBankRdBursts::1 69926 # Per bank write bursts -system.physmem.perBankRdBursts::2 70289 # Per bank write bursts -system.physmem.perBankRdBursts::3 64893 # Per bank write bursts -system.physmem.perBankRdBursts::4 64804 # Per bank write bursts -system.physmem.perBankRdBursts::5 73543 # Per bank write bursts -system.physmem.perBankRdBursts::6 62283 # Per bank write bursts -system.physmem.perBankRdBursts::7 61053 # Per bank write bursts -system.physmem.perBankRdBursts::8 62184 # Per bank write bursts -system.physmem.perBankRdBursts::9 109202 # Per bank write bursts -system.physmem.perBankRdBursts::10 70171 # Per bank write bursts -system.physmem.perBankRdBursts::11 67486 # Per bank write bursts -system.physmem.perBankRdBursts::12 64856 # Per bank write bursts -system.physmem.perBankRdBursts::13 71148 # Per bank write bursts -system.physmem.perBankRdBursts::14 68907 # Per bank write bursts -system.physmem.perBankRdBursts::15 71898 # Per bank write bursts -system.physmem.perBankWrBursts::0 59424 # Per bank write bursts -system.physmem.perBankWrBursts::1 59953 # Per bank write bursts -system.physmem.perBankWrBursts::2 60707 # Per bank write bursts -system.physmem.perBankWrBursts::3 57771 # Per bank write bursts -system.physmem.perBankWrBursts::4 56630 # Per bank write bursts -system.physmem.perBankWrBursts::5 62461 # Per bank write bursts -system.physmem.perBankWrBursts::6 55190 # Per bank write bursts -system.physmem.perBankWrBursts::7 55103 # Per bank write bursts -system.physmem.perBankWrBursts::8 55968 # Per bank write bursts -system.physmem.perBankWrBursts::9 60498 # Per bank write bursts -system.physmem.perBankWrBursts::10 60512 # Per bank write bursts -system.physmem.perBankWrBursts::11 59733 # Per bank write bursts -system.physmem.perBankWrBursts::12 57588 # Per bank write bursts -system.physmem.perBankWrBursts::13 61842 # Per bank write bursts -system.physmem.perBankWrBursts::14 59660 # Per bank write bursts -system.physmem.perBankWrBursts::15 61995 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 294002 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 72701 # Per bank write bursts +system.physmem.perBankRdBursts::1 69688 # Per bank write bursts +system.physmem.perBankRdBursts::2 71671 # Per bank write bursts +system.physmem.perBankRdBursts::3 65333 # Per bank write bursts +system.physmem.perBankRdBursts::4 67150 # Per bank write bursts +system.physmem.perBankRdBursts::5 75432 # Per bank write bursts +system.physmem.perBankRdBursts::6 63718 # Per bank write bursts +system.physmem.perBankRdBursts::7 62281 # Per bank write bursts +system.physmem.perBankRdBursts::8 61723 # Per bank write bursts +system.physmem.perBankRdBursts::9 108434 # Per bank write bursts +system.physmem.perBankRdBursts::10 66581 # Per bank write bursts +system.physmem.perBankRdBursts::11 66036 # Per bank write bursts +system.physmem.perBankRdBursts::12 64933 # Per bank write bursts +system.physmem.perBankRdBursts::13 72823 # Per bank write bursts +system.physmem.perBankRdBursts::14 65732 # Per bank write bursts +system.physmem.perBankRdBursts::15 71336 # Per bank write bursts +system.physmem.perBankWrBursts::0 59678 # Per bank write bursts +system.physmem.perBankWrBursts::1 59397 # Per bank write bursts +system.physmem.perBankWrBursts::2 61038 # Per bank write bursts +system.physmem.perBankWrBursts::3 58102 # Per bank write bursts +system.physmem.perBankWrBursts::4 58442 # Per bank write bursts +system.physmem.perBankWrBursts::5 63800 # Per bank write bursts +system.physmem.perBankWrBursts::6 56091 # Per bank write bursts +system.physmem.perBankWrBursts::7 56307 # Per bank write bursts +system.physmem.perBankWrBursts::8 55145 # Per bank write bursts +system.physmem.perBankWrBursts::9 60224 # Per bank write bursts +system.physmem.perBankWrBursts::10 58756 # Per bank write bursts +system.physmem.perBankWrBursts::11 59336 # Per bank write bursts +system.physmem.perBankWrBursts::12 57263 # Per bank write bursts +system.physmem.perBankWrBursts::13 62824 # Per bank write bursts +system.physmem.perBankWrBursts::14 57899 # Per bank write bursts +system.physmem.perBankWrBursts::15 61470 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 51771787505500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times write queue was full causing retry +system.physmem.totGap 51771752359500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1081653 # Read request sizes (log2) +system.physmem.readPktSize::6 1083174 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 944726 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1098127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 20478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 945460 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1099993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 20089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1098 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,137 +165,137 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 55253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 54993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 56005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 55878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 57269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 56677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 57037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 56298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 54772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 55404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 53434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 52819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 51965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 441395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 300.022755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.726713 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.159215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 176110 39.90% 39.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 107371 24.33% 64.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38199 8.65% 72.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22075 5.00% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15487 3.51% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11537 2.61% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10154 2.30% 86.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8595 1.95% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 51867 11.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 441395 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 52856 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.268333 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 295.103325 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 52849 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 53872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 55240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 55119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 56051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 56007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 57237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 56745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 56988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 56201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 54839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 55500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 53521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 52708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 51972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 442229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 299.767080 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.615293 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.948153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 176550 39.92% 39.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 107641 24.34% 64.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38242 8.65% 72.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22044 4.98% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15615 3.53% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11547 2.61% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10103 2.28% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8633 1.95% 88.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 51854 11.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 442229 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52882 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.284426 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 294.979543 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 52875 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 52856 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 52856 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.879427 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.143276 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.780491 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 105 0.20% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 78 0.15% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 62 0.12% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 98 0.19% 0.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49304 93.28% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 574 1.09% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 365 0.69% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 594 1.12% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 149 0.28% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 324 0.61% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 209 0.40% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 26 0.05% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 84 0.16% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 140 0.26% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 28 0.05% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 39 0.07% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 454 0.86% 99.58% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 52882 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52882 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.884573 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.137705 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.800600 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 115 0.22% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 64 0.12% 0.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 68 0.13% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 119 0.23% 0.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49331 93.29% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 541 1.02% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 348 0.66% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 615 1.16% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 130 0.25% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 329 0.62% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 199 0.38% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 29 0.05% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 82 0.16% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 151 0.29% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 24 0.05% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 42 0.08% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 468 0.88% 99.57% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 24 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 18 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 112 0.21% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 11 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 24 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 7 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 52856 # Writes before turning the bus around for reads -system.physmem.totQLat 13880638873 # Total ticks spent queuing -system.physmem.totMemAccLat 34958751373 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5620830000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12347.50 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::72-75 19 0.04% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 123 0.23% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 28 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52882 # Writes before turning the bus around for reads +system.physmem.totQLat 13860867186 # Total ticks spent queuing +system.physmem.totMemAccLat 34965342186 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5627860000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12314.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31097.50 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31064.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.34 # Average system read bandwidth in MiByte/s @@ -305,40 +305,40 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.36 # Average write queue length when enqueuing -system.physmem.readRowHits 908414 # Number of row buffer hits during reads -system.physmem.writeRowHits 719391 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.12 # Row buffer hit rate for writes -system.physmem.avgGap 24985563.94 # Average gap between requests -system.physmem.pageHitRate 78.67 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1674025920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 913407000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4198810200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3027708720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3381481552800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1295576085285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29926602975000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34613474564925 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.577915 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49785017997770 # Time in different power states -system.physmem_0.memoryStateTime::REF 1728773800000 # Time in different power states +system.physmem.avgWrQLen 9.22 # Average write queue length when enqueuing +system.physmem.readRowHits 909331 # Number of row buffer hits during reads +system.physmem.writeRowHits 719783 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.11 # Row buffer hit rate for writes +system.physmem.avgGap 24958385.15 # Average gap between requests +system.physmem.pageHitRate 78.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1706473440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 931111500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4274158200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3064100400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3381479010000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1298516894550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29923999959000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34613971707090 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.588021 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49780674651877 # Time in different power states +system.physmem_0.memoryStateTime::REF 1728772500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 257997880230 # Time in different power states +system.physmem_0.memoryStateTime::ACT 262307488123 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1662920280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 907347375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4569645600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3096118080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3381481552800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1293349218120 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29928556367250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34613623169505 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.580786 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49788229996275 # Time in different power states -system.physmem_1.memoryStateTime::REF 1728773800000 # Time in different power states +system.physmem_1.actEnergy 1636777800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 893083125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4505264400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3064502160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3381479010000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1291239562905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29930383583250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34613201783640 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.573149 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49791285234291 # Time in different power states +system.physmem_1.memoryStateTime::REF 1728772500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 254784926225 # Time in different power states +system.physmem_1.memoryStateTime::ACT 251692056959 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -392,68 +392,69 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 115431 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 115431 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17925 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83577 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 115422 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.155949 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 52.981983 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 115421 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 115460 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 115460 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17717 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83741 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 115450 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.259853 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 63.668442 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 115448 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 115422 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 101511 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 24872.984209 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21671.671712 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15716.369374 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 100971 99.47% 99.47% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.47% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 465 0.46% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 13 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 29 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 115450 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 101468 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 25057.924666 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21784.198284 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16152.265883 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 100874 99.41% 99.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.42% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 517 0.51% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 5 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 13 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 19 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 101511 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 118356120 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean -14.037796 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1779815204 1503.78% 1503.78% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -1661459084 -1403.78% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 118356120 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 83577 82.34% 82.34% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17925 17.66% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 101502 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 115431 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 101468 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -3983763676 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.449006 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1788733704 -44.90% -44.90% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -5772497380 144.90% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -3983763676 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 83741 82.54% 82.54% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17717 17.46% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101458 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 115460 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 115431 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101502 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 115460 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101458 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101502 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 216933 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101458 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 216918 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 77847569 # DTB read hits -system.cpu0.dtb.read_misses 88672 # DTB read misses -system.cpu0.dtb.write_hits 70757652 # DTB write hits -system.cpu0.dtb.write_misses 26759 # DTB write misses +system.cpu0.dtb.read_hits 77974126 # DTB read hits +system.cpu0.dtb.read_misses 88549 # DTB read misses +system.cpu0.dtb.write_hits 70569009 # DTB write hits +system.cpu0.dtb.write_misses 26911 # DTB write misses system.cpu0.dtb.flush_tlb 51778 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 18503 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 67979 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 18628 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 500 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 67577 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3908 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3961 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9235 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 77936241 # DTB read accesses -system.cpu0.dtb.write_accesses 70784411 # DTB write accesses +system.cpu0.dtb.perms_faults 9183 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78062675 # DTB read accesses +system.cpu0.dtb.write_accesses 70595920 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 148605221 # DTB hits -system.cpu0.dtb.misses 115431 # DTB misses -system.cpu0.dtb.accesses 148720652 # DTB accesses +system.cpu0.dtb.hits 148543135 # DTB hits +system.cpu0.dtb.misses 115460 # DTB misses +system.cpu0.dtb.accesses 148658595 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,277 +484,278 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 74042 # Table walker walks requested -system.cpu0.itb.walker.walksLong 74042 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4197 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64819 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 74042 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 74042 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 74042 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 69016 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28471.542831 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25336.788819 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18532.815053 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 68368 99.06% 99.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 559 0.81% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 14 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 69016 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 74491 # Table walker walks requested +system.cpu0.itb.walker.walksLong 74491 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4184 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 65168 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 74491 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 74491 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 74491 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 69352 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28600.025955 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25396.938168 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18997.799631 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 68658 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 606 0.87% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 12 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 31 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 69352 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 64819 93.92% 93.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4197 6.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 69016 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 65168 93.97% 93.97% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4184 6.03% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 69352 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74042 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74042 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74491 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74491 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 69016 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 69016 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 143058 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 414105554 # ITB inst hits -system.cpu0.itb.inst_misses 74042 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 69352 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 69352 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 143843 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 413472692 # ITB inst hits +system.cpu0.itb.inst_misses 74491 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51778 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 18503 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 50190 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 18628 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 500 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 50115 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 414179596 # ITB inst accesses -system.cpu0.itb.hits 414105554 # DTB hits -system.cpu0.itb.misses 74042 # DTB misses -system.cpu0.itb.accesses 414179596 # DTB accesses -system.cpu0.numCycles 51772404432 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 413547183 # ITB inst accesses +system.cpu0.itb.hits 413472692 # DTB hits +system.cpu0.itb.misses 74491 # DTB misses +system.cpu0.itb.accesses 413547183 # DTB accesses +system.cpu0.numCycles 51772397578 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 15961 # number of quiesce instructions executed -system.cpu0.committedInsts 413854142 # Number of instructions committed -system.cpu0.committedOps 486394511 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 447175967 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 436796 # Number of float alu accesses -system.cpu0.num_func_calls 24852805 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 62753360 # number of instructions that are conditional controls -system.cpu0.num_int_insts 447175967 # number of integer instructions -system.cpu0.num_fp_insts 436796 # number of float instructions -system.cpu0.num_int_register_reads 647088270 # number of times the integer registers were read -system.cpu0.num_int_register_writes 354432965 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 705701 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 368548 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 107266365 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 106966753 # number of times the CC registers were written -system.cpu0.num_mem_refs 148595341 # number of memory refs -system.cpu0.num_load_insts 77843031 # Number of load instructions -system.cpu0.num_store_insts 70752310 # Number of store instructions -system.cpu0.num_idle_cycles 50229100240.489449 # Number of idle cycles -system.cpu0.num_busy_cycles 1543304191.510550 # Number of busy cycles -system.cpu0.not_idle_fraction 0.029809 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.970191 # Percentage of idle cycles -system.cpu0.Branches 92298416 # Number of branches fetched +system.cpu0.committedInsts 413219664 # Number of instructions committed +system.cpu0.committedOps 485565994 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 446433803 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 442229 # Number of float alu accesses +system.cpu0.num_func_calls 24786010 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 62671041 # number of instructions that are conditional controls +system.cpu0.num_int_insts 446433803 # number of integer instructions +system.cpu0.num_fp_insts 442229 # number of float instructions +system.cpu0.num_int_register_reads 644929511 # number of times the integer registers were read +system.cpu0.num_int_register_writes 353812607 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 719009 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 362960 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 107066643 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 106758859 # number of times the CC registers were written +system.cpu0.num_mem_refs 148533323 # number of memory refs +system.cpu0.num_load_insts 77969520 # Number of load instructions +system.cpu0.num_store_insts 70563803 # Number of store instructions +system.cpu0.num_idle_cycles 50229359275.953438 # Number of idle cycles +system.cpu0.num_busy_cycles 1543038302.046558 # Number of busy cycles +system.cpu0.not_idle_fraction 0.029804 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.970196 # Percentage of idle cycles +system.cpu0.Branches 92169862 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 336911536 69.23% 69.23% # Class of executed instruction -system.cpu0.op_class::IntMult 1057551 0.22% 69.45% # Class of executed instruction -system.cpu0.op_class::IntDiv 48617 0.01% 69.46% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 54899 0.01% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::MemRead 77843031 16.00% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 70752310 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 336128174 69.18% 69.18% # Class of executed instruction +system.cpu0.op_class::IntMult 1076007 0.22% 69.41% # Class of executed instruction +system.cpu0.op_class::IntDiv 49967 0.01% 69.42% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.42% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 53572 0.01% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::MemRead 77969520 16.05% 85.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 70563803 14.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 486667985 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9213148 # number of replacements +system.cpu0.op_class::total 485841084 # Class of executed instruction +system.cpu0.dcache.tags.replacements 9212621 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.942746 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 287360735 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9213660 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.188554 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 287301900 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9213133 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.183952 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5830459500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 293.957596 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 217.985149 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.574136 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.425752 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 301.496360 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 210.446385 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.588860 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.411028 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1195960121 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1195960121 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 72895855 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 72819187 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 145715042 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67181478 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 66888003 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134069481 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186279 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 186038 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 372317 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 164783 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 168129 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 332912 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1645519 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1628369 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3273888 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1788293 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1767339 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3555632 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 140077333 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 139707190 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 279784523 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 140263612 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 139893228 # number of overall hits -system.cpu0.dcache.overall_hits::total 280156840 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2397654 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2407349 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 4805003 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 991343 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 966962 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1958305 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 562095 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 539989 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1102084 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 607610 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 610974 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1218584 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 143596 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 139766 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 283362 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1195722346 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1195722346 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73035245 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 72652643 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 145687888 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67007378 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 67030482 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 134037860 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 184933 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 187057 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 371990 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165113 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 167764 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 332877 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1642151 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1632221 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3274372 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1781285 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1774075 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3555360 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 140042623 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 139683125 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 279725748 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 140227556 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 139870182 # number of overall hits +system.cpu0.dcache.overall_hits::total 280097738 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2403483 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2400966 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 4804449 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 980962 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 977666 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1958628 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 551880 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 550634 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1102514 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 610138 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 608619 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1218757 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 139928 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 142675 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 282603 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3388997 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 3374311 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6763308 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3951092 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 3914300 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2163537000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4321902000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 3384445 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 3378632 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6763077 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3936325 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 3929266 # number of overall misses +system.cpu0.dcache.overall_misses::total 7865591 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41217416000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 41024037000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 82241453000 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 69302452000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 138968792500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80072421500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 79431687000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 159504108500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3017045500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3182297000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6199342500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3020495500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3197083500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6217579000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6037541000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6379380500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12416921500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031702 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031850 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031776 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014259 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014233 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014246 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.747720 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745285 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.746502 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.787020 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.783916 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785467 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059893 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061439 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060664 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023464 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023438 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023451 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027233 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027069 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027151 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15877.639730 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15922.927190 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15900.330526 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32334.670436 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32482.814834 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32407.878251 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18614.640601 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18792.744994 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18701.912223 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58492.480374 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59440.322338 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58967.709653 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13590.714396 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13848.196100 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13716.849827 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023434 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023475 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023454 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027136 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027178 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027157 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15940.680085 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15902.920255 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15921.804675 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32536.278660 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32323.375357 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32429.910360 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18888.209028 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18423.825461 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18656.257722 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58224.653275 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59594.020233 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58908.483397 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13780.177825 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13734.880373 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13757.286323 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20668.020359 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20649.827258 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20658.940952 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20374.632292 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20392.618941 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20383.585752 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182561.399276 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185362.003505 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.139466 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179058.486647 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189858.278460 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.503961 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180795.797188 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187592.739206 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184221.846396 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20727.546384 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20635.599229 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20681.590992 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20468.509816 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20324.454356 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20396.517068 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182685.165002 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185189.536778 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183962.209561 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178854.541686 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190087.609251 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.578129 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180748.465707 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187612.284210 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184210.923360 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13381945 # number of replacements +system.cpu0.icache.tags.replacements 13370435 # number of replacements system.cpu0.icache.tags.tagsinuse 511.782255 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 813274304 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13382457 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 60.771673 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 813133937 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13370947 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 60.813489 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 61705740500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.029971 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.752284 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541074 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.458501 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 285.320721 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 226.461534 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.557267 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.442308 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 840039228 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 840039228 # 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number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436799500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016198 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016179 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016189 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016198 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016179 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016189 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016198 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016179 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016189 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12625.782307 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12675.090947 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12650.375843 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12625.782307 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12675.090947 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12650.375843 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12625.782307 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12675.090947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12650.375843 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016256 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016099 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016178 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016256 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016099 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016178 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016256 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016099 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016178 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12649.957665 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12671.439152 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12660.640731 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12649.957665 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12671.439152 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12660.640731 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12649.957665 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12671.439152 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12660.640731 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043 # average ReadReq mshr uncacheable latency @@ -1066,69 +1068,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 118026 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 118026 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17902 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85905 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 118017 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.101680 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 34.930834 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 118016 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 118017 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 103816 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25027.404254 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21748.751472 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15644.616464 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 103269 99.47% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 118174 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 118174 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17820 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86207 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 118168 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 118168 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 118168 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 104033 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25040.588083 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21749.548904 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15700.304805 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 103488 99.48% 99.48% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.00% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 471 0.45% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 7 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 35 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 17 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 103816 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2951550812 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.475602 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.499404 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1547787704 52.44% 52.44% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1403763108 47.56% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2951550812 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 85906 82.75% 82.75% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17902 17.25% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 103808 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 118026 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 470 0.45% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 4 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 22 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 104033 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1363590484 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 2.149961 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1568075704 -115.00% -115.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -2931666188 215.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1363590484 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 86208 82.87% 82.87% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17820 17.13% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 104028 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 118174 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 118026 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103808 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 118174 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 104028 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103808 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 221834 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 104028 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 222202 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 77737807 # DTB read hits -system.cpu1.dtb.read_misses 91072 # DTB read misses -system.cpu1.dtb.write_hits 70427017 # DTB write hits -system.cpu1.dtb.write_misses 26954 # DTB write misses +system.cpu1.dtb.read_hits 77583369 # DTB read hits +system.cpu1.dtb.read_misses 91391 # DTB read misses +system.cpu1.dtb.write_hits 70584225 # DTB write hits +system.cpu1.dtb.write_misses 26783 # DTB write misses system.cpu1.dtb.flush_tlb 51774 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 19160 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 483 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 67493 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 19034 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 497 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 67777 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3798 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3786 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9286 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 77828879 # DTB read accesses -system.cpu1.dtb.write_accesses 70453971 # DTB write accesses +system.cpu1.dtb.perms_faults 9337 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 77674760 # DTB read accesses +system.cpu1.dtb.write_accesses 70611008 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 148164824 # DTB hits -system.cpu1.dtb.misses 118026 # DTB misses -system.cpu1.dtb.accesses 148282850 # DTB accesses +system.cpu1.dtb.hits 148167594 # DTB hits +system.cpu1.dtb.misses 118174 # DTB misses +system.cpu1.dtb.accesses 148285768 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1158,129 +1156,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 75801 # Table walker walks requested -system.cpu1.itb.walker.walksLong 75801 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4159 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66376 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 75801 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 75801 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75801 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 70535 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28466.739916 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25302.677208 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18338.850484 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 69863 99.05% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 592 0.84% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 11 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 25 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 22 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 70535 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 75448 # Table walker walks requested +system.cpu1.itb.walker.walksLong 75448 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4153 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66142 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 75448 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 75448 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75448 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 70295 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28625.784195 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25406.753839 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18792.899470 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 69604 99.02% 99.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1 0.00% 99.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 599 0.85% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 17 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 70295 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1449734704 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1449734704 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1449734704 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 66376 94.10% 94.10% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4159 5.90% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 70535 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 66142 94.09% 94.09% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4153 5.91% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 70295 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75801 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75801 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75448 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75448 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 70535 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 70535 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 146336 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 412551212 # ITB inst hits -system.cpu1.itb.inst_misses 75801 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 70295 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 70295 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 145743 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 413032197 # ITB inst hits +system.cpu1.itb.inst_misses 75448 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51774 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 19160 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 483 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 50654 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 19034 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 497 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 50656 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 412627013 # ITB inst accesses -system.cpu1.itb.hits 412551212 # DTB hits -system.cpu1.itb.misses 75801 # DTB misses -system.cpu1.itb.accesses 412627013 # DTB accesses -system.cpu1.numCycles 51771176237 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 413107645 # ITB inst accesses +system.cpu1.itb.hits 413032197 # DTB hits +system.cpu1.itb.misses 75448 # DTB misses +system.cpu1.itb.accesses 413107645 # DTB accesses +system.cpu1.numCycles 51771113015 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 412292259 # Number of instructions committed -system.cpu1.committedOps 484490585 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 445445369 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 462328 # Number of float alu accesses -system.cpu1.num_func_calls 24787523 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 62474042 # number of instructions that are conditional controls -system.cpu1.num_int_insts 445445369 # number of integer instructions -system.cpu1.num_fp_insts 462328 # number of float instructions -system.cpu1.num_int_register_reads 644065931 # number of times the integer registers were read -system.cpu1.num_int_register_writes 352949314 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 746699 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 388588 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 106522074 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 106212078 # number of times the CC registers were written -system.cpu1.num_mem_refs 148153513 # number of memory refs -system.cpu1.num_load_insts 77732872 # Number of load instructions -system.cpu1.num_store_insts 70420641 # Number of store instructions -system.cpu1.num_idle_cycles 50233711408.448738 # Number of idle cycles -system.cpu1.num_busy_cycles 1537464828.551259 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029697 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970303 # Percentage of idle cycles -system.cpu1.Branches 92021257 # Number of branches fetched +system.cpu1.committedInsts 412774823 # Number of instructions committed +system.cpu1.committedOps 485146327 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 446024475 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 456863 # Number of float alu accesses +system.cpu1.num_func_calls 24836924 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 62537039 # number of instructions that are conditional controls +system.cpu1.num_int_insts 446024475 # number of integer instructions +system.cpu1.num_fp_insts 456863 # number of float instructions +system.cpu1.num_int_register_reads 646025772 # number of times the integer registers were read +system.cpu1.num_int_register_writes 353451520 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 733263 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 394304 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 106699743 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 106398156 # number of times the CC registers were written +system.cpu1.num_mem_refs 148156265 # number of memory refs +system.cpu1.num_load_insts 77578568 # Number of load instructions +system.cpu1.num_store_insts 70577697 # Number of store instructions +system.cpu1.num_idle_cycles 50233500723.542557 # Number of idle cycles +system.cpu1.num_busy_cycles 1537612291.457444 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029700 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970300 # Percentage of idle cycles +system.cpu1.Branches 92112103 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 335453186 69.20% 69.20% # Class of executed instruction -system.cpu1.op_class::IntMult 1057928 0.22% 69.42% # Class of executed instruction -system.cpu1.op_class::IntDiv 48471 0.01% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 57500 0.01% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::MemRead 77732872 16.03% 85.47% # Class of executed instruction -system.cpu1.op_class::MemWrite 70420641 14.53% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 336122870 69.24% 69.24% # Class of executed instruction +system.cpu1.op_class::IntMult 1039751 0.21% 69.46% # Class of executed instruction +system.cpu1.op_class::IntDiv 47048 0.01% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 58827 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::MemRead 77578568 15.98% 85.46% # Class of executed instruction +system.cpu1.op_class::MemWrite 70577697 14.54% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 484770600 # Class of executed instruction -system.iobus.trans_dist::ReadReq 40328 # Transaction distribution -system.iobus.trans_dist::ReadResp 40328 # Transaction distribution +system.cpu1.op_class::total 485424763 # Class of executed instruction +system.iobus.trans_dist::ReadReq 40321 # Transaction distribution +system.iobus.trans_dist::ReadResp 40321 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) @@ -1290,18 +1289,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231014 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231014 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353798 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353784 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1311,24 +1308,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334488 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334488 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492408 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) @@ -1341,79 +1337,73 @@ system.iobus.reqLayer16.occupancy 16500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25714000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25707000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 171000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38602500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 38601000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 565399896 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 121500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565515993 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147774000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147760000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115489 # number of replacements -system.iocache.tags.tagsinuse 10.442885 # Cycle average of tags in use +system.iocache.tags.replacements 115482 # number of replacements +system.iocache.tags.tagsinuse 10.442874 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115505 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13183784929000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.514154 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928730 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ethernet 3.514153 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928721 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.219635 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433046 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433045 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652680 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039920 # Number of tag accesses -system.iocache.tags.data_accesses 1039920 # Number of data accesses +system.iocache.tags.tag_accesses 1039857 # Number of tag accesses +system.iocache.tags.data_accesses 1039857 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8843 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8880 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8843 # number of demand (read+write) misses -system.iocache.demand_misses::total 8883 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses +system.iocache.demand_misses::total 8876 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8843 # number of overall misses -system.iocache.overall_misses::total 8883 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1656329126 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1661399626 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8836 # number of overall misses +system.iocache.overall_misses::total 8876 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5087000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1609197370 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1614284370 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13864058367 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13864058367 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1656329126 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1661750626 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1656329126 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1661750626 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13863548526 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13863548526 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5438000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1609197370 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1614635370 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5438000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1609197370 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1614635370 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8843 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8880 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8843 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8883 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8843 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8883 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1427,55 +1417,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187303.983490 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187094.552477 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182118.308058 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181932.195424 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.796661 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129978.796661 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 187303.983490 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 187070.879883 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 187303.983490 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 187070.879883 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34559 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.016782 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129974.016782 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135950 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182118.308058 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 181910.248986 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135950 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182118.308058 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 181910.248986 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32984 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3493 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3440 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.893788 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.588372 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8843 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8880 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8843 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8883 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8843 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8883 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1214179126 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1217399626 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3237000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1167397370 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1170634370 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530858367 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8530858367 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1214179126 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1217600626 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1214179126 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1217600626 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530348526 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8530348526 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3438000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1167397370 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1170835370 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3438000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1167397370 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1170835370 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1489,303 +1479,304 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137303.983490 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137094.552477 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132118.308058 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 131932.195424 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79978.796661 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.796661 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 137303.983490 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 137070.879883 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 137303.983490 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 137070.879883 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.016782 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.016782 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85950 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132118.308058 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131910.248986 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85950 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132118.308058 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131910.248986 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 985866 # number of replacements -system.l2c.tags.tagsinuse 65209.136555 # Cycle average of tags in use -system.l2c.tags.total_refs 41640566 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1047670 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 39.745880 # Average number of references to valid blocks. +system.l2c.tags.replacements 987985 # number of replacements +system.l2c.tags.tagsinuse 65209.498770 # Cycle average of tags in use +system.l2c.tags.total_refs 41654495 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1049725 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 39.681340 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 56075802500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37748.652544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 103.945817 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 161.083000 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3928.961788 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9675.154455 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 97.159223 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 145.757666 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4633.882908 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8714.539154 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575999 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001586 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059951 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.147631 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001483 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002224 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.070707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.132973 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995012 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 334 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61470 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 334 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 429 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2433 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5559 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53016 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005096 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.937958 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 371905439 # Number of tag accesses -system.l2c.tags.data_accesses 371905439 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 203125 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 155182 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 208882 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 158880 # number of ReadReq hits -system.l2c.ReadReq_hits::total 726069 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7212950 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7212950 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 13380350 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 13380350 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 4416 # 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number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 203125 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 155182 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6674320 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3753782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 208882 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 158880 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6638729 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3716312 # number of demand (read+write) hits -system.l2c.demand_hits::total 21509212 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 203125 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 155182 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6674320 # number of overall hits -system.l2c.overall_hits::cpu0.data 3753782 # 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number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5642597500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5636515000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2392920500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5965581500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 16505916000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004914 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006842 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004641 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.006454 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005585 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785735 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.786447 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.786093 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5970754000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 16505006000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005260 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007178 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004498 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.006520 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005729 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.786272 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.785361 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.785811 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.162817 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.163815 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.163310 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.004981 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005394 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005187 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.035065 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005394 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.065761 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.027072 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004914 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006842 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.004981 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.065570 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006454 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005394 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.065761 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.027072 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 126667.729279 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70680.375448 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70685.072261 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70682.738625 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.164651 # 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mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.391875 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005260 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007178 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005178 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.066471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004498 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.006520 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005358 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.065133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.027182 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005260 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007178 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005178 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.066471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004498 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006520 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005358 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.065133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.027182 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 127259.766556 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70685.332258 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70682.310251 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70683.801911 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120643.039166 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120656.223109 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 120649.571835 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122185.509459 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122001.944174 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122090.292885 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122703.908531 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122702.842091 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122703.372915 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120150.186998 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120189.809882 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120170.249757 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122185.509459 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121481.969037 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122001.944174 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121502.712249 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 121596.923925 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122185.509459 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121481.969037 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122001.944174 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121502.712249 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 121596.923925 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120524.496157 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120652.920493 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120588.213860 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122217.575566 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122121.681168 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122169.066076 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122600.651960 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122782.359685 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122690.203624 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120219.548432 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120186.409444 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120202.755444 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122217.575566 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121380.034993 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122121.681168 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121523.580194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121575.846667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122217.575566 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121380.034993 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122121.681168 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121523.580194 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121575.846667 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170038.721351 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170162.700575 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172838.872664 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138964.926782 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167558.189911 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178357.952186 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.192453 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172666.084730 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138954.857857 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167354.216011 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178587.311969 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.266621 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168788.438528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168742.777595 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175577.052123 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 149331.560091 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175594.918095 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 149324.678145 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76825 # Transaction distribution -system.membus.trans_dist::ReadResp 374618 # Transaction distribution +system.membus.trans_dist::ReadReq 76824 # Transaction distribution +system.membus.trans_dist::ReadResp 376266 # Transaction distribution system.membus.trans_dist::WriteReq 33707 # Transaction distribution system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::WritebackDirty 944726 # Transaction distribution -system.membus.trans_dist::CleanEvict 152734 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33164 # Transaction distribution +system.membus.trans_dist::WritebackDirty 945460 # Transaction distribution +system.membus.trans_dist::CleanEvict 154121 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33223 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33165 # Transaction distribution -system.membus.trans_dist::ReadExReq 787274 # Transaction distribution -system.membus.trans_dist::ReadExResp 787274 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 297793 # Transaction distribution +system.membus.trans_dist::UpgradeResp 33224 # Transaction distribution +system.membus.trans_dist::ReadExReq 787142 # Transaction distribution +system.membus.trans_dist::ReadExResp 787142 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 299442 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3294284 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3423970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340925 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 340925 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3764895 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3299562 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3429246 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 340924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3770170 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 122665376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 122835190 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7216000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7216000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 130051190 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3421 # Total snoops (count) -system.membus.snoop_fanout::samples 2435800 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13844 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 122809888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 122979698 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7215808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7215808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 130195506 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3417 # Total snoops (count) +system.membus.snoop_fanout::samples 2439476 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2435800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2439476 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2435800 # Request fanout histogram -system.membus.reqLayer0.occupancy 106891000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2439476 # Request fanout histogram +system.membus.reqLayer0.occupancy 106887500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5617000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5646000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6213973567 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6220729239 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5964440131 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5972547051 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227489060 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227475321 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2102,61 +2093,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 45763569 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 23167437 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2234 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2234 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 45741552 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 23157457 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2207 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1181074 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 20663813 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1182207 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 20652494 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8157694 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 13380350 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2156668 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 41465 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8165321 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13368850 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2150617 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 41555 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 41466 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1895643 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1895643 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13382462 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6108330 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1325248 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1218584 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40231524 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27858913 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 757060 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1077336 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 69924833 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1712992468 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 973558114 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2529304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3311872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2692391758 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1591852 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 25069303 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021336 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144501 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 41556 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1895867 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1895867 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13370952 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6107399 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1325421 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1218757 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40197004 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27857487 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 758584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1079607 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 69892682 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1711519828 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 973953566 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2539040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3323424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2691335858 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1592408 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 25060590 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021420 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144781 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 24534434 97.87% 97.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 534869 2.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 24523786 97.86% 97.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 536804 2.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 25069303 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 43835486500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 25060590 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 43819448000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1550881 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1523382 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20116818000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20099553000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12673228476 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 12672308976 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 440897000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 441204000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 663352000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 664179000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |