diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
20 files changed, 7013 insertions, 6805 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index ca493d5ab..302db364d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/dist/m5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,21 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/z/stever/hg/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/dist/m5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -186,6 +187,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -220,6 +222,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.dtb [system.cpu0.dstage2_mmu.stage2_tlb] @@ -237,7 +240,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu0.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -645,6 +647,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -713,6 +716,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.itb [system.cpu0.istage2_mmu.stage2_tlb] @@ -730,7 +734,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu0.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -755,6 +758,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -776,19 +780,27 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu0.l2cache.tags] @@ -805,13 +817,16 @@ size=1048576 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu0.l2cache.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port [system.cpu0.tracer] type=ExeTracer @@ -906,6 +921,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -940,6 +956,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.dtb [system.cpu1.dstage2_mmu.stage2_tlb] @@ -957,7 +974,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu1.toL2Bus.slave[5] [system.cpu1.dtb] type=ArmTLB @@ -1365,6 +1381,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -1433,6 +1450,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.itb [system.cpu1.istage2_mmu.stage2_tlb] @@ -1450,7 +1468,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu1.toL2Bus.slave[4] [system.cpu1.itb] type=ArmTLB @@ -1475,6 +1492,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -1496,19 +1514,27 @@ mem_side=system.toL2Bus.slave[1] [system.cpu1.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu1.l2cache.tags] @@ -1525,13 +1551,16 @@ size=1048576 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu1.l2cache.cpu_side -slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port [system.cpu1.tracer] type=ExeTracer @@ -1562,9 +1591,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=true -width=8 +width=16 default=system.realview.pciconfig.pio master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma @@ -1575,6 +1606,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -1610,6 +1642,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -1644,11 +1677,14 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side @@ -1698,7 +1734,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -2409,11 +2445,14 @@ port=3456 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false -width=8 +width=32 master=system.l2c.cpu_side slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr index 99334c62c..99334c62c 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout index 167ce3cc3..ef8cccd23 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -1,17 +1,17 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 31 2014 10:01:44 -gem5 started Oct 31 2014 11:28:00 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu0.isa: ISA system set to: 0x5a2b680 0x5a2b680 - 0: system.cpu1.isa: ISA system set to: 0x5a2b680 0x5a2b680 +info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu0.isa: ISA system set to: 0x36c6a30 0x36c6a30 + 0: system.cpu1.isa: ISA system set to: 0x36c6a30 0x36c6a30 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: Read CNTFREQ_EL0 frequency info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2843665155500 because m5_exit instruction encountered +Exiting @ tick 2846097440000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 57022429e..c733baa00 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846001 # Number of seconds simulated -sim_ticks 2846001096000 # Number of ticks simulated -final_tick 2846001096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846097 # Number of seconds simulated +sim_ticks 2846097440000 # Number of ticks simulated +final_tick 2846097440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163513 # Simulator instruction rate (inst/s) -host_op_rate 197998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3697981305 # Simulator tick rate (ticks/s) -host_mem_usage 648920 # Number of bytes of host memory used -host_seconds 769.61 # Real time elapsed on the host -sim_insts 125841424 # Number of instructions simulated -sim_ops 152380857 # Number of ops (including micro ops) simulated +host_inst_rate 101530 # Simulator instruction rate (inst/s) +host_op_rate 122947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2278332577 # Simulator tick rate (ticks/s) +host_mem_usage 584920 # Number of bytes of host memory used +host_seconds 1249.20 # Real time elapsed on the host +sim_insts 126830911 # Number of instructions simulated +sim_ops 153585651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1676864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1253436 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 9344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1671232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1335292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8458880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 217536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 601248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 396864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 606496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 432576 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12760092 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1676864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 217536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8825856 # Number of bytes written to this memory +system.physmem.bytes_read::total 12733532 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1671232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1888512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8840256 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8843600 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26201 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20110 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134408 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8858000 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 146 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26113 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 132170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9418 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9500 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6759 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199925 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137904 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199510 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138129 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142340 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 589200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 440420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3022526 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142565 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 587201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 469166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2972098 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 211261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 139446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 213097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 151989 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4483516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 589200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3101143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4474032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 587201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76343 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 663544 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3106097 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6220 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3107378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3101143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 589200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 446641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3022526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3112332 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3106097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 587201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 475386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2972098 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 211275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 139446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 213111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 151989 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7590894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199925 # Number of read requests accepted -system.physmem.writeReqs 178564 # Number of write requests accepted -system.physmem.readBursts 199925 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 178564 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12787648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 9914112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12760092 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11161936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23627 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14395 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11804 # Per bank write bursts -system.physmem.perBankRdBursts::1 12403 # Per bank write bursts -system.physmem.perBankRdBursts::2 13173 # Per bank write bursts -system.physmem.perBankRdBursts::3 12915 # Per bank write bursts -system.physmem.perBankRdBursts::4 15440 # Per bank write bursts -system.physmem.perBankRdBursts::5 12419 # Per bank write bursts -system.physmem.perBankRdBursts::6 12541 # Per bank write bursts -system.physmem.perBankRdBursts::7 12439 # Per bank write bursts -system.physmem.perBankRdBursts::8 12804 # Per bank write bursts -system.physmem.perBankRdBursts::9 13107 # Per bank write bursts -system.physmem.perBankRdBursts::10 11847 # Per bank write bursts -system.physmem.perBankRdBursts::11 11130 # Per bank write bursts -system.physmem.perBankRdBursts::12 12155 # Per bank write bursts -system.physmem.perBankRdBursts::13 12699 # Per bank write bursts -system.physmem.perBankRdBursts::14 11526 # Per bank write bursts -system.physmem.perBankRdBursts::15 11405 # Per bank write bursts -system.physmem.perBankWrBursts::0 9464 # Per bank write bursts -system.physmem.perBankWrBursts::1 9978 # Per bank write bursts -system.physmem.perBankWrBursts::2 10476 # Per bank write bursts -system.physmem.perBankWrBursts::3 10111 # Per bank write bursts -system.physmem.perBankWrBursts::4 9384 # Per bank write bursts -system.physmem.perBankWrBursts::5 9602 # Per bank write bursts -system.physmem.perBankWrBursts::6 9874 # Per bank write bursts -system.physmem.perBankWrBursts::7 9552 # Per bank write bursts -system.physmem.perBankWrBursts::8 9896 # Per bank write bursts -system.physmem.perBankWrBursts::9 10357 # Per bank write bursts -system.physmem.perBankWrBursts::10 9473 # Per bank write bursts -system.physmem.perBankWrBursts::11 9143 # Per bank write bursts -system.physmem.perBankWrBursts::12 9886 # Per bank write bursts -system.physmem.perBankWrBursts::13 9717 # Per bank write bursts -system.physmem.perBankWrBursts::14 9232 # Per bank write bursts -system.physmem.perBankWrBursts::15 8763 # Per bank write bursts +system.physmem.bw_total::total 7586364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199510 # Number of read requests accepted +system.physmem.writeReqs 178789 # Number of write requests accepted +system.physmem.readBursts 199510 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 178789 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12761024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 9911424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12733532 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11176336 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23895 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12377 # Per bank write bursts +system.physmem.perBankRdBursts::1 12507 # Per bank write bursts +system.physmem.perBankRdBursts::2 12921 # Per bank write bursts +system.physmem.perBankRdBursts::3 12944 # Per bank write bursts +system.physmem.perBankRdBursts::4 15059 # Per bank write bursts +system.physmem.perBankRdBursts::5 12345 # Per bank write bursts +system.physmem.perBankRdBursts::6 13163 # Per bank write bursts +system.physmem.perBankRdBursts::7 13279 # Per bank write bursts +system.physmem.perBankRdBursts::8 12255 # Per bank write bursts +system.physmem.perBankRdBursts::9 12304 # Per bank write bursts +system.physmem.perBankRdBursts::10 12058 # Per bank write bursts +system.physmem.perBankRdBursts::11 11233 # Per bank write bursts +system.physmem.perBankRdBursts::12 11543 # Per bank write bursts +system.physmem.perBankRdBursts::13 12301 # Per bank write bursts +system.physmem.perBankRdBursts::14 11677 # Per bank write bursts +system.physmem.perBankRdBursts::15 11425 # Per bank write bursts +system.physmem.perBankWrBursts::0 9896 # Per bank write bursts +system.physmem.perBankWrBursts::1 10159 # Per bank write bursts +system.physmem.perBankWrBursts::2 10174 # Per bank write bursts +system.physmem.perBankWrBursts::3 9995 # Per bank write bursts +system.physmem.perBankWrBursts::4 9156 # Per bank write bursts +system.physmem.perBankWrBursts::5 9568 # Per bank write bursts +system.physmem.perBankWrBursts::6 10283 # Per bank write bursts +system.physmem.perBankWrBursts::7 10373 # Per bank write bursts +system.physmem.perBankWrBursts::8 9590 # Per bank write bursts +system.physmem.perBankWrBursts::9 9571 # Per bank write bursts +system.physmem.perBankWrBursts::10 9719 # Per bank write bursts +system.physmem.perBankWrBursts::11 9542 # Per bank write bursts +system.physmem.perBankWrBursts::12 9254 # Per bank write bursts +system.physmem.perBankWrBursts::13 9350 # Per bank write bursts +system.physmem.perBankWrBursts::14 9412 # Per bank write bursts +system.physmem.perBankWrBursts::15 8824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 62 # Number of times write queue was full causing retry -system.physmem.totGap 2846000520000 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 2846096933500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199338 # Read request sizes (log2) +system.physmem.readPktSize::6 198923 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 174128 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 99213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174353 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,162 +184,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1868 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 117 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.620056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.134877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.994619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47499 52.23% 52.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17879 19.66% 71.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6335 6.97% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3699 4.07% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2819 3.10% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1518 1.67% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 969 1.07% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1044 1.15% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9183 10.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90945 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6522 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.635388 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.912572 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6520 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.927069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.222601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 310.362875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47359 52.21% 52.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17889 19.72% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6289 6.93% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3581 3.95% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2839 3.13% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.73% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 985 1.09% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1019 1.12% 89.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9187 10.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90716 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.562538 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.578248 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6522 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.751610 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.656400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 41.548658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6178 94.73% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 86 1.32% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 19 0.29% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 12 0.18% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 33 0.51% 97.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 33 0.51% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 29 0.44% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.20% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 13 0.20% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 4 0.06% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 22 0.34% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 18 0.28% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 8 0.12% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.09% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.08% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.08% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 7 0.11% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 9 0.14% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-911 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6522 # Writes before turning the bus around for reads -system.physmem.totQLat 5658505376 # Total ticks spent queuing -system.physmem.totMemAccLat 9404886626 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 999035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28319.86 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.737891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.670801 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 40.283485 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6175 94.65% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 90 1.38% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 23 0.35% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 26 0.40% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 32 0.49% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 26 0.40% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 10 0.15% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 20 0.31% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 20 0.31% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 23 0.35% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.11% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 7 0.11% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 5 0.08% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.06% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 14 0.21% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads +system.physmem.totQLat 5679096455 # Total ticks spent queuing +system.physmem.totMemAccLat 9417677705 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 996955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28482.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47069.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47232.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing -system.physmem.readRowHits 166469 # Number of row buffer hits during reads -system.physmem.writeRowHits 97300 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.80 # Row buffer hit rate for writes -system.physmem.avgGap 7519374.46 # Average gap between requests -system.physmem.pageHitRate 74.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 351842400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 191977500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 804437400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 508297680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83070715860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634730471750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905544559550 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.552036 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719396100671 # Time in different power states -system.physmem_0.memoryStateTime::REF 95034160000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing +system.physmem.readRowHits 166067 # Number of row buffer hits during reads +system.physmem.writeRowHits 97473 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.93 # Row buffer hit rate for writes +system.physmem.avgGap 7523405.91 # Average gap between requests +system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 359115120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 195945750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 815841000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83249453610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634629745250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905658854330 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.570214 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719227401175 # Time in different power states +system.physmem_0.memoryStateTime::REF 95037280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31570722329 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31827968825 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 335701800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 183170625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 754049400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 495506160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82302536835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635404313000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905362094780 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.487923 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720522847414 # Time in different power states -system.physmem_1.memoryStateTime::REF 95034160000 # Time in different power states +system.physmem_1.actEnergy 326697840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178257750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 739401000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 487697760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82096607520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635641013750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905362595300 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.466120 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720918284391 # Time in different power states +system.physmem_1.memoryStateTime::REF 95037280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30442207586 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30141762609 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -365,15 +363,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20635824 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13602989 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1045571 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13187813 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9323038 # Number of BTB hits +system.cpu0.branchPred.lookups 20630955 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13593557 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1040069 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13124579 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9315197 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.694345 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3366354 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 208367 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 70.975206 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3367508 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 204886 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,59 +402,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 68383 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 68383 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45560 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22823 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 68383 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 68383 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 68383 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6747 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9430.747147 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8234.841596 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6251.099816 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6572 97.41% 97.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 158 2.34% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6747 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 69457 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 69457 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46535 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22922 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 69457 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 69457 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 69457 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6849 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9469.922616 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8283.824538 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6457.338241 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6642 96.98% 96.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 191 2.79% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6849 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5180 76.77% 76.77% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1567 23.23% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6747 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68383 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5259 76.78% 76.78% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1590 23.22% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6849 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69457 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68383 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6747 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69457 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6849 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6747 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 75130 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6849 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 76306 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17310932 # DTB read hits -system.cpu0.dtb.read_misses 62315 # DTB read misses -system.cpu0.dtb.write_hits 14537397 # DTB write hits -system.cpu0.dtb.write_misses 6068 # DTB write misses +system.cpu0.dtb.read_hits 17312533 # DTB read hits +system.cpu0.dtb.read_misses 63301 # DTB read misses +system.cpu0.dtb.write_hits 14536158 # DTB write hits +system.cpu0.dtb.write_misses 6156 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1254 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1942 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17373247 # DTB read accesses -system.cpu0.dtb.write_accesses 14543465 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17375834 # DTB read accesses +system.cpu0.dtb.write_accesses 14542314 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31848329 # DTB hits -system.cpu0.dtb.misses 68383 # DTB misses -system.cpu0.dtb.accesses 31916712 # DTB accesses +system.cpu0.dtb.hits 31848691 # DTB hits +system.cpu0.dtb.misses 69457 # DTB misses +system.cpu0.dtb.accesses 31918148 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -486,38 +484,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3838 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3838 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3532 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3838 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3838 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3838 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2413 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9817.861169 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8667.312532 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5173.169908 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 854 35.39% 35.39% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1509 62.54% 97.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.12% 98.05% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 46 1.91% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3833 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9485.117817 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8378.584027 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4911.792845 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 918 37.95% 37.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1466 60.60% 98.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.20% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2114 87.61% 87.61% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.39% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2413 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3838 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3838 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2413 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2413 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6251 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38726658 # ITB inst hits -system.cpu0.itb.inst_misses 3838 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6252 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38694088 # ITB inst hits +system.cpu0.itb.inst_misses 3833 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -526,123 +524,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7377 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7309 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38730496 # ITB inst accesses -system.cpu0.itb.hits 38726658 # DTB hits -system.cpu0.itb.misses 3838 # DTB misses -system.cpu0.itb.accesses 38730496 # DTB accesses -system.cpu0.numCycles 164623207 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38697921 # ITB inst accesses +system.cpu0.itb.hits 38694088 # DTB hits +system.cpu0.itb.misses 3833 # DTB misses +system.cpu0.itb.accesses 38697921 # DTB accesses +system.cpu0.numCycles 164664294 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79533802 # Number of instructions committed -system.cpu0.committedOps 95718607 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5045973 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1856 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5527394503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.069852 # CPI: cycles per instruction -system.cpu0.ipc 0.483126 # IPC: instructions per cycle +system.cpu0.committedInsts 79545676 # Number of instructions committed +system.cpu0.committedOps 95726645 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5037895 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1845 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527555817 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.070060 # CPI: cycles per instruction +system.cpu0.ipc 0.483078 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed -system.cpu0.tickCycles 128554371 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 36068836 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 714653 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.517650 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30439123 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 715165 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.562378 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed +system.cpu0.tickCycles 127989646 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 36674648 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 713904 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.482804 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30358451 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 714416 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.494080 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.517650 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977574 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.977574 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.482804 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977505 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.977505 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63710880 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63710880 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 16167111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 16167111 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13468154 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13468154 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 380067 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 380067 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361342 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361342 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29635265 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29635265 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29635265 # number of overall hits -system.cpu0.dcache.overall_hits::total 29635265 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 537159 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 537159 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 529716 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 529716 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6447 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6447 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20264 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20264 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1066875 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1066875 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1066875 # number of overall misses -system.cpu0.dcache.overall_misses::total 1066875 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6690812322 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6690812322 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8678584493 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8678584493 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104630740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 104630740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454305285 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 454305285 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 153000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 153000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 15369396815 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15369396815 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 15369396815 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15369396815 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16704270 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16704270 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13997870 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13997870 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386514 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386514 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381606 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381606 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30702140 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30702140 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30702140 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30702140 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032157 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.032157 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037843 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016680 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016680 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053102 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053102 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034749 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034749 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034749 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.034749 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12455.925195 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12455.925195 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16383.466788 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16383.466788 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16229.368699 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16229.368699 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22419.329106 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22419.329106 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63703980 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63703980 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15781686 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15781686 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13418199 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13418199 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321521 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 321521 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365596 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365596 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361488 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361488 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29199885 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29199885 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29521406 # number of overall hits +system.cpu0.dcache.overall_hits::total 29521406 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 463568 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 463568 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 577310 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 577310 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136519 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 136519 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21073 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21073 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20283 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20283 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1040878 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1040878 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1177397 # number of overall misses +system.cpu0.dcache.overall_misses::total 1177397 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6134841542 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6134841542 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9140419725 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9140419725 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 317623227 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 317623227 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453858268 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 453858268 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386669 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381771 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381771 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30240763 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30240763 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30698803 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30698803 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028536 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028536 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041250 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041250 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298050 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298050 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054499 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054499 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053129 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053129 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034420 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034420 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038353 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.038353 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.962530 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.962530 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15832.775675 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15832.775675 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15072.520619 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15072.520619 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22376.288912 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22376.288912 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14405.995843 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14405.995843 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14675.361826 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14675.361826 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12973.755893 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12973.755893 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,74 +657,84 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 516062 # number of writebacks -system.cpu0.dcache.writebacks::total 516062 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42087 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 42087 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 229086 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 229086 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 271173 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 271173 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 271173 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 271173 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 495072 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 495072 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 300630 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 300630 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6447 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6447 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20264 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20264 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 795702 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 795702 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 795702 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 795702 # 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number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10162587229 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10162587229 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10162587229 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10162587229 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276747000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276747000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261903001 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261903001 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538650001 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538650001 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029637 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029637 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021477 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021477 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016680 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016680 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053102 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053102 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025917 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025917 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10948.595326 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10948.595326 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15774.354669 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15774.354669 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14725.261362 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14725.261362 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20884.411518 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.411518 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 513522 # number of writebacks +system.cpu0.dcache.writebacks::total 513522 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72271 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 72271 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253439 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 253439 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14656 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14656 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 325710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 325710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 325710 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 325710 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391297 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 391297 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323871 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323871 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103394 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 103394 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6417 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6417 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20283 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20283 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 715168 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 715168 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 818562 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 818562 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4428376943 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4428376943 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4906976685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4906976685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1616801678 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1616801678 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 95832009 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95832009 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422721232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422721232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 436500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 436500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335353628 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9335353628 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10952155306 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10952155306 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276481750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276481750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261665000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261665000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538146750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538146750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024087 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024087 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023141 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023141 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225731 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225731 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016596 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053129 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053129 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026664 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026664 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11317.175810 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11317.175810 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15151.022120 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15151.022120 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15637.287251 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15637.287251 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14934.082749 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14934.082749 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20841.159197 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20841.159197 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13053.371555 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13053.371555 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13379.750472 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13379.750472 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -726,58 +742,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1970130 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.783768 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36748265 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1970642 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.647865 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6452193250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783768 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 1969157 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.783924 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36716761 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1969669 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.641082 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6455779250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783924 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79408512 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79408512 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36748265 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36748265 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36748265 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36748265 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36748265 # number of overall hits -system.cpu0.icache.overall_hits::total 36748265 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1970661 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1970661 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1970661 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1970661 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1970661 # number of overall misses -system.cpu0.icache.overall_misses::total 1970661 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18596838762 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18596838762 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18596838762 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18596838762 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18596838762 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18596838762 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38718926 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38718926 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38718926 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38718926 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38718926 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38718926 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050897 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050897 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050897 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050897 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050897 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050897 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9436.853300 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9436.853300 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9436.853300 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9436.853300 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79342579 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79342579 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36716761 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36716761 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36716761 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36716761 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36716761 # number of overall hits +system.cpu0.icache.overall_hits::total 36716761 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1969686 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1969686 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1969686 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1969686 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1969686 # number of overall misses +system.cpu0.icache.overall_misses::total 1969686 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18594001543 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18594001543 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18594001543 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18594001543 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18594001543 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18594001543 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38686447 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38686447 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38686447 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38686447 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38686447 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38686447 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050914 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050914 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050914 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050914 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050914 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050914 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9440.084127 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9440.084127 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9440.084127 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9440.084127 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -786,358 +802,356 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1970661 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1970661 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1970661 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1970661 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1970661 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1970661 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16616813240 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16616813240 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16616813240 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16616813240 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16616813240 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16616813240 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 312357250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 312357250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 312357250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 312357250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050897 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050897 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050897 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8432.101330 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1969686 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1969686 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1969686 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1969686 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1969686 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1969686 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16614994457 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16614994457 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16614994457 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16614994457 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16614994457 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16614994457 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 312159000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 312159000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 312159000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 312159000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050914 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050914 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050914 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8435.351857 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8435.351857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8435.351857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8435.351857 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 2299938 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 2300657 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 626 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1838342 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1838481 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 119 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 288151 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 300423 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16135.818285 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2948802 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 316647 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.312585 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2825975663500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6474.830142 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 56.840728 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090495 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5820.472159 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1850.674004 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1932.910757 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.395192 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003469 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.355253 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.112956 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.117976 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984852 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1935 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 233119 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 300411 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16152.844833 # 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mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199716 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067384 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.851603 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.851603 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.910132 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.910132 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482875 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482875 # 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average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 116499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 116499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38767.974866 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38767.974866 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33619.682585 # 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average ReadReq mshr uncacheable latency @@ -1147,65 +1161,65 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2704309 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2644372 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 516061 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 357573 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 65952 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43054 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 89535 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298181 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284517 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3948091 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2342949 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11777 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172611 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6475428 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126338880 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86633336 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17628 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325620 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 213315464 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 705686 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3997625 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.147566 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.354669 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2703667 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2643606 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19130 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19130 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 513519 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 304285 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88848 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42983 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297594 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284124 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3946133 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2385460 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11633 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174179 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6517405 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126276224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86385120 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327200 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 213005640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 651207 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3963380 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.135029 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.341755 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 3407711 85.24% 85.24% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 589914 14.76% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 3428208 86.50% 86.50% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 535172 13.50% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3997625 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2250942493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3963380 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2258643996 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 117029497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 116241999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2966538511 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2965047043 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1219549045 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1230256203 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7373994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7364491 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 91216246 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 92392742 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 18670420 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6078179 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 807720 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9612678 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 6998038 # Number of BTB hits +system.cpu1.branchPred.lookups 18842889 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6205402 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 629106 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9920552 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 7177439 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.800088 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8300224 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 592338 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.349190 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8245946 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 413041 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1235,59 +1249,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 26198 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26198 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19047 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7151 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26198 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26198 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26198 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2710 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9322.699631 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8294.308784 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5681.860876 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1066 39.34% 39.34% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1510 55.72% 95.06% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.14% 99.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.22% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 3 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2710 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1205143764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1205143764 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1205143764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2001 73.84% 73.84% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 709 26.16% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2710 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26198 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 26188 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26188 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19132 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7056 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26188 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2719 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9780.159618 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8826.212048 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5631.617808 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 919 33.80% 33.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1662 61.13% 94.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.50% 97.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 62 2.28% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2719 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1631340764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1631340764 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1631340764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2011 73.96% 73.96% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 708 26.04% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2719 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26188 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26198 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2710 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2719 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2710 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28908 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2719 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28907 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10899944 # DTB read hits -system.cpu1.dtb.read_misses 24664 # DTB read misses -system.cpu1.dtb.write_hits 6857896 # DTB write hits -system.cpu1.dtb.write_misses 1534 # DTB write misses +system.cpu1.dtb.read_hits 11112548 # DTB read hits +system.cpu1.dtb.read_misses 24192 # DTB read misses +system.cpu1.dtb.write_hits 6961122 # DTB write hits +system.cpu1.dtb.write_misses 1996 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 340 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2061 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10924608 # DTB read accesses -system.cpu1.dtb.write_accesses 6859430 # DTB write accesses +system.cpu1.dtb.perms_faults 278 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11136740 # DTB read accesses +system.cpu1.dtb.write_accesses 6963118 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17757840 # DTB hits -system.cpu1.dtb.misses 26198 # DTB misses -system.cpu1.dtb.accesses 17784038 # DTB accesses +system.cpu1.dtb.hits 18073670 # DTB hits +system.cpu1.dtb.misses 26188 # DTB misses +system.cpu1.dtb.accesses 18099858 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1317,41 +1332,41 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2253 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2253 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2076 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2253 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2253 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2253 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 2252 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2252 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2071 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2252 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2252 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2252 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9627.345845 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8644.762201 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4978.900312 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.44% 16.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.39% 30.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 501 44.77% 75.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 236 21.09% 96.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 97.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.88% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9763.181412 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8935.720507 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4528.605471 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 139 12.42% 12.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.19% 27.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 525 46.92% 74.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 97.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.88% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.63% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1204569264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1204569264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1204569264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 955 85.34% 85.34% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 164 14.66% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walksPending::samples 1630766264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1630766264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1630766264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2253 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2253 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2252 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2252 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3372 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39818327 # ITB inst hits -system.cpu1.itb.inst_misses 2253 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin::total 3371 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39781680 # ITB inst hits +system.cpu1.itb.inst_misses 2252 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1364,118 +1379,126 @@ system.cpu1.itb.flush_entries 1157 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1899 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39820580 # ITB inst accesses -system.cpu1.itb.hits 39818327 # DTB hits -system.cpu1.itb.misses 2253 # DTB misses -system.cpu1.itb.accesses 39820580 # DTB accesses -system.cpu1.numCycles 115094455 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 39783932 # ITB inst accesses +system.cpu1.itb.hits 39781680 # DTB hits +system.cpu1.itb.misses 2252 # DTB misses +system.cpu1.itb.accesses 39783932 # DTB accesses +system.cpu1.numCycles 114623988 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 46307622 # Number of instructions committed -system.cpu1.committedOps 56662250 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 4905736 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2805 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5576292649 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.485432 # CPI: cycles per instruction -system.cpu1.ipc 0.402345 # IPC: instructions per cycle +system.cpu1.committedInsts 47285235 # Number of instructions committed +system.cpu1.committedOps 57859006 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5005620 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2776 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5576963738 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.424097 # CPI: cycles per instruction +system.cpu1.ipc 0.412525 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2806 # number of quiesce instructions executed -system.cpu1.tickCycles 98408596 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 16685859 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 195662 # number of replacements -system.cpu1.dcache.tags.tagsinuse 474.092793 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17323078 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 195999 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 88.383502 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90082708500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.092793 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925962 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.925962 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 35540406 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 35540406 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10562839 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10562839 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6561699 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6561699 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 92378 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 92378 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71754 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71754 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17124538 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17124538 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17124538 # number of overall hits -system.cpu1.dcache.overall_hits::total 17124538 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 188265 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 188265 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 144615 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 144615 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4906 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4906 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23743 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23743 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 332880 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 332880 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 332880 # number of overall misses -system.cpu1.dcache.overall_misses::total 332880 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2782453534 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2782453534 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3892497330 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3892497330 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 87637747 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 87637747 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 559501111 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 559501111 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 370500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 370500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6674950864 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6674950864 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6674950864 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6674950864 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10751104 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10751104 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6706314 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6706314 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97284 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97284 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95497 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95497 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17457418 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17457418 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17457418 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17457418 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.017511 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.017511 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021564 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021564 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050430 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.050430 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248626 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248626 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.019068 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.019068 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019068 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.019068 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14779.452017 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14779.452017 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26916.276527 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26916.276527 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17863.380962 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17863.380962 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23564.886956 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23564.886956 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2776 # number of quiesce instructions executed +system.cpu1.tickCycles 97884766 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 16739222 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 194739 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.948438 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17633406 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 195100 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 90.381374 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90504077500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.948438 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923727 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923727 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.705078 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36178407 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36178407 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10725883 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10725883 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6668052 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6668052 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49984 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49984 # 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number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3861386324 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316030492 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 316030492 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557062155 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 557062155 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 124000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 124000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6177338753 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6177338753 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6177338753 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6177338753 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10883851 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10883851 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6812778 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6812778 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96970 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96970 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95177 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95177 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 17696629 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 17696629 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 17777429 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 17777429 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014514 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.014514 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021243 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021243 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381386 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381386 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174477 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174477 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248779 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248779 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017105 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.017105 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018760 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.018760 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14660.896061 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14660.896061 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26680.667772 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26680.667772 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18679.029021 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18679.029021 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23526.571290 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23526.571290 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20052.123480 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20052.123480 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20407.866535 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20407.866535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18522.199493 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18522.199493 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1484,74 +1507,84 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120164 # number of writebacks -system.cpu1.dcache.writebacks::total 120164 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15759 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15759 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52033 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52033 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 67792 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 67792 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 67792 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 67792 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172506 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172506 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92582 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92582 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4906 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4906 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23743 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23743 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265088 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265088 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265088 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265088 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2304438945 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2304438945 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2314812844 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2314812844 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80267253 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80267253 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522512389 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522512389 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 358500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 358500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4619251789 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4619251789 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4619251789 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4619251789 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322402500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322402500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1844154499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1844154499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166556999 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166556999 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016045 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.016045 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013805 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013805 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050430 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050430 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248626 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248626 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.015185 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015185 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.601701 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.601701 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25002.839040 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25002.839040 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16361.038117 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16361.038117 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22007.007918 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22007.007918 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 119475 # number of writebacks +system.cpu1.dcache.writebacks::total 119475 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16075 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 16075 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52265 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52265 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 68340 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 68340 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 68340 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 68340 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141893 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 141893 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92461 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92461 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29935 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29935 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23678 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23678 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 234354 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 234354 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 264289 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 264289 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1871458583 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1871458583 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2300176813 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2300176813 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487265761 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487265761 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79878753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79878753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520207345 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520207345 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 119500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 119500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4171635396 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4171635396 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4658901157 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4658901157 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322015751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322015751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843986000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843986000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166001751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166001751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013037 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013037 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013572 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013572 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370483 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370483 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050366 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050366 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248779 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248779 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013243 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013243 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014867 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014867 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13189.224155 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13189.224155 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24877.265150 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24877.265150 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16277.459863 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16277.459863 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16355.191032 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16355.191032 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21970.071163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21970.071163 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17800.572621 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17800.572621 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17628.055488 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17628.055488 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1559,57 +1592,57 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 948962 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.398770 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38866849 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 949474 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.935138 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 71724827500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.398770 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975388 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975388 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 947666 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.322678 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38831450 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 948178 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.953756 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72138919500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.322678 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975240 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975240 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80582120 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80582120 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 38866849 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38866849 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38866849 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38866849 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38866849 # number of overall hits -system.cpu1.icache.overall_hits::total 38866849 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 949474 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 949474 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 949474 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 949474 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 949474 # number of overall misses -system.cpu1.icache.overall_misses::total 949474 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8197479438 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8197479438 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8197479438 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8197479438 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8197479438 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8197479438 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39816323 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39816323 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39816323 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39816323 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39816323 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39816323 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023846 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023846 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023846 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023846 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023846 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023846 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.706071 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.706071 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8633.706071 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8633.706071 # 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number of overall misses +system.cpu1.icache.overall_misses::total 948178 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8186316171 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8186316171 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8186316171 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8186316171 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8186316171 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8186316171 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39779628 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39779628 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39779628 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39779628 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8633.733509 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8633.733509 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1618,344 +1651,354 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 949474 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 949474 # 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average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 263000 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 263018 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 198185 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 198250 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 56 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 69926 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 55260 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15340.181807 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1180273 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 70026 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.854783 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58438 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 54866 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15346.205956 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1177923 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 69767 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.883670 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 7920.573124 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.864575 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.107624 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4396.054830 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2144.688544 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 841.893110 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.483433 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002250 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.268314 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.130901 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051385 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.936290 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2047 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12670 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 77 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 853 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5605 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6801 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.124939 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.773315 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 22538505 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 22538505 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28252 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2535 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 928580 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 109415 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1068782 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120163 # 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mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947996 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947996 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958863 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958863 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546801 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546801 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104183 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124466 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15397.298227 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18475.608133 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35413.300077 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15957.484300 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15957.484300 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15100.211457 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15100.211457 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32362.948722 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32362.948722 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22377.297493 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24720.789733 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123779 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15573.986058 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18476.484941 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42252.287771 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15940.014772 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15940.014772 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15081.828305 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15081.828305 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 97000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 97000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32781.531259 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32781.531259 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22327.514398 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25481.924738 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1965,58 +2008,58 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1549513 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1217389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120163 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 34752 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42182 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86369 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85047 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67036 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1899176 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835933 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7082 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62248 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2804439 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60773632 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25876936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11012 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115596 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86777176 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 610005 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1929839 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.274006 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.446012 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1546268 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1215347 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11936 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 119475 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 29668 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76508 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42110 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86467 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67037 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1896584 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 833808 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7155 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62301 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2799848 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60690688 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25792980 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11328 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 116228 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86611224 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 603822 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1920664 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.272089 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.445035 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 1401052 72.60% 72.60% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 528787 27.40% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 1398073 72.79% 72.79% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 522591 27.21% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1929839 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 840003478 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1920664 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 837814982 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80148998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80458500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1425055438 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1423116171 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 412471555 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 410915491 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4329500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4323500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33365476 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33252737 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::ReadReq 31003 # Transaction distribution +system.iobus.trans_dist::ReadResp 31003 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution @@ -2042,9 +2085,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2067,9 +2110,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2110,52 +2153,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 199065929 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198973953 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36796533 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36786758 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.480362 # Cycle average of tags in use +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.479940 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270133806000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.480362 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.905023 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.905023 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270378265000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.479940 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904996 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904996 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32660377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32660377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6669320019 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6669320019 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32660377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32660377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32660377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32660377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses +system.iocache.demand_misses::total 243 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 243 # number of overall misses +system.iocache.overall_misses::total 243 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31380127 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31380127 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6638963068 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6638963068 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31380127 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31380127 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31380127 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31380127 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2164,40 +2207,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128079.909804 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128079.909804 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184113.295578 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 184113.295578 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128079.909804 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128079.909804 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 23275 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129136.325103 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129136.325103 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183275.261374 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183275.261374 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129136.325103 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129136.325103 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22458 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3594 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.476071 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.576281 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19371377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19371377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4785606085 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4785606085 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19371377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19371377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19371377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19371377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18685627 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18685627 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4755299084 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4755299084 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18685627 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18685627 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18685627 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18685627 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2206,304 +2249,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75966.184314 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75966.184314 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132111.475403 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132111.475403 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75966.184314 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75966.184314 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75966.184314 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75966.184314 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76895.584362 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76895.584362 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131274.820119 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131274.820119 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 135784 # number of replacements -system.l2c.tags.tagsinuse 63989.836026 # Cycle average of tags in use -system.l2c.tags.total_refs 379813 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200303 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.896192 # Average number of references to valid blocks. +system.l2c.tags.replacements 135638 # number of replacements +system.l2c.tags.tagsinuse 64035.864385 # Cycle average of tags in use +system.l2c.tags.total_refs 380564 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200114 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.901736 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12166.183008 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 73.341692 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030170 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8672.913636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2762.328324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.457886 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.004073 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2139.434191 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 561.920463 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1923.222583 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.185641 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.132338 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544380 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032645 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008574 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976407 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31538 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32925 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 124 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5437 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25977 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 12087.017372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.160254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033685 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8509.496822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2877.165248 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.414678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.500349 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2186.391247 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 567.991773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2040.692959 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.184433 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001177 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.129845 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544379 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.033362 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008667 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.031139 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977110 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30037 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34391 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25126 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29429 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.481232 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.502396 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5287676 # Number of tag accesses -system.l2c.tags.data_accesses 5287676 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 420 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 71 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 47985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 21581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 76019 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 126 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 31 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 17578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 7426 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7556 # number of ReadReq hits -system.l2c.ReadReq_hits::total 178793 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 232242 # number of Writeback hits -system.l2c.Writeback_hits::total 232242 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3124 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 764 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3888 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 164 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12016886672 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1614750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 232356996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 671943770 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 826146057 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16947682100 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 205778000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3714619750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6850000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919856251 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5847104001 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2763444000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533087000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4296531000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 205778000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6478063750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6850000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3452943251 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10143635001 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.165732 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.105127 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.496318 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.747173 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817723 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.762950 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795024 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.883639 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850575 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.728427 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.828958 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.768265 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281792 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.462040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.514585 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.247458 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319374 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281792 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735232 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141892 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.157199 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.462040 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.549870 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.514585 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74516.538416 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73944.513196 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87588.427365 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17836.287759 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.012109 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17818.385732 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17922.124457 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.561719 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17828.243024 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80203.430324 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69785.069598 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75770.793429 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75854.403149 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79090.867580 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87801.166169 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17751.429622 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17758.884431 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17753.216423 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17896.675112 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.948923 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.447505 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79077.135895 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69691.543041 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75064.022094 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2706,58 +2752,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215369 # Transaction distribution -system.membus.trans_dist::ReadResp 215369 # Transaction distribution -system.membus.trans_dist::WriteReq 31074 # Transaction distribution -system.membus.trans_dist::WriteResp 31074 # Transaction distribution -system.membus.trans_dist::Writeback 137904 # Transaction distribution +system.membus.trans_dist::ReadReq 214962 # Transaction distribution +system.membus.trans_dist::ReadResp 214962 # Transaction distribution +system.membus.trans_dist::WriteReq 31066 # Transaction distribution +system.membus.trans_dist::WriteResp 31066 # Transaction distribution +system.membus.trans_dist::Writeback 138129 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 77019 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40910 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14411 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 39992 # Transaction distribution -system.membus.trans_dist::ReadExResp 19617 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76255 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40796 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14193 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 40018 # Transaction distribution +system.membus.trans_dist::ReadExResp 19540 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14196 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 785643 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 894551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661851 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 783963 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892875 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19286572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19478976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24114432 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 124537 # Total snoops (count) -system.membus.snoop_fanout::samples 508980 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19273388 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19465716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24102196 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123912 # Total snoops (count) +system.membus.snoop_fanout::samples 507941 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 508980 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 507941 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 508980 # Request fanout histogram -system.membus.reqLayer0.occupancy 88720999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 507941 # Request fanout histogram +system.membus.reqLayer0.occupancy 88612000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12492999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12528499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1167594605 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1167691410 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1174957130 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1172073016 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37546467 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37476242 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2790,44 +2836,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 518257 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 518242 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31074 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31074 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 232242 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 80802 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41230 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 122032 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51798 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51798 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1084621 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339731 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1424352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34113464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5575752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39689216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 290726 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 922102 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039605 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.195030 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 516720 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 516705 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31066 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31066 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232835 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79932 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41134 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 121066 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51762 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51762 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083099 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1421855 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34093856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5618324 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39712180 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 288702 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 920160 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039660 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195160 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 885582 96.04% 96.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36520 3.96% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 883666 96.03% 96.03% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36494 3.97% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 922102 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 794355306 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 920160 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 787000770 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 683518313 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 681574777 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 260405210 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 259216519 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal index 89f9e916a..03b467a01 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal @@ -158,10 +158,10 @@ ata1.00: 1048320 sectors, multi 0: LBA ata1.00: configured for UDMA/33
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
+sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-sd 0:0:0:0: Attached scsi generic sg0 type 0
sda: sda1
sd 0:0:0:0: [sda] Attached SCSI disk
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
@@ -199,7 +199,7 @@ oprofile: using timer interrupt. TCP: cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200)
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
ALSA device list:
No soundcards found.
@@ -209,6 +209,6 @@ Freeing unused kernel memory: 292K (806aa000 - 806f3000)
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
starting pid 680, tty '': '/etc/rc.d/rc.local'
warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 12:00:02 UTC 2009
+Thu Jan 1 00:00:02 UTC 2009
S: devpts
-Thu Jan 1 12:00:02 UTC 2009
+Thu Jan 1 00:00:02 UTC 2009
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index 9c1096f55..b2af2f1b4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/binaries/boot_emm.arm +boot_loader=/dist/m5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,21 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.vram system.physmem system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.ext/tests/halt.sh +readfile=/z/stever/hg/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-aarch32-ael.img +image_file=/dist/m5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -186,6 +187,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -220,6 +222,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -237,7 +240,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -645,6 +647,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -713,6 +716,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -730,7 +734,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -755,6 +758,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -788,13 +792,16 @@ size=4194304 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -825,9 +832,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=true -width=8 +width=16 default=system.realview.pciconfig.pio master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma @@ -838,6 +847,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -872,11 +882,14 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side @@ -926,7 +939,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr index 99a5b93a6..99a5b93a6 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout index 89600f4c4..e4f6e6f46 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout @@ -1,16 +1,16 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 31 2014 10:01:44 -gem5 started Oct 31 2014 11:27:21 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 - 0: system.cpu.isa: ISA system set to: 0x5580680 0x5580680 +info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 + 0: system.cpu.isa: ISA system set to: 0x3fbcc30 0x3fbcc30 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 +info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: Read CNTFREQ_EL0 frequency info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2852222670000 because m5_exit instruction encountered +Exiting @ tick 2852831758500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 6dd28da03..46452a5a5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.853442 # Number of seconds simulated -sim_ticks 2853442108500 # Number of ticks simulated -final_tick 2853442108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852832 # Number of seconds simulated +sim_ticks 2852831758500 # Number of ticks simulated +final_tick 2852831758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171765 # Simulator instruction rate (inst/s) -host_op_rate 207684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4374009836 # Simulator tick rate (ticks/s) -host_mem_usage 619996 # Number of bytes of host memory used -host_seconds 652.36 # Real time elapsed on the host -sim_insts 112053421 # Number of instructions simulated -sim_ops 135485276 # Number of ops (including micro ops) simulated +host_inst_rate 111123 # Simulator instruction rate (inst/s) +host_op_rate 134357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2834419538 # Simulator tick rate (ticks/s) +host_mem_usage 554504 # Number of bytes of host memory used +host_seconds 1006.50 # Real time elapsed on the host +sim_insts 111845135 # Number of instructions simulated +sim_ops 135229426 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7744 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1671680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9169380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1669888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9170532 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10849380 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1671680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1671680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7972992 # Number of bytes written to this memory +system.physmem.bytes_read::total 10849188 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1669888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1669888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7971008 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7990516 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 114 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7988532 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 121 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26092 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143809 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170041 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124578 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170038 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124547 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128959 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2557 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128928 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2714 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 585847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3213445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 585847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 585847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2794166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2800308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2794166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 585344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3214537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2794069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2800211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2794069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2714 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 585847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3219587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6602516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170041 # Number of read requests accepted -system.physmem.writeReqs 165183 # Number of write requests accepted -system.physmem.readBursts 170041 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165183 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10875008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 9072064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10849380 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10308852 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23407 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4604 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10431 # Per bank write bursts -system.physmem.perBankRdBursts::1 10779 # Per bank write bursts -system.physmem.perBankRdBursts::2 11040 # Per bank write bursts -system.physmem.perBankRdBursts::3 10735 # Per bank write bursts -system.physmem.perBankRdBursts::4 13061 # Per bank write bursts -system.physmem.perBankRdBursts::5 10390 # Per bank write bursts -system.physmem.perBankRdBursts::6 11080 # Per bank write bursts -system.physmem.perBankRdBursts::7 11267 # Per bank write bursts -system.physmem.perBankRdBursts::8 10153 # Per bank write bursts -system.physmem.perBankRdBursts::9 10232 # Per bank write bursts -system.physmem.perBankRdBursts::10 10264 # Per bank write bursts -system.physmem.perBankRdBursts::11 9394 # Per bank write bursts -system.physmem.perBankRdBursts::12 10277 # Per bank write bursts -system.physmem.perBankRdBursts::13 10799 # Per bank write bursts -system.physmem.perBankRdBursts::14 10090 # Per bank write bursts -system.physmem.perBankRdBursts::15 9930 # Per bank write bursts -system.physmem.perBankWrBursts::0 8676 # Per bank write bursts -system.physmem.perBankWrBursts::1 9067 # Per bank write bursts -system.physmem.perBankWrBursts::2 9547 # Per bank write bursts -system.physmem.perBankWrBursts::3 9319 # Per bank write bursts -system.physmem.perBankWrBursts::4 8434 # Per bank write bursts -system.physmem.perBankWrBursts::5 8678 # Per bank write bursts -system.physmem.perBankWrBursts::6 9214 # Per bank write bursts -system.physmem.perBankWrBursts::7 9423 # Per bank write bursts -system.physmem.perBankWrBursts::8 8918 # Per bank write bursts -system.physmem.perBankWrBursts::9 8886 # Per bank write bursts -system.physmem.perBankWrBursts::10 8752 # Per bank write bursts -system.physmem.perBankWrBursts::11 8449 # Per bank write bursts -system.physmem.perBankWrBursts::12 8824 # Per bank write bursts -system.physmem.perBankWrBursts::13 8894 # Per bank write bursts -system.physmem.perBankWrBursts::14 8297 # Per bank write bursts -system.physmem.perBankWrBursts::15 8373 # Per bank write bursts +system.physmem.bw_total::cpu.inst 585344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3220679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6603165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170038 # Number of read requests accepted +system.physmem.writeReqs 165152 # Number of write requests accepted +system.physmem.readBursts 170038 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165152 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10876672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue +system.physmem.bytesWritten 9051328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10849188 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10306868 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23701 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4591 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10711 # Per bank write bursts +system.physmem.perBankRdBursts::1 10418 # Per bank write bursts +system.physmem.perBankRdBursts::2 10743 # Per bank write bursts +system.physmem.perBankRdBursts::3 10617 # Per bank write bursts +system.physmem.perBankRdBursts::4 13557 # Per bank write bursts +system.physmem.perBankRdBursts::5 10851 # Per bank write bursts +system.physmem.perBankRdBursts::6 10986 # Per bank write bursts +system.physmem.perBankRdBursts::7 10951 # Per bank write bursts +system.physmem.perBankRdBursts::8 10335 # Per bank write bursts +system.physmem.perBankRdBursts::9 10516 # Per bank write bursts +system.physmem.perBankRdBursts::10 10068 # Per bank write bursts +system.physmem.perBankRdBursts::11 9192 # Per bank write bursts +system.physmem.perBankRdBursts::12 10325 # Per bank write bursts +system.physmem.perBankRdBursts::13 10893 # Per bank write bursts +system.physmem.perBankRdBursts::14 9864 # Per bank write bursts +system.physmem.perBankRdBursts::15 9921 # Per bank write bursts +system.physmem.perBankWrBursts::0 8907 # Per bank write bursts +system.physmem.perBankWrBursts::1 8809 # Per bank write bursts +system.physmem.perBankWrBursts::2 9307 # Per bank write bursts +system.physmem.perBankWrBursts::3 9147 # Per bank write bursts +system.physmem.perBankWrBursts::4 8787 # Per bank write bursts +system.physmem.perBankWrBursts::5 9076 # Per bank write bursts +system.physmem.perBankWrBursts::6 9209 # Per bank write bursts +system.physmem.perBankWrBursts::7 9123 # Per bank write bursts +system.physmem.perBankWrBursts::8 9054 # Per bank write bursts +system.physmem.perBankWrBursts::9 9064 # Per bank write bursts +system.physmem.perBankWrBursts::10 8553 # Per bank write bursts +system.physmem.perBankWrBursts::11 8266 # Per bank write bursts +system.physmem.perBankWrBursts::12 8846 # Per bank write bursts +system.physmem.perBankWrBursts::13 9045 # Per bank write bursts +system.physmem.perBankWrBursts::14 8063 # Per bank write bursts +system.physmem.perBankWrBursts::15 8171 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 40 # Number of times write queue was full causing retry -system.physmem.totGap 2853441702500 # Total gap between requests +system.physmem.numWrRetry 51 # Number of times write queue was full causing retry +system.physmem.totGap 2852831352500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169486 # Read request sizes (log2) +system.physmem.readPktSize::6 169483 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160802 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160771 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,121 +159,118 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 100 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.802648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.147121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.470119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22296 36.08% 36.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14465 23.41% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6637 10.74% 70.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3539 5.73% 75.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2616 4.23% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1600 2.59% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1149 1.86% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1212 1.96% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8279 13.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.927818 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 584.509202 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5873 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 157 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.918330 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.336942 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.461853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22238 36.04% 36.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14509 23.51% 59.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6552 10.62% 70.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3615 5.86% 76.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2651 4.30% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1538 2.49% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.84% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1152 1.87% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8321 13.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61712 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.886962 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.019916 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5882 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.134684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.418054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 43.798135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5542 94.36% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 90 1.53% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 17 0.29% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 15 0.26% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 16 0.27% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 28 0.48% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 28 0.48% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.22% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 10 0.17% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 8 0.14% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 17 0.29% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 16 0.27% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 10 0.17% 98.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.039946 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.374321 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 43.145306 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5549 94.32% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 83 1.41% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 21 0.36% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 19 0.32% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 30 0.51% 96.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 24 0.41% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 22 0.37% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 15 0.25% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.19% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.05% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 21 0.36% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 13 0.22% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 9 0.15% 98.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 5 0.09% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 7 0.12% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.09% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 11 0.19% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 8 0.14% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::592-607 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads -system.physmem.totQLat 1685079736 # Total ticks spent queuing -system.physmem.totMemAccLat 4871117236 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9916.78 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.03% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 4 0.07% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.12% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.05% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.03% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.10% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 9 0.15% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 3 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 5 0.08% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 5 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads +system.physmem.totQLat 1723441444 # Total ticks spent queuing +system.physmem.totMemAccLat 4909966444 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10140.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28666.78 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28890.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -281,40 +278,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 140217 # Number of row buffer hits during reads -system.physmem.writeRowHits 109661 # Number of row buffer hits during writes +system.physmem.avgWrQLen 27.38 # Average write queue length when enqueuing +system.physmem.readRowHits 140236 # Number of row buffer hits during reads +system.physmem.writeRowHits 109426 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.35 # Row buffer hit rate for writes -system.physmem.avgGap 8512044.79 # Average gap between requests +system.physmem.writeRowHitRate 77.36 # Row buffer hit rate for writes +system.physmem.avgGap 8511087.30 # Average gap between requests system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242267760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132189750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 692507400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 468860400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83617160895 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638712655250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1910238133215 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.452112 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2726011845150 # Time in different power states -system.physmem_0.memoryStateTime::REF 95282460000 # Time in different power states +system.physmem_0.actEnergy 243129600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132660000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 692905200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 468925200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83554754445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638403001250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909828199775 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.450935 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725489926444 # Time in different power states +system.physmem_0.memoryStateTime::REF 95262180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32147776350 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32075649806 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 224857080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122689875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 632876400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 449634240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82395435150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639784344500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909982329005 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.362464 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727805815350 # Time in different power states -system.physmem_1.memoryStateTime::REF 95282460000 # Time in different power states +system.physmem_1.actEnergy 223413120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121902000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 632681400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 447521760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82328316795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639478823750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909565482905 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.358845 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727297379194 # Time in different power states +system.physmem_1.memoryStateTime::REF 95262180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30353736650 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30272102306 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -334,15 +331,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31053109 # Number of BP lookups -system.cpu.branchPred.condPredicted 16852863 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2525514 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18620216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13364906 # Number of BTB hits +system.cpu.branchPred.lookups 31016169 # Number of BP lookups +system.cpu.branchPred.condPredicted 16821620 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2509164 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18454178 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13299317 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.776321 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7853668 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1516989 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.066699 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7885459 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1501288 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -373,58 +370,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 65844 # Table walker walks requested -system.cpu.dtb.walker.walksShort 65844 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43330 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22514 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 65844 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 65844 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 65844 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7786 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8821.657087 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7338.018596 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 78.00% 78.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1707 21.92% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66365 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66365 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43579 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22786 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66365 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66365 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66365 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7796 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11013.949461 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8730.002722 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7624.437396 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6093 78.16% 78.16% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.75% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7786 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7796 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6400 82.20% 82.20% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1386 17.80% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7786 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65844 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6406 82.17% 82.17% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1390 17.83% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7796 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66365 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65844 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7786 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66365 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7796 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7786 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 73630 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7796 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74161 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24757406 # DTB read hits -system.cpu.dtb.read_misses 59085 # DTB read misses -system.cpu.dtb.write_hits 19449348 # DTB write hits -system.cpu.dtb.write_misses 6759 # DTB write misses +system.cpu.dtb.read_hits 24709745 # DTB read hits +system.cpu.dtb.read_misses 59626 # DTB read misses +system.cpu.dtb.write_hits 19412201 # DTB write hits +system.cpu.dtb.write_misses 6739 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1292 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1782 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24816491 # DTB read accesses -system.cpu.dtb.write_accesses 19456107 # DTB write accesses +system.cpu.dtb.perms_faults 733 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24769371 # DTB read accesses +system.cpu.dtb.write_accesses 19418940 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44206754 # DTB hits -system.cpu.dtb.misses 65844 # DTB misses -system.cpu.dtb.accesses 44272598 # DTB accesses +system.cpu.dtb.hits 44121946 # DTB hits +system.cpu.dtb.misses 66365 # DTB misses +system.cpu.dtb.accesses 44188311 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -454,37 +451,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5446 # Table walker walks requested -system.cpu.itb.walker.walksShort 5446 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5122 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5446 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5446 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5446 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11253.454774 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8989.562910 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7050.042435 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1281 40.23% 40.23% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1185 37.22% 77.45% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 717 22.52% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5448 # Table walker walks requested +system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5129 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11214.016933 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8947.518192 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7056.251032 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1295 40.61% 40.61% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1177 36.91% 77.52% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2875 90.30% 90.30% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.70% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5446 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5446 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8630 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57726188 # ITB inst hits -system.cpu.itb.inst_misses 5446 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8637 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57588649 # ITB inst hits +system.cpu.itb.inst_misses 5448 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -493,191 +490,209 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8450 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8467 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57731634 # ITB inst accesses -system.cpu.itb.hits 57726188 # DTB hits -system.cpu.itb.misses 5446 # DTB misses -system.cpu.itb.accesses 57731634 # DTB accesses -system.cpu.numCycles 317415724 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57594097 # ITB inst accesses +system.cpu.itb.hits 57588649 # DTB hits +system.cpu.itb.misses 5448 # DTB misses +system.cpu.itb.accesses 57594097 # DTB accesses +system.cpu.numCycles 315565701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112053421 # Number of instructions committed -system.cpu.committedOps 135485276 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7764036 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 111845135 # Number of instructions committed +system.cpu.committedOps 135229426 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7692999 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5389516808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.832718 # CPI: cycles per instruction -system.cpu.ipc 0.353018 # IPC: instructions per cycle +system.cpu.quiesceCycles 5390158471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.821452 # CPI: cycles per instruction +system.cpu.ipc 0.354427 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 228406815 # Number of cycles that the object actually ticked -system.cpu.idleCycles 89008909 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842109 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.947879 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42706608 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842621 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.683057 # Average number of references to valid blocks. +system.cpu.tickCycles 227544928 # Number of cycles that the object actually ticked +system.cpu.idleCycles 88020773 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842581 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947861 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42538360 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 843093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.455122 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.947879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947861 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176191359 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176191359 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23499832 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23499832 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18286134 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18286134 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457571 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457571 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460116 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460116 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41785966 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41785966 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41785966 # number of overall hits -system.cpu.dcache.overall_hits::total 41785966 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 583874 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 583874 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 541283 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 541283 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8366 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8366 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 175914832 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175914832 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23018220 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23018220 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18257083 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18257083 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356514 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356514 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443429 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443429 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460179 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460179 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41275303 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41275303 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41631817 # number of overall hits +system.cpu.dcache.overall_hits::total 41631817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 492255 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 492255 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 547766 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 547766 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169911 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169911 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22569 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22569 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1125157 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1125157 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1125157 # number of overall misses -system.cpu.dcache.overall_misses::total 1125157 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8774452459 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8774452459 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23299729316 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23299729316 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120081750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 120081750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1040021 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1040021 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1209932 # number of overall misses +system.cpu.dcache.overall_misses::total 1209932 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7281770758 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7281770758 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23432647284 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23432647284 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285921000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 285921000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32074181775 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32074181775 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32074181775 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32074181775 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24083706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24083706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18827417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18827417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465937 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465937 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460118 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460118 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42911123 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42911123 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42911123 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42911123 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024244 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024244 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028750 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028750 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017955 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017955 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 30714418042 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30714418042 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30714418042 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30714418042 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23510475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23510475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18804849 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18804849 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526425 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526425 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460181 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460181 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42315324 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42315324 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42841749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42841749 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020938 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020938 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029129 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029129 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322764 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.322764 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048432 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048432 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026221 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026221 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026221 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026221 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15027.989702 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15027.989702 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43045.374261 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43045.374261 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14353.544107 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14353.544107 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.024578 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024578 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028242 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14792.680131 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14792.680131 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42778.572025 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42778.572025 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12668.749169 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12668.749169 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28506.405573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28506.405573 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29532.497942 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29532.497942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25385.243172 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25385.243172 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 240 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 697919 # number of writebacks -system.cpu.dcache.writebacks::total 697919 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45195 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45195 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242825 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 242825 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 288020 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 288020 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 288020 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 288020 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538679 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 538679 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298458 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298458 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8366 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8366 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 698329 # number of writebacks +system.cpu.dcache.writebacks::total 698329 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75041 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75041 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14319 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14319 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 324082 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 324082 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 324082 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 324082 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417214 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 417214 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298725 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298725 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121762 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121762 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8250 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8250 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 837137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 837137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 837137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 837137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7251218502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7251218502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12288582898 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12288582898 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 107501250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 107501250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 715939 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 715939 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 837701 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 837701 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703446143 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703446143 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12331014162 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12331014162 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562604290 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562604290 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106206750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106206750 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19539801400 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19539801400 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19539801400 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19539801400 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836783750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836783750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510033500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510033500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346817250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346817250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015852 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015852 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017955 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017955 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18034460305 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18034460305 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19597064595 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19597064595 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836567000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836567000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510270500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510270500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346837500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346837500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017746 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017746 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015886 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015886 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231300 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231300 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.019509 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019509 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13461.112280 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13461.112280 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41173.575170 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41173.575170 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12849.778867 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12849.778867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016919 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016919 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.313419 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.313419 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41278.815506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41278.815506 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12833.267276 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12833.267276 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12873.545455 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12873.545455 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25189.939792 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25189.939792 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23393.865586 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23393.865586 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -685,58 +700,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2898605 # number of replacements -system.cpu.icache.tags.tagsinuse 511.397830 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54818221 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2899117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.908592 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15715014250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.397830 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998824 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998824 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2897467 # number of replacements +system.cpu.icache.tags.tagsinuse 511.399907 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54681814 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897979 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.868948 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15532087250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.399907 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60616478 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60616478 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54818221 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54818221 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54818221 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54818221 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54818221 # number of overall hits -system.cpu.icache.overall_hits::total 54818221 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2899129 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2899129 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2899129 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2899129 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2899129 # number of overall misses -system.cpu.icache.overall_misses::total 2899129 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39309012875 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39309012875 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39309012875 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39309012875 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39309012875 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39309012875 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57717350 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57717350 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 34950907125 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34950907125 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34950907125 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897991 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2897991 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2897991 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2897991 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2897991 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2897991 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34937740638 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34937740638 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34937740638 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34937740638 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34937740638 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34937740638 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050230 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.848565 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.848565 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96782 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65059.413288 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4045474 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162031 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66140.481134 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1055,52 +1070,52 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3579627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3579531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3579472 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579378 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 697919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 698329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2831 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295607 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804583 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506486 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15045 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158423 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8484537 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185746048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98788181 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17908 # 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Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159855 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8484970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185672448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98844821 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17796 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 282816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284817881 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61238 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4578493 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4541479 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 36488 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4542001 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36492 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4577967 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3013390750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4578493 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3014061750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4358889625 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4357263112 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1341438850 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1342100655 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10568000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10577000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 88362250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89155750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1197,23 +1212,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198914708 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198870981 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36809505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.032937 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.031296 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270823051000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.032937 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064559 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064559 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270543128000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.031296 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064456 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064456 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1227,14 +1242,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29244877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29244877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652334326 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6652334326 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29244877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29244877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29244877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29244877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6646548599 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6646548599 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1251,19 +1266,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124978.106838 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183644.388417 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183644.388417 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124978.106838 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22952 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183484.667596 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183484.667596 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22676 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3466 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.565217 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.542412 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1277,14 +1292,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16937877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16937877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768676336 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768676336 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16937877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16937877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16937877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16937877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4762888611 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4762888611 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1293,66 +1308,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72384.089744 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72384.089744 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131644.112633 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131644.112633 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131484.336655 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131484.336655 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71726 # Transaction distribution -system.membus.trans_dist::ReadResp 71726 # Transaction distribution +system.membus.trans_dist::ReadReq 71736 # Transaction distribution +system.membus.trans_dist::ReadResp 71736 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124578 # Transaction distribution +system.membus.trans_dist::Writeback 124547 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution -system.membus.trans_dist::ReadExReq 129395 # Transaction distribution -system.membus.trans_dist::ReadExResp 129395 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution +system.membus.trans_dist::ReadExReq 129383 # Transaction distribution +system.membus.trans_dist::ReadExResp 129383 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446633 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554193 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 663142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 663080 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16522776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16686485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16520600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16684309 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21321941 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 504 # Total snoops (count) -system.membus.snoop_fanout::samples 332271 # Request fanout histogram +system.membus.pkt_size::total 21319765 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 505 # Total snoops (count) +system.membus.snoop_fanout::samples 332236 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332271 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332236 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332271 # Request fanout histogram -system.membus.reqLayer0.occupancy 90362500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332236 # Request fanout histogram +system.membus.reqLayer0.occupancy 90365500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1704000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1715000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1022735199 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1025055153 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 997821410 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 997764949 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37468495 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal index b3be0ec54..ad91d76dd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal @@ -193,7 +193,7 @@ oprofile: using timer interrupt. TCP: cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 12:00:00 UTC (1230811200)
+rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
ALSA device list:
No soundcards found.
@@ -203,6 +203,6 @@ Freeing unused kernel memory: 292K (806aa000 - 806f3000)
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
starting pid 673, tty '': '/etc/rc.d/rc.local'
warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 12:00:02 UTC 2009
+Thu Jan 1 00:00:02 UTC 2009
S: devpts
-Thu Jan 1 12:00:02 UTC 2009
+Thu Jan 1 00:00:02 UTC 2009
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini index 59744d039..33618dc77 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_loader=/dist/m5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,21 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.vram system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/z/stever/hg/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -186,6 +187,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -220,6 +222,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.dtb [system.cpu0.dstage2_mmu.stage2_tlb] @@ -237,7 +240,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu0.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -645,6 +647,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -713,6 +716,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.itb [system.cpu0.istage2_mmu.stage2_tlb] @@ -730,7 +734,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu0.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -755,6 +758,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -776,19 +780,27 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu0.l2cache.tags] @@ -805,13 +817,16 @@ size=1048576 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu0.l2cache.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port [system.cpu0.tracer] type=ExeTracer @@ -906,6 +921,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -940,6 +956,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.dtb [system.cpu1.dstage2_mmu.stage2_tlb] @@ -957,7 +974,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu1.toL2Bus.slave[5] [system.cpu1.dtb] type=ArmTLB @@ -1365,6 +1381,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=1 @@ -1433,6 +1450,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.itb [system.cpu1.istage2_mmu.stage2_tlb] @@ -1450,7 +1468,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu1.toL2Bus.slave[4] [system.cpu1.itb] type=ArmTLB @@ -1475,6 +1492,7 @@ children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 @@ -1496,19 +1514,27 @@ mem_side=system.toL2Bus.slave[1] [system.cpu1.l2cache.prefetcher] type=StridePrefetcher +cache_snoop=false clk_domain=system.cpu_clk_domain -cross_pages=false -data_accesses_only=false degree=8 eventq_index=0 -inst_tagged=true latency=1 -on_miss_only=false -on_prefetch=true -on_read_only=false -serial_squash=false -size=100 +max_conf=7 +min_conf=0 +on_data=true +on_inst=true +on_miss=false +on_read=true +on_write=true +queue_filter=true +queue_size=32 +queue_squash=true +start_conf=4 sys=system +table_assoc=4 +table_sets=16 +tag_prefetch=true +thresh_conf=4 use_master_id=true [system.cpu1.l2cache.tags] @@ -1525,13 +1551,16 @@ size=1048576 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu1.l2cache.cpu_side -slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port [system.cpu1.tracer] type=ExeTracer @@ -1562,9 +1591,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=true -width=8 +width=16 default=system.realview.pciconfig.pio master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma @@ -1575,6 +1606,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -1610,6 +1642,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -1644,11 +1677,14 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side @@ -1698,7 +1734,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -2409,11 +2445,14 @@ port=3456 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false -width=8 +width=32 master=system.l2c.cpu_side slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr index 744db2c76..744db2c76 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout index b85d856c0..bc06c34c6 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout @@ -1,17 +1,17 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:35:48 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 - 0: system.cpu0.isa: ISA system set to: 0x5394b00 0x5394b00 - 0: system.cpu1.isa: ISA system set to: 0x5394b00 0x5394b00 +info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch64.20140821 + 0: system.cpu0.isa: ISA system set to: 0x3d33a20 0x3d33a20 + 0: system.cpu1.isa: ISA system set to: 0x3d33a20 0x3d33a20 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47349475204500 because m5_exit instruction encountered +Exiting @ tick 47397610926500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index f6bd584fc..ec3592c1e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.357291 # Number of seconds simulated -sim_ticks 47357290872500 # Number of ticks simulated -final_tick 47357290872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.397611 # Number of seconds simulated +sim_ticks 47397610926500 # Number of ticks simulated +final_tick 47397610926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179609 # Simulator instruction rate (inst/s) -host_op_rate 211253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9509351214 # Simulator tick rate (ticks/s) -host_mem_usage 764316 # Number of bytes of host memory used -host_seconds 4980.08 # Real time elapsed on the host -sim_insts 894465242 # Number of instructions simulated -sim_ops 1052057457 # Number of ops (including micro ops) simulated +host_inst_rate 110253 # Simulator instruction rate (inst/s) +host_op_rate 129665 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5829907242 # Simulator tick rate (ticks/s) +host_mem_usage 703216 # Number of bytes of host memory used +host_seconds 8130.08 # Real time elapsed on the host +sim_insts 896366789 # Number of instructions simulated +sim_ops 1054186264 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 141696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 131328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8696576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13989464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 21378112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 133248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 113344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3297088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7559072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 13082368 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 433472 # Number of bytes read from this memory -system.physmem.bytes_read::total 68955768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8696576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3297088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11993664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79042240 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 107072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 78336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7782464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12802520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15762560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 159744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 154688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3994240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12481056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14503040 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 448448 # Number of bytes read from this memory +system.physmem.bytes_read::total 68274168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7782464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3994240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11776704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79542656 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 79063056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2214 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 135884 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 218607 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 334033 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 51517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 118125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 204412 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6773 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1077470 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1235035 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79563472 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 121601 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 200061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 246290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2496 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 62410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 195031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 226610 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7007 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1066820 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1242854 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1237638 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 183638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 295403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 451422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 69622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 159618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 276248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1456075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 183638 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 69622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 253259 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1669062 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1245457 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 164195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 270109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 332560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 84271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 305987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1440456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 164195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 84271 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1678200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1669501 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1669062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 183638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 295842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 451422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 69622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 159618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 276248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3125576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1077470 # Number of read requests accepted -system.physmem.writeReqs 1907210 # Number of write requests accepted -system.physmem.readBursts 1077470 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1907210 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 68937984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue -system.physmem.bytesWritten 118940800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 68955768 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 121915664 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 48739 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 118611 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 58565 # Per bank write bursts -system.physmem.perBankRdBursts::1 71236 # Per bank write bursts -system.physmem.perBankRdBursts::2 60619 # Per bank write bursts -system.physmem.perBankRdBursts::3 68763 # Per bank write bursts -system.physmem.perBankRdBursts::4 63623 # Per bank write bursts -system.physmem.perBankRdBursts::5 74242 # Per bank write bursts -system.physmem.perBankRdBursts::6 69161 # Per bank write bursts -system.physmem.perBankRdBursts::7 67695 # Per bank write bursts -system.physmem.perBankRdBursts::8 61029 # Per bank write bursts -system.physmem.perBankRdBursts::9 112215 # Per bank write bursts -system.physmem.perBankRdBursts::10 55292 # Per bank write bursts -system.physmem.perBankRdBursts::11 71140 # Per bank write bursts -system.physmem.perBankRdBursts::12 63760 # Per bank write bursts -system.physmem.perBankRdBursts::13 63951 # Per bank write bursts -system.physmem.perBankRdBursts::14 57537 # Per bank write bursts -system.physmem.perBankRdBursts::15 58328 # Per bank write bursts -system.physmem.perBankWrBursts::0 113661 # Per bank write bursts -system.physmem.perBankWrBursts::1 123588 # Per bank write bursts -system.physmem.perBankWrBursts::2 119813 # Per bank write bursts -system.physmem.perBankWrBursts::3 126847 # Per bank write bursts -system.physmem.perBankWrBursts::4 114977 # Per bank write bursts -system.physmem.perBankWrBursts::5 123724 # Per bank write bursts -system.physmem.perBankWrBursts::6 117451 # Per bank write bursts -system.physmem.perBankWrBursts::7 117840 # Per bank write bursts -system.physmem.perBankWrBursts::8 112656 # Per bank write bursts -system.physmem.perBankWrBursts::9 114020 # Per bank write bursts -system.physmem.perBankWrBursts::10 109420 # Per bank write bursts -system.physmem.perBankWrBursts::11 118853 # Per bank write bursts -system.physmem.perBankWrBursts::12 108855 # Per bank write bursts -system.physmem.perBankWrBursts::13 111956 # Per bank write bursts -system.physmem.perBankWrBursts::14 111151 # Per bank write bursts -system.physmem.perBankWrBursts::15 113638 # Per bank write bursts +system.physmem.bw_write::total 1678639 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1678200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 164195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 270548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 332560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 84271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 305987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3119095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1066820 # Number of read requests accepted +system.physmem.writeReqs 1912174 # Number of write requests accepted +system.physmem.readBursts 1066820 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1912174 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68253568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22912 # Total number of bytes read from write queue +system.physmem.bytesWritten 119234048 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68274168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 122233360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 358 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49121 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 113360 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 61922 # Per bank write bursts +system.physmem.perBankRdBursts::1 70972 # Per bank write bursts +system.physmem.perBankRdBursts::2 57667 # Per bank write bursts +system.physmem.perBankRdBursts::3 64982 # Per bank write bursts +system.physmem.perBankRdBursts::4 65050 # Per bank write bursts +system.physmem.perBankRdBursts::5 70572 # Per bank write bursts +system.physmem.perBankRdBursts::6 72322 # Per bank write bursts +system.physmem.perBankRdBursts::7 67337 # Per bank write bursts +system.physmem.perBankRdBursts::8 57787 # Per bank write bursts +system.physmem.perBankRdBursts::9 110760 # Per bank write bursts +system.physmem.perBankRdBursts::10 57283 # Per bank write bursts +system.physmem.perBankRdBursts::11 63297 # Per bank write bursts +system.physmem.perBankRdBursts::12 60054 # Per bank write bursts +system.physmem.perBankRdBursts::13 63124 # Per bank write bursts +system.physmem.perBankRdBursts::14 62259 # Per bank write bursts +system.physmem.perBankRdBursts::15 61074 # Per bank write bursts +system.physmem.perBankWrBursts::0 110998 # Per bank write bursts +system.physmem.perBankWrBursts::1 120192 # Per bank write bursts +system.physmem.perBankWrBursts::2 114368 # Per bank write bursts +system.physmem.perBankWrBursts::3 118573 # Per bank write bursts +system.physmem.perBankWrBursts::4 116138 # Per bank write bursts +system.physmem.perBankWrBursts::5 119482 # Per bank write bursts +system.physmem.perBankWrBursts::6 124701 # Per bank write bursts +system.physmem.perBankWrBursts::7 122822 # Per bank write bursts +system.physmem.perBankWrBursts::8 112747 # Per bank write bursts +system.physmem.perBankWrBursts::9 113706 # Per bank write bursts +system.physmem.perBankWrBursts::10 111725 # Per bank write bursts +system.physmem.perBankWrBursts::11 114999 # Per bank write bursts +system.physmem.perBankWrBursts::12 115986 # Per bank write bursts +system.physmem.perBankWrBursts::13 114347 # Per bank write bursts +system.physmem.perBankWrBursts::14 116931 # Per bank write bursts +system.physmem.perBankWrBursts::15 115317 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 260 # Number of times write queue was full causing retry -system.physmem.totGap 47357288950000 # Total gap between requests +system.physmem.numWrRetry 309 # Number of times write queue was full causing retry +system.physmem.totGap 47397609004000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1077428 # Read request sizes (log2) +system.physmem.readPktSize::6 1066778 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1904607 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 705573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 108235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 38392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 22131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1909571 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 706521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 37446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 27253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 21077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 5735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 743 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,169 +188,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 64765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 92305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 104587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 111564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 110175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 106822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 101643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 99926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 96867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 96399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 113990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 101913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 97920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 113164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 100658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 96398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 90928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 4227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 3337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 781 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1066280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 176.199272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 107.583604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.477591 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 681708 63.93% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 204893 19.22% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51569 4.84% 87.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24658 2.31% 90.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19159 1.80% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12349 1.16% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8689 0.81% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7706 0.72% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 55549 5.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1066280 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 82344 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.080819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 137.450182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 82341 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 44683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 64606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 92963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 104605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 112793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 111359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 106848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 102432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 100351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 96443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 96232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 115397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 102859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 98750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 102100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 95328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 770 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1060336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 176.818458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 107.808098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 246.499626 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 676218 63.77% 63.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 204682 19.30% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51639 4.87% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24739 2.33% 90.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18449 1.74% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11998 1.13% 93.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8607 0.81% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7827 0.74% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 56177 5.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1060336 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 82745 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.888404 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 137.186201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 82742 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 82344 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 82344 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.569343 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.983627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.346474 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 74619 90.62% 90.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 3701 4.49% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 1617 1.96% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 776 0.94% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 389 0.47% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 290 0.35% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 467 0.57% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 184 0.22% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 57 0.07% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 20 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 62 0.08% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 36 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 12 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 2 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 5 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 10 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 13 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 9 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 24 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 82745 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 82745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.515342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.971264 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.554947 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 75024 90.67% 90.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 3669 4.43% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 1611 1.95% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 792 0.96% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 419 0.51% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 279 0.34% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 435 0.53% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 203 0.25% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 68 0.08% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 22 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 73 0.09% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 36 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 10 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 7 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 4 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 7 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 11 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 22 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 82344 # Writes before turning the bus around for reads -system.physmem.totQLat 41096385470 # Total ticks spent queuing -system.physmem.totMemAccLat 61293060470 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5385780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 38152.68 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 82745 # Writes before turning the bus around for reads +system.physmem.totQLat 40375015102 # Total ticks spent queuing +system.physmem.totMemAccLat 60371177602 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5332310000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37858.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56902.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.51 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56608.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.47 # Average write queue length when enqueuing -system.physmem.readRowHits 809420 # Number of row buffer hits during reads -system.physmem.writeRowHits 1059902 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.03 # Row buffer hit rate for writes -system.physmem.avgGap 15866789.39 # Average gap between requests -system.physmem.pageHitRate 63.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4185760320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2283897000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4164435600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6207198480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1197399382470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27364022846250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31671411386760 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.775859 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45522011263316 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581363940000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.99 # Average write queue length when enqueuing +system.physmem.readRowHits 803348 # Number of row buffer hits during reads +system.physmem.writeRowHits 1065807 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.21 # Row buffer hit rate for writes +system.physmem.avgGap 15910609.09 # Average gap between requests +system.physmem.pageHitRate 63.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4142388600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2260231875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4140419400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6138335520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1201204741230 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27384875125500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31698542432445 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.779401 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45556660870724 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582710220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 253913912184 # Time in different power states +system.physmem_0.memoryStateTime::ACT 258234748026 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3875316480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2114508000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4237256400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5835557520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1190113153695 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27370414275000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31669737933735 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.740522 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45532636458203 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581363940000 # Time in different power states +system.physmem_1.actEnergy 3873751560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2113654125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4177906200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5934111840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1188231262785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27396255369750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31696367246580 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.733509 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45575630122499 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582710220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 243288251797 # Time in different power states +system.physmem_1.memoryStateTime::ACT 239268979001 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -384,15 +384,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 151571686 # Number of BP lookups -system.cpu0.branchPred.condPredicted 107212809 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6769997 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 114323741 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 82790418 # Number of BTB hits +system.cpu0.branchPred.lookups 133516333 # Number of BP lookups +system.cpu0.branchPred.condPredicted 94941201 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6028887 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 100948341 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 73074204 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.417520 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17895403 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1177591 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.387722 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15498997 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1074405 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -423,61 +423,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 310912 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 310912 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11841 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90150 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 310912 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 310912 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 310912 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 101991 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19193.830760 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17232.192163 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15084.416179 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 100737 98.77% 98.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1058 1.04% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 58 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 274493 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 274493 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8574 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74935 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 274493 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 274493 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 274493 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 83509 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18665.041972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 16952.057368 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12810.377808 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 82824 99.18% 99.18% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 578 0.69% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 32 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 36 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 101991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 83509 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90150 88.39% 88.39% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11841 11.61% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 101991 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 310912 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 74935 89.73% 89.73% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8574 10.27% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 83509 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 274493 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 310912 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101991 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 274493 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 83509 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101991 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 412903 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 83509 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 358002 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 98035121 # DTB read hits -system.cpu0.dtb.read_misses 261233 # DTB read misses -system.cpu0.dtb.write_hits 86222704 # DTB write hits -system.cpu0.dtb.write_misses 49679 # DTB write misses +system.cpu0.dtb.read_hits 84777209 # DTB read hits +system.cpu0.dtb.read_misses 227212 # DTB read misses +system.cpu0.dtb.write_hits 75760151 # DTB write hits +system.cpu0.dtb.write_misses 47281 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 42277 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2349 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10561 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 33980 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2153 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9225 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 12531 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 98296354 # DTB read accesses -system.cpu0.dtb.write_accesses 86272383 # DTB write accesses +system.cpu0.dtb.perms_faults 11068 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 85004421 # DTB read accesses +system.cpu0.dtb.write_accesses 75807432 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 184257825 # DTB hits -system.cpu0.dtb.misses 310912 # DTB misses -system.cpu0.dtb.accesses 184568737 # DTB accesses +system.cpu0.dtb.hits 160537360 # DTB hits +system.cpu0.dtb.misses 274493 # DTB misses +system.cpu0.dtb.accesses 160811853 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,185 +507,192 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 67664 # Table walker walks requested -system.cpu0.itb.walker.walksLong 67664 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 693 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59407 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 67664 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 67664 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 67664 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 60100 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 21688.993677 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19128.313408 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17789.670668 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 55182 91.82% 91.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3533 5.88% 97.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 493 0.82% 98.52% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 740 1.23% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.03% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 25 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 48 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 24 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 60100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 61212 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61212 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 587 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52411 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 61212 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61212 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61212 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52998 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21062.649289 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19099.820516 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 14417.313367 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48615 91.73% 91.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3682 6.95% 98.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 228 0.43% 99.11% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 379 0.72% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52998 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 59407 98.85% 98.85% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 693 1.15% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 60100 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 52411 98.89% 98.89% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 587 1.11% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52998 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67664 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67664 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61212 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61212 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60100 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60100 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 127764 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 272362835 # ITB inst hits -system.cpu0.itb.inst_misses 67664 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52998 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52998 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 114210 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 238748421 # ITB inst hits +system.cpu0.itb.inst_misses 61212 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29878 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24001 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 206888 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 196095 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 272430499 # ITB inst accesses -system.cpu0.itb.hits 272362835 # DTB hits -system.cpu0.itb.misses 67664 # DTB misses -system.cpu0.itb.accesses 272430499 # DTB accesses -system.cpu0.numCycles 1079786982 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 238809633 # ITB inst accesses +system.cpu0.itb.hits 238748421 # DTB hits +system.cpu0.itb.misses 61212 # DTB misses +system.cpu0.itb.accesses 238809633 # DTB accesses +system.cpu0.numCycles 949769690 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 504924574 # Number of instructions committed -system.cpu0.committedOps 592395738 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 49310302 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4906 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93635655345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.138511 # CPI: cycles per instruction -system.cpu0.ipc 0.467615 # IPC: instructions per cycle +system.cpu0.committedInsts 439719858 # Number of instructions committed +system.cpu0.committedOps 516807751 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 45409758 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 3855 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93846100118 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.159943 # CPI: cycles per instruction +system.cpu0.ipc 0.462975 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13863 # number of quiesce instructions executed -system.cpu0.tickCycles 807512344 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 272274638 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 6269899 # number of replacements -system.cpu0.dcache.tags.tagsinuse 502.388707 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 174903450 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6270410 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.893463 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 12790 # number of quiesce instructions executed +system.cpu0.tickCycles 712933683 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 236836007 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5519291 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.702778 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 152151321 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5519802 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.564634 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.388707 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981228 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.981228 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.702778 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938873 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938873 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 207 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 371740852 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 371740852 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 90280740 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 90280740 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80064017 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80064017 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 281235 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 281235 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1931472 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1931472 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1872190 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1872190 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 170344757 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 170344757 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 170344757 # number of overall hits -system.cpu0.dcache.overall_hits::total 170344757 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 4509015 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 4509015 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2541213 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2541213 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 864871 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 864871 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 140737 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 140737 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198480 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 198480 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 7050228 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7050228 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7050228 # number of overall misses -system.cpu0.dcache.overall_misses::total 7050228 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 66986292890 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 66986292890 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47882988891 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 47882988891 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 35264024894 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 35264024894 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2028925085 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2028925085 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4179395855 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4179395855 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2760500 # 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number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2072209 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2072209 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2070670 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2070670 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 177394985 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 177394985 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 177394985 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 177394985 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047569 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.047569 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030763 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030763 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.754617 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.754617 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.067916 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.067916 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095853 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095853 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039743 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.039743 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039743 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.039743 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.081182 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.081182 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18842.571989 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18842.571989 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40773.739545 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40773.739545 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14416.429830 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14416.429830 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21057.012571 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21057.012571 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 323933952 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 323933952 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77613049 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77613049 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 70091195 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 70091195 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268191 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 268191 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 249696 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 249696 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1731388 # 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number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46218650240 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 46218650240 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32570768827 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32570768827 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2177391616 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2177391616 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3839424984 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3839424984 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3590500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3590500 # 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number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1037736 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1880339 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1880339 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1879115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1879115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 153417684 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 153417684 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154359469 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154359469 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041107 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14618.173869 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21263.277605 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21263.277605 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16292.988224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16292.988224 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16862.469903 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16862.469903 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15084.107904 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15084.107904 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -694,88 +701,96 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4374601 # number of writebacks -system.cpu0.dcache.writebacks::total 4374601 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429861 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 429861 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1046667 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1046667 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 81 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 81 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 33 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 33 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 55 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 55 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1476528 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1476528 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80025073061 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 80025073061 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5766564749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5766564749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5473208250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5473208250 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11239772999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11239772999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043034 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043034 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018093 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.754546 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.754546 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067900 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067900 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031420 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031420 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13198.751645 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13198.751645 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17520.593206 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17520.593206 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39268.456339 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39268.456339 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12907.505472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12907.505472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19498.007353 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19498.007353 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3800112 # number of writebacks +system.cpu0.dcache.writebacks::total 3800112 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429398 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 429398 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1005493 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1005493 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 83 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 83 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41403 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41403 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 51 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 51 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1434891 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1434891 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1434891 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1434891 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2897775 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2897775 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380774 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1380774 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 667964 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 667964 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 787957 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 787957 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 107548 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 107548 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180515 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 180515 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4278549 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4278549 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4946513 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4946513 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37570974686 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37570974686 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 24854865946 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 24854865946 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14971801156 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14971801156 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31379224673 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31379224673 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1379388880 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1379388880 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3557992992 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3557992992 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2840500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 62425840632 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 62425840632 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77397641788 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 77397641788 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5923264746 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5923264746 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5701581250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5701581250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11624845996 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11624845996 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019051 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019051 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.709253 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.709253 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759304 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759304 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057196 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057196 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096064 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096064 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027888 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027888 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032045 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032045 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12965.456147 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12965.456147 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18000.676393 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18000.676393 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22414.083927 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22414.083927 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39823.524219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39823.524219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12825.797597 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12825.797597 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19710.234562 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19710.234562 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14590.423209 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14590.423209 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15646.909608 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15646.909608 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -783,57 +798,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 10307657 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.930132 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 261841431 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 10308169 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 25.401352 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 23262861250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930132 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 9444901 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.930140 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 229100961 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9445413 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.255261 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930140 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 554607398 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 554607398 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 261841431 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 261841431 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 261841431 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 261841431 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 261841431 # number of overall hits -system.cpu0.icache.overall_hits::total 261841431 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 10308179 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 10308179 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 10308179 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 10308179 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 10308179 # number of overall misses -system.cpu0.icache.overall_misses::total 10308179 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 103403812050 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 103403812050 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 103403812050 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 103403812050 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 103403812050 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 103403812050 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 272149610 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 272149610 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 272149610 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 272149610 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 272149610 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 272149610 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037877 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.037877 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037877 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.037877 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037877 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.037877 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.239470 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.239470 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10031.239470 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10031.239470 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 486538188 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 486538188 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 229100961 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 229100961 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 229100961 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 229100961 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 229100961 # number of overall hits +system.cpu0.icache.overall_hits::total 229100961 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9445422 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9445422 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9445422 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9445422 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9445422 # number of overall misses +system.cpu0.icache.overall_misses::total 9445422 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93680049293 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 93680049293 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 93680049293 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 93680049293 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 93680049293 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 93680049293 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 238546383 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 238546383 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 238546383 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 238546383 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 238546383 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 238546383 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039596 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039596 # 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number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -842,238 +858,241 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10308179 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 10308179 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 10308179 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 10308179 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 10308179 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 10308179 # 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number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037877 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.037877 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.037877 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9027.919133 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039596 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039596 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039596 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8915.044680 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8915.044680 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8915.044680 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 12908052 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 12916183 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7100 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7452732 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7456615 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 3365 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1498641 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 3094586 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16261.036528 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 17187399 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3110668 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.525308 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 953257 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2717195 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16004.441587 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15093815 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2732791 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.523223 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6030.877634 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.708580 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.789449 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5140.303922 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2691.250303 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2256.106640 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.368096 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004072 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004626 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.313739 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.164261 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.137702 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2268 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13711 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 410 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1208 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 648 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3981 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4660 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3950 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.138428 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.836853 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 360310183 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 93445363825 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5508458001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9899528751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5233419500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5233419500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5656823753 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10047894503 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452375000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5452375000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10741877501 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15132948251 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.186574 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.109364 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11109198753 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15500269503 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.266241 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.127536 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.725161 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.725161 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.628747 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.628747 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793519 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.793519 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.741477 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.741477 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.538902 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.538902 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.817105 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817105 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.210133 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.210133 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.117225 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224862 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224862 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135114 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186936 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29763.331275 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26938.772911 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44997.202450 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43674.769924 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43674.769924 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20418.408310 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20418.408310 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15115.924084 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15115.924084 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 389899.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 389899.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41290.896998 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41290.896998 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28945.720413 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34931.503009 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.184057 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26709.503385 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25473.948849 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 52502.734204 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43489.607650 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43489.607650 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20266.143903 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20266.143903 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.483112 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.483112 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1165000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1165000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39938.078665 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39938.078665 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27348.089069 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34037.079428 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1229,66 +1252,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 17791242 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 15586246 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31969 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31969 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4374599 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1496771 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1185210 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 863337 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 459789 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354172 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 478714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1428335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1300035 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20720970 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18253192 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 368054 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1214499 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 40556715 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 663070976 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 695774006 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328184 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4426744 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1364599910 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5020747 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27005623 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.173372 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.378569 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 16517621 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14068332 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3800110 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1086057 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1148168 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786224 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 477409 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332434 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 482483 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1303516 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1171227 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18995457 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16182353 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 335795 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1061304 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 36574909 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607854592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 610383865 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1223600 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3866424 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1223328481 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4849156 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24579773 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.184734 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.388082 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 22323591 82.66% 82.66% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 4682032 17.34% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 20039056 81.53% 81.53% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 4540717 18.47% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27005623 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 16474086937 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 24579773 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14682015163 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 218344490 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 205334987 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 15570026567 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14272912820 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9017811583 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7968080178 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 202360718 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 183071466 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 661550198 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 578323929 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 120391711 # Number of BP lookups -system.cpu1.branchPred.condPredicted 86208358 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5520869 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91435615 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 66348303 # Number of BTB hits +system.cpu1.branchPred.lookups 139172899 # Number of BP lookups +system.cpu1.branchPred.condPredicted 99233401 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6252869 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 105205307 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 76618629 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.562866 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 13861535 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 936317 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.827722 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16237430 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1026400 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1318,67 +1342,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 259478 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 259478 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8847 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78200 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 259478 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 259478 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 259478 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 87047 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19103.472745 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17330.859199 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14131.069495 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 82878 95.21% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3197 3.67% 98.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 459 0.53% 99.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 357 0.41% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 35 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 16 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 26 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 28 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 87047 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 492358444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 492358444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 492358444 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 78200 89.84% 89.84% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8847 10.16% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 87047 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259478 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 295412 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 295412 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11437 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91734 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 295412 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 295412 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 295412 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 103171 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19450.829041 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17494.566732 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15964.350233 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 101752 98.62% 98.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1198 1.16% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 80 0.08% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 103171 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 91734 88.91% 88.91% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11437 11.09% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 103171 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 295412 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259478 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87047 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 295412 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103171 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87047 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 346525 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103171 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 398583 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 76628852 # DTB read hits -system.cpu1.dtb.read_misses 212787 # DTB read misses -system.cpu1.dtb.write_hits 67332330 # DTB write hits -system.cpu1.dtb.write_misses 46691 # DTB write misses +system.cpu1.dtb.read_hits 90130445 # DTB read hits +system.cpu1.dtb.read_misses 246227 # DTB read misses +system.cpu1.dtb.write_hits 78064785 # DTB write hits +system.cpu1.dtb.write_misses 49185 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 32755 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 660 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6687 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 41873 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 864 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7939 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10091 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 76841639 # DTB read accesses -system.cpu1.dtb.write_accesses 67379021 # DTB write accesses +system.cpu1.dtb.perms_faults 11435 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90376672 # DTB read accesses +system.cpu1.dtb.write_accesses 78113970 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 143961182 # DTB hits -system.cpu1.dtb.misses 259478 # DTB misses -system.cpu1.dtb.accesses 144220660 # DTB accesses +system.cpu1.dtb.hits 168195230 # DTB hits +system.cpu1.dtb.misses 295412 # DTB misses +system.cpu1.dtb.accesses 168490642 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1408,178 +1427,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 59975 # Table walker walks requested -system.cpu1.itb.walker.walksLong 59975 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 467 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50555 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 59975 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 59975 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 59975 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 51022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21947.479421 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19426.626910 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17730.380785 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 49865 97.73% 97.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1035 2.03% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.09% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 68039 # Table walker walks requested +system.cpu1.itb.walker.walksLong 68039 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 556 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57997 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 68039 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 68039 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 68039 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 58553 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 22020.763957 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19263.180418 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18942.782929 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 56928 97.22% 97.22% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1459 2.49% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 45 0.08% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 89 0.15% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 51022 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 491673944 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 491673944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 491673944 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 50555 99.08% 99.08% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 467 0.92% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 51022 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 58553 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57997 99.05% 99.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 556 0.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 58553 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59975 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59975 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68039 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68039 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51022 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51022 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 110997 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 214508261 # ITB inst hits -system.cpu1.itb.inst_misses 59975 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58553 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58553 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 126592 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 249268487 # ITB inst hits +system.cpu1.itb.inst_misses 68039 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 23598 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 30522 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 213038 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 226060 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 214568236 # ITB inst accesses -system.cpu1.itb.hits 214508261 # DTB hits -system.cpu1.itb.misses 59975 # DTB misses -system.cpu1.itb.accesses 214568236 # DTB accesses -system.cpu1.numCycles 819770260 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 249336526 # ITB inst accesses +system.cpu1.itb.hits 249268487 # DTB hits +system.cpu1.itb.misses 68039 # DTB misses +system.cpu1.itb.accesses 249336526 # DTB accesses +system.cpu1.numCycles 932637373 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 389540668 # Number of instructions committed -system.cpu1.committedOps 459661719 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 43651844 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93895466763 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.104454 # CPI: cycles per instruction -system.cpu1.ipc 0.475183 # IPC: instructions per cycle +system.cpu1.committedInsts 456646931 # Number of instructions committed +system.cpu1.committedOps 537378513 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 48077866 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5781 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93863478723 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.042360 # CPI: cycles per instruction +system.cpu1.ipc 0.489630 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5089 # number of quiesce instructions executed -system.cpu1.tickCycles 643812229 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 175958031 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 4705434 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.508572 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 136862260 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4705946 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.082837 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379321114000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.508572 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.813493 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.813493 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5811 # number of quiesce instructions executed +system.cpu1.tickCycles 738281563 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 194355810 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5504177 # number of replacements +system.cpu1.dcache.tags.tagsinuse 462.121005 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 159889231 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5504689 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.046006 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 462.121005 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.902580 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.902580 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 290353323 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 290353323 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 70292866 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 70292866 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 62721831 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 62721831 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 37138 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 37138 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1710890 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1710890 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1626994 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1626994 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 133014697 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 133014697 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 133014697 # number of overall hits -system.cpu1.dcache.overall_hits::total 133014697 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3624776 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3624776 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2086736 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2086736 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 382666 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 382666 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 105529 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 105529 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 188259 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 188259 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5711512 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5711512 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5711512 # number of overall misses -system.cpu1.dcache.overall_misses::total 5711512 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50593739173 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 50593739173 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36769582633 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 36769582633 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 10366896775 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 10366896775 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1534806603 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1534806603 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3974138991 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3974138991 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3324999 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3324999 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 87363321806 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 87363321806 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 87363321806 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 87363321806 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 73917642 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 73917642 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 64808567 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 64808567 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 419804 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 419804 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1816419 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1816419 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1815253 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1815253 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 138726209 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 138726209 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 138726209 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 138726209 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049038 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049038 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032198 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.032198 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.911535 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.911535 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.058097 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.058097 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103710 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103710 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041171 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.041171 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041171 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041171 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13957.756058 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13957.756058 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17620.620257 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17620.620257 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27091.240860 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27091.240860 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14543.932028 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14543.932028 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21109.954855 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21109.954855 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 339217340 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 339217340 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 82545716 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 82545716 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 72881068 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 72881068 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 234096 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 234096 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 75438 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 75438 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1844359 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1844359 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1835233 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1835233 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 155426784 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 155426784 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 155660880 # number of overall hits +system.cpu1.dcache.overall_hits::total 155660880 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3601145 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3601145 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2300638 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2300638 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 662253 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 662253 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 453115 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 453115 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186074 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 186074 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193760 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 193760 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5901783 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5901783 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6564036 # number of overall misses +system.cpu1.dcache.overall_misses::total 6564036 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55051091271 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 55051091271 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39953352540 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 39953352540 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12827340347 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12827340347 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2834422928 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2834422928 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4003287927 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4003287927 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3321500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3321500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 95004443811 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 95004443811 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 95004443811 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 95004443811 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 86146861 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 86146861 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75181706 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 75181706 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 896349 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 896349 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 528553 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 528553 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2030433 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2030433 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2028993 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2028993 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 161328567 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 161328567 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 162224916 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 162224916 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041802 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.041802 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030601 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030601 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.738834 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.738834 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.857274 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.857274 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091643 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091643 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095496 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095496 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036582 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.036582 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040463 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040463 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15287.107648 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15287.107648 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17366.205609 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17366.205609 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28309.237935 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28309.237935 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15232.772596 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15232.772596 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20661.064859 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20661.064859 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15296.005997 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15296.005997 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16097.583359 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16097.583359 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14473.480007 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14473.480007 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1588,88 +1616,96 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3043303 # number of writebacks -system.cpu1.dcache.writebacks::total 3043303 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 326021 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 326021 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 860988 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 860988 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 76 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 76 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 32 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 53 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1187009 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1187009 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1187009 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1187009 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3298755 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3298755 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1225748 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1225748 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 382590 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 382590 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105497 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105497 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 188206 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 188206 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4524503 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4524503 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4524503 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4524503 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40628902084 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40628902084 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20156955784 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20156955784 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9784547475 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 9784547475 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1375359879 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1375359879 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3682414982 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3682414982 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2828501 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2828501 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60785857868 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 60785857868 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60785857868 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 60785857868 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 684362251 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 684362251 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 814922500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 814922500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1499284751 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1499284751 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044627 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044627 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018913 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018913 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.911354 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.911354 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058080 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058080 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103680 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103680 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032615 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032615 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12316.435165 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12316.435165 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16444.616499 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16444.616499 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25574.498745 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25574.498745 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13036.957250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13036.957250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19565.874531 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19565.874531 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3506045 # number of writebacks +system.cpu1.dcache.writebacks::total 3506045 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 409825 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 409825 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 940543 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 940543 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 72 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 72 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45181 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45181 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1350368 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1350368 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1350368 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1350368 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3191320 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3191320 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1360095 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1360095 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 661949 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 661949 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 453043 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 453043 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 140893 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 140893 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193713 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193713 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4551415 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4551415 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5213364 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5213364 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42631813644 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42631813644 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22019784779 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22019784779 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605448576 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605448576 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12141090903 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12141090903 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1806083972 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1806083972 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3702335044 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3702335044 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2795500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2795500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64651598423 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 64651598423 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78257046999 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 78257046999 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 498907500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 498907500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 556628501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 556628501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1055536001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1055536001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037045 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037045 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.738495 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.738495 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.857138 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.857138 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069391 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069391 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095472 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095472 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028212 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028212 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032137 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032137 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.677176 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.677176 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16189.887309 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16189.887309 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20553.620560 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20553.620560 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26798.981340 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26798.981340 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12818.833952 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.833952 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19112.475900 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19112.475900 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14204.724997 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14204.724997 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15010.854220 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15010.854220 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1677,58 +1713,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 8513181 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.039853 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 205775695 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8513693 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.169969 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8369241421000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.039853 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990312 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990312 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 9392574 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.206734 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 239643264 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9393086 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.512730 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8370013399000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.206734 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990638 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990638 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 437092471 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 437092471 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 205775695 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 205775695 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 205775695 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 205775695 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 205775695 # number of overall hits -system.cpu1.icache.overall_hits::total 205775695 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8513694 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8513694 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8513694 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8513694 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8513694 # number of overall misses -system.cpu1.icache.overall_misses::total 8513694 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84159322077 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 84159322077 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 84159322077 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 84159322077 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 84159322077 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 84159322077 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 214289389 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 214289389 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 214289389 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 214289389 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 214289389 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 214289389 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039730 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.039730 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039730 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.039730 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039730 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.039730 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9885.171123 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9885.171123 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9885.171123 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9885.171123 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 507465788 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 507465788 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 239643264 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 239643264 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 239643264 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 239643264 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 239643264 # number of overall hits +system.cpu1.icache.overall_hits::total 239643264 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9393087 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9393087 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9393087 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 9393087 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 9393087 # number of overall misses +system.cpu1.icache.overall_misses::total 9393087 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93629377858 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 93629377858 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 93629377858 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 93629377858 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 93629377858 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 93629377858 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 249036351 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 249036351 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 249036351 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 249036351 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 249036351 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 249036351 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037718 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037718 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037718 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037718 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037718 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037718 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9967.902763 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9967.902763 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9967.902763 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9967.902763 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1737,241 +1773,236 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8513694 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8513694 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8513694 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8513694 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8513694 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8513694 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75624287377 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 75624287377 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75624287377 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 75624287377 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75624287377 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 75624287377 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8552000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8552000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8552000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8552000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039730 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.039730 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.039730 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8882.664491 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9393087 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 9393087 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 9393087 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 9393087 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 9393087 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 9393087 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 84210400586 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 84210400586 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 84210400586 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 84210400586 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 84210400586 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 84210400586 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8117000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8117000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8117000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8117000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037718 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.037718 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.037718 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8965.146451 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8965.146451 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8965.146451 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 10121407 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 10125724 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 3757 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7598599 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7600232 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 1400 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 1112844 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2221085 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13329.151476 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 13836589 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2237248 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.184647 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10494820402000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5280.158493 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.775550 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 82.006725 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3962.886937 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2390.470426 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.853345 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.322275 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004564 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.241875 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.145903 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093924 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.813547 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2457 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13645 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 113 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 719 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 972 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 645 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 937 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4967 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4448 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3191 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.149963 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832825 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 282497183 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 282497183 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 472812 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141552 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7799132 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2711848 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 11125344 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3043302 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3043302 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 157363 # 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number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 985933999 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.261514 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133003 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.587342 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.587342 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.665364 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.665364 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827885 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.827885 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.582696 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.582696 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.656981 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.656981 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784553 # 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mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207555 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207555 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138603 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191906 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 23524.613506 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23038.594142 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36143.355229 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30445.827572 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30445.827572 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19406.762982 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.762982 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14569.405435 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14569.405435 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 393582.833333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 393582.833333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31760.741811 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31760.741811 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24293.872687 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28557.983969 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186252 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26660.088082 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25037.672304 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46384.470766 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32812.266011 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32812.266011 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19486.318153 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19486.318153 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14796.710109 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14796.710109 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33792.425824 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33792.425824 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26022.436146 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31231.631271 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2131,63 +2158,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 15445485 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 12769085 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6630 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6630 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3043303 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1203167 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105360 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 381381 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 459466 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345603 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 466676 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1177489 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1018273 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17027569 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13630896 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 329758 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1060916 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32049139 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544882176 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 508019480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1204400 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3883720 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1057989776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5539420 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22773399 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.231012 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.421480 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 16687989 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 14334572 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4962 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4962 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3506045 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1053826 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1133141 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 451918 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 452249 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341136 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 469204 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1304040 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1151075 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18786353 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15676887 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371904 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1206650 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36041794 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 601163264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587975003 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349240 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4407712 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1194895219 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5002181 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 24473447 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.192626 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.394362 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 17512462 76.90% 76.90% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 5260937 23.10% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 19759234 80.74% 80.74% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 4714213 19.26% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22773399 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 12190933688 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 24473447 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 13845201909 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175938985 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 163397980 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12781364350 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 14102728136 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7076644304 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8209870082 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 179556153 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 203661942 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 575808723 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 656138927 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40350 # Transaction distribution -system.iobus.trans_dist::ReadResp 40350 # Transaction distribution -system.iobus.trans_dist::WriteReq 136657 # Transaction distribution -system.iobus.trans_dist::WriteResp 29929 # Transaction distribution +system.iobus.trans_dist::ReadReq 40316 # Transaction distribution +system.iobus.trans_dist::ReadResp 40316 # Transaction distribution +system.iobus.trans_dist::WriteReq 136601 # Transaction distribution +system.iobus.trans_dist::WriteResp 29873 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47838 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47648 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2202,13 +2229,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122720 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122530 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47858 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47668 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2223,13 +2250,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496658 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36180000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2257,71 +2284,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 607629108 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607453407 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92660000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148521376 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148582123 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115588 # number of replacements -system.iocache.tags.tagsinuse 11.296723 # Cycle average of tags in use +system.iocache.tags.replacements 115592 # number of replacements +system.iocache.tags.tagsinuse 11.295153 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115604 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9128912382000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841062 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.455661 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240066 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465979 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706045 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9129697263000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.412327 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.882827 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463270 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242677 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705947 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040820 # Number of tag accesses -system.iocache.tags.data_accesses 1040820 # Number of data accesses +system.iocache.tags.tag_accesses 1040865 # Number of tag accesses +system.iocache.tags.data_accesses 1040865 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8884 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8921 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses -system.iocache.demand_misses::total 8919 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8884 # number of demand (read+write) misses +system.iocache.demand_misses::total 8924 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8879 # number of overall misses -system.iocache.overall_misses::total 8919 # number of overall misses +system.iocache.overall_misses::realview.ide 8884 # number of overall misses +system.iocache.overall_misses::total 8924 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1619625499 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1624820999 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1659251745 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1664447245 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871885233 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19871885233 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19947928539 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19947928539 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1619625499 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1625189999 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1659251745 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1664816245 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1619625499 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1625189999 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1659251745 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1664816245 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8884 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8921 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8884 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8924 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8884 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8924 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2336,54 +2363,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182410.800653 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182236.540938 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186768.544012 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186576.308149 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186191.863738 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 186191.863738 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186904.360046 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186904.360046 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 182216.616100 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186768.544012 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186554.935567 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 182216.616100 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 110413 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 186768.544012 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186554.935567 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 112960 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16202 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16486 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.814776 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.851874 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106678 # number of writebacks +system.iocache.writebacks::total 106678 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8884 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8921 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8884 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8924 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8884 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8924 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1156744203 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1160014703 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1196099891 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1199370391 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14321981281 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14321981281 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14397972639 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14397972639 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1156744203 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1160227703 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1196099891 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1199583391 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1156744203 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1160227703 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1196099891 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1199583391 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2398,563 +2425,560 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130278.657844 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130104.834343 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134635.287145 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134443.491873 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.414446 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.414446 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134903.424022 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134903.424022 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 134422.163940 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 134422.163940 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1509391 # number of replacements -system.l2c.tags.tagsinuse 64395.788312 # Cycle average of tags in use -system.l2c.tags.total_refs 5071928 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1569787 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.230966 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8741120000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18420.928371 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 254.564671 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 327.558520 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5783.699822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9967.407270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17191.318601 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 126.325801 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 133.881896 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2759.726372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3037.353013 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6393.023977 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.281081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003884 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004998 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.088252 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.152091 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.262319 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001928 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042110 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.046346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097550 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.982602 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 14050 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 46146 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1105 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 12755 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4647 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 39226 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.214386 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.704132 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65830537 # Number of tag accesses -system.l2c.tags.data_accesses 65830537 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 7044 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4822 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 775995 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 424099 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 575063 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4575 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 662903 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 363815 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 472407 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3297275 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2504876 # number of Writeback hits -system.l2c.Writeback_hits::total 2504876 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 140601 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 125515 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 266116 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 34998 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 27403 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 62401 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7236 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5610 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12846 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55428 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53807 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109235 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 775995 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 479527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 575063 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4575 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 662903 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 417622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 472407 # number of demand (read+write) hits -system.l2c.demand_hits::total 3406510 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7044 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4822 # number of overall hits -system.l2c.overall_hits::cpu0.inst 775995 # number of overall hits -system.l2c.overall_hits::cpu0.data 479527 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 575063 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6552 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4575 # number of overall hits -system.l2c.overall_hits::cpu1.inst 662903 # number of overall hits -system.l2c.overall_hits::cpu1.data 417622 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 472407 # number of overall hits -system.l2c.overall_hits::total 3406510 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2214 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2052 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 83747 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 137620 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 334397 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2082 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1771 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 51652 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 69122 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 204701 # number of ReadReq misses -system.l2c.ReadReq_misses::total 889358 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 476508 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 89488 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 565996 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 48344 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 44372 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 92716 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10817 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7620 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18437 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 83374 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50998 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 134372 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2214 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2052 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 83747 # 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Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1548603 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.239898 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8811587000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 16300.231028 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.590542 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 5.410855 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3923.984358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5628.040249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3900.550479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 368.152358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 516.465158 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.190900 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.212817 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.765143 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.484776 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.678929 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.600521 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586709 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.593738 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.596623 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.586703 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591741 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.575848 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.512878 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.547492 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.231370 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.231370 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80848.279354 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77016.382199 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 99617.771443 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33583.928144 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32063.710201 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33250.137211 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17840.886677 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.886334 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17819.536552 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17860.137471 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.412203 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17840.755008 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77480.654562 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72287.514629 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75289.979524 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2969,58 +2993,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 988965 # Transaction distribution -system.membus.trans_dist::ReadResp 988965 # Transaction distribution -system.membus.trans_dist::WriteReq 38599 # Transaction distribution -system.membus.trans_dist::WriteResp 38599 # Transaction distribution -system.membus.trans_dist::Writeback 1235035 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 669572 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 669572 # Transaction distribution -system.membus.trans_dist::UpgradeReq 443245 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 300309 # Transaction distribution -system.membus.trans_dist::UpgradeResp 118634 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution -system.membus.trans_dist::ReadExReq 147271 # Transaction distribution -system.membus.trans_dist::ReadExResp 130046 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122720 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 979077 # Transaction distribution +system.membus.trans_dist::ReadResp 979077 # Transaction distribution +system.membus.trans_dist::WriteReq 38187 # Transaction distribution +system.membus.trans_dist::WriteResp 38187 # Transaction distribution +system.membus.trans_dist::Writeback 1242854 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 666717 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 666717 # Transaction distribution +system.membus.trans_dist::UpgradeReq 428866 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 287024 # Transaction distribution +system.membus.trans_dist::UpgradeResp 113399 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 145453 # Transaction distribution +system.membus.trans_dist::ReadExResp 128623 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122530 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26568 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5280771 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5430111 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5765953 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5227832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5375480 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336065 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336065 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5711545 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155660 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176778952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 176989262 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14092480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14092480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191081742 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 645066 # Total snoops (count) -system.membus.snoop_fanout::samples 3693594 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176401096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 176608212 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14106432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14106432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190714644 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 622043 # Total snoops (count) +system.membus.snoop_fanout::samples 3659684 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3693594 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3659684 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3693594 # Request fanout histogram -system.membus.reqLayer0.occupancy 110078000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3659684 # Request fanout histogram +system.membus.reqLayer0.occupancy 109555497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22086998 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20982498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11288947920 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11300972211 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6557942197 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6484776493 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151922124 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151978377 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3064,45 +3088,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 5164890 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5157651 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38599 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38599 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2504876 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 938982 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 832112 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 498168 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 313155 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 811323 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 114 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 303337 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 303337 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8953428 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6273029 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15226457 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302864374 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 197929240 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 500793614 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1680481 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9632863 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012020 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.108976 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5072106 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5064869 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38187 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38187 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2487202 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 936242 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 829317 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 482057 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 299353 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 781410 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 127 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 300573 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 300573 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8029813 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6984147 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15013960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269549433 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 226408539 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 495957972 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1618057 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9487188 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012211 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.109827 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9517074 98.80% 98.80% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115789 1.20% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9371339 98.78% 98.78% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115849 1.22% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9632863 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8806822228 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9487188 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8381122122 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2527500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5125474266 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4575963989 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4045471741 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4435446795 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal index f1314d2a7..04cd08c82 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000019] Console: colour dummy device 80x25
-[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000022] pid_max: default: 32768 minimum: 301
-[ 0.000033] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000034] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000131] hw perfevents: no hardware support available
-[ 0.060036] CPU1: Booted secondary processor
-[ 1.080071] CPU2: failed to come online
-[ 2.100137] CPU3: failed to come online
-[ 2.100139] Brought up 2 CPUs
-[ 2.100140] SMP: Total of 2 processors activated.
-[ 2.100190] devtmpfs: initialized
-[ 2.100793] atomic64_test: passed
-[ 2.100838] regulator-dummy: no parameters
-[ 2.101214] NET: Registered protocol family 16
-[ 2.101343] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101351] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.101748] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.101750] Serial: AMBA PL011 UART driver
-[ 2.101922] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.101956] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.102494] console [ttyAMA0] enabled
-[ 2.102553] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.102585] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.102617] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.102647] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.140272] 3V3: 3300 mV
-[ 2.140314] vgaarb: loaded
-[ 2.140359] SCSI subsystem initialized
-[ 2.140388] libata version 3.00 loaded.
-[ 2.140440] usbcore: registered new interface driver usbfs
-[ 2.140458] usbcore: registered new interface driver hub
-[ 2.140480] usbcore: registered new device driver usb
-[ 2.140506] pps_core: LinuxPPS API ver. 1 registered
-[ 2.140514] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.140532] PTP clock support registered
-[ 2.140657] Switched to clocksource arch_sys_counter
-[ 2.141767] NET: Registered protocol family 2
-[ 2.141832] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.141848] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.141863] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.141883] TCP: reno registered
-[ 2.141889] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141901] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.141933] NET: Registered protocol family 1
-[ 2.141985] RPC: Registered named UNIX socket transport module.
-[ 2.141995] RPC: Registered udp transport module.
-[ 2.142003] RPC: Registered tcp transport module.
-[ 2.142011] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.142022] PCI: CLS 0 bytes, default 64
-[ 2.142178] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.142262] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.144252] fuse init (API version 7.23)
-[ 2.144348] msgmni has been set to 469
-[ 2.144441] io scheduler noop registered
-[ 2.144502] io scheduler cfq registered (default)
-[ 2.144877] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.144889] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.144900] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.144912] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.144921] pci_bus 0000:00: scanning bus
-[ 2.144930] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.144942] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.144956] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.144993] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.145004] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.145014] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.145025] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.145035] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.145045] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.145056] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.145094] pci_bus 0000:00: fixups for bus
-[ 2.145101] pci_bus 0000:00: bus scan returning with max=00
-[ 2.145112] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.145130] pci 0000:00:00.0: fixup irq: got 33
-[ 2.145138] pci 0000:00:00.0: assigning IRQ 33
-[ 2.145148] pci 0000:00:01.0: fixup irq: got 34
-[ 2.145156] pci 0000:00:01.0: assigning IRQ 34
-[ 2.145166] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.145178] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.145191] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.145203] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.145214] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.145225] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.145236] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.145246] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.145736] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.145999] ata_piix 0000:00:01.0: version 2.13
-[ 2.146009] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.146029] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.146283] scsi0 : ata_piix
-[ 2.146361] scsi1 : ata_piix
-[ 2.146393] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.146405] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.146514] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.146526] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.146540] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.146551] e1000 0000:00:00.0: enabling bus mastering
-[ 2.290688] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.290697] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.290723] ata1.00: configured for UDMA/33
-[ 2.290764] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.290877] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.290883] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.290933] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.290942] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.290962] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.291097] sda: sda1
-[ 2.291216] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.410964] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.410977] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.411000] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.411009] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.411031] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.411042] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.411120] usbcore: registered new interface driver usb-storage
-[ 2.411175] mousedev: PS/2 mouse device common for all mice
-[ 2.411347] usbcore: registered new interface driver usbhid
-[ 2.411357] usbhid: USB HID core driver
-[ 2.411384] TCP: cubic registered
-[ 2.411391] NET: Registered protocol family 17
- -[ 2.411738] devtmpfs: mounted
-[ 2.411771] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000024] Console: colour dummy device 80x25
+[ 0.000026] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000028] pid_max: default: 32768 minimum: 301
+[ 0.000040] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000041] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000162] hw perfevents: no hardware support available
+[ 0.060041] CPU1: Booted secondary processor
+[ 1.080077] CPU2: failed to come online
+[ 2.100147] CPU3: failed to come online
+[ 2.100150] Brought up 2 CPUs
+[ 2.100151] SMP: Total of 2 processors activated.
+[ 2.100222] devtmpfs: initialized
+[ 2.100720] atomic64_test: passed
+[ 2.100765] regulator-dummy: no parameters
+[ 2.101110] NET: Registered protocol family 16
+[ 2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.101774] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.101778] Serial: AMBA PL011 UART driver
+[ 2.101977] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.102014] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.102559] console [ttyAMA0] enabled
+[ 2.102714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.102776] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.102840] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.102896] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.140326] 3V3: 3300 mV
+[ 2.140386] vgaarb: loaded
+[ 2.140451] SCSI subsystem initialized
+[ 2.140500] libata version 3.00 loaded.
+[ 2.140582] usbcore: registered new interface driver usbfs
+[ 2.140606] usbcore: registered new interface driver hub
+[ 2.140634] usbcore: registered new device driver usb
+[ 2.140679] pps_core: LinuxPPS API ver. 1 registered
+[ 2.140690] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.140713] PTP clock support registered
+[ 2.140890] Switched to clocksource arch_sys_counter
+[ 2.142410] NET: Registered protocol family 2
+[ 2.142497] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.142513] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.142530] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.142553] TCP: reno registered
+[ 2.142559] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.142571] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.142606] NET: Registered protocol family 1
+[ 2.142648] RPC: Registered named UNIX socket transport module.
+[ 2.142658] RPC: Registered udp transport module.
+[ 2.142666] RPC: Registered tcp transport module.
+[ 2.142674] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.142686] PCI: CLS 0 bytes, default 64
+[ 2.142917] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.143025] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.145169] fuse init (API version 7.23)
+[ 2.145284] msgmni has been set to 469
+[ 2.145389] io scheduler noop registered
+[ 2.145440] io scheduler cfq registered (default)
+[ 2.145841] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.145854] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.145865] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.145877] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.145887] pci_bus 0000:00: scanning bus
+[ 2.145897] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.145910] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.145924] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.145958] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.145969] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.145980] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.145990] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.146000] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.146011] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.146022] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.146056] pci_bus 0000:00: fixups for bus
+[ 2.146064] pci_bus 0000:00: bus scan returning with max=00
+[ 2.146076] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.146095] pci 0000:00:00.0: fixup irq: got 33
+[ 2.146103] pci 0000:00:00.0: assigning IRQ 33
+[ 2.146113] pci 0000:00:01.0: fixup irq: got 34
+[ 2.146121] pci 0000:00:01.0: assigning IRQ 34
+[ 2.146133] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.146145] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.146158] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.146170] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.146181] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.146192] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.146203] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.146214] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.146861] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.147132] ata_piix 0000:00:01.0: version 2.13
+[ 2.147142] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.147165] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.147427] scsi0 : ata_piix
+[ 2.147508] scsi1 : ata_piix
+[ 2.147536] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.147548] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.147650] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.147662] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.147676] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.147687] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290931] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290941] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.290968] ata1.00: configured for UDMA/33
+[ 2.291021] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.291157] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.291201] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.291210] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.291229] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.291303] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291385] sda: sda1
+[ 2.291511] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.411191] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.411204] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.411225] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.411235] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.411255] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.411267] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.411336] usbcore: registered new interface driver usb-storage
+[ 2.411399] mousedev: PS/2 mouse device common for all mice
+[ 2.411553] usbcore: registered new interface driver usbhid
+[ 2.411563] usbhid: USB HID core driver
+[ 2.411592] TCP: cubic registered
+[ 2.411599] NET: Registered protocol family 17
+ +[ 2.411989] devtmpfs: mounted
+[ 2.412026] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.449963] udevd[609]: starting version 182
+[ 2.450394] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.513292] random: dd urandom read with 17 bits of entropy available
+[ 2.513589] random: dd urandom read with 17 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.640887] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.641120] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini index f34f6e208..ef40366e9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_loader=/dist/m5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,20 +30,21 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.vram system.physmem system.realview.nvmem +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/z/stever/hg/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -186,6 +187,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -220,6 +222,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu.dtb [system.cpu.dstage2_mmu.stage2_tlb] @@ -237,7 +240,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[5] [system.cpu.dtb] type=ArmTLB @@ -645,6 +647,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -713,6 +716,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu.itb [system.cpu.istage2_mmu.stage2_tlb] @@ -730,7 +734,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.cpu.toL2Bus.slave[4] [system.cpu.itb] type=ArmTLB @@ -755,6 +758,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -788,13 +792,16 @@ size=4194304 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -825,9 +832,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=true -width=8 +width=16 default=system.realview.pciconfig.pio master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma @@ -838,6 +847,7 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -872,11 +882,14 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side @@ -926,7 +939,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr index 744db2c76..744db2c76 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout index 9642d869b..e83ff881b 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout @@ -1,16 +1,16 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 10:29:11 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor +gem5 compiled Mar 15 2015 20:30:55 +gem5 started Mar 15 2015 20:31:14 +gem5 executing on zizzer2 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 - 0: system.cpu.isa: ISA system set to: 0x5c61b00 0x5c61b00 +info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch64.20140821 + 0: system.cpu.isa: ISA system set to: 0x404afc0 0x404afc0 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51727209160500 because m5_exit instruction encountered +Exiting @ tick 51609998980000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 72f54d4c6..f1c6e64c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.690388 # Number of seconds simulated -sim_ticks 51690388482000 # Number of ticks simulated -final_tick 51690388482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.609999 # Number of seconds simulated +sim_ticks 51609998980000 # Number of ticks simulated +final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185969 # Simulator instruction rate (inst/s) -host_op_rate 218525 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10104822635 # Simulator tick rate (ticks/s) -host_mem_usage 719212 # Number of bytes of host memory used -host_seconds 5115.42 # Real time elapsed on the host -sim_insts 951311494 # Number of instructions simulated -sim_ops 1117847862 # Number of ops (including micro ops) simulated +host_inst_rate 125549 # Simulator instruction rate (inst/s) +host_op_rate 147521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6837484784 # Simulator tick rate (ticks/s) +host_mem_usage 653616 # Number of bytes of host memory used +host_seconds 7548.10 # Real time elapsed on the host +sim_insts 947659008 # Number of instructions simulated +sim_ops 1113505098 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 413184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 346752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10436032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 67415176 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 415104 # Number of bytes read from this memory -system.physmem.bytes_read::total 79026248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10436032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10436032 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 95778368 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 398592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 332160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10228032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65553800 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 419072 # Number of bytes read from this memory +system.physmem.bytes_read::total 76931656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10228032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10228032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 93992704 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 95798948 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5418 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 163063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1053375 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6486 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1234798 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1496537 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 94013284 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159813 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1024291 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6548 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1202070 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1468636 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1499110 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6708 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1304211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1528838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1852924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1853322 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1852924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1304609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3382161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1234798 # Number of read requests accepted -system.physmem.writeReqs 2155868 # Number of write requests accepted -system.physmem.readBursts 1234798 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2155868 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 78985984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 41088 # Total number of bytes read from write queue -system.physmem.bytesWritten 134775168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 79026248 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 137831460 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 642 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 49988 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39660 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74085 # Per bank write bursts -system.physmem.perBankRdBursts::1 76722 # Per bank write bursts -system.physmem.perBankRdBursts::2 75273 # Per bank write bursts -system.physmem.perBankRdBursts::3 67779 # Per bank write bursts -system.physmem.perBankRdBursts::4 73670 # Per bank write bursts -system.physmem.perBankRdBursts::5 87218 # Per bank write bursts -system.physmem.perBankRdBursts::6 75623 # Per bank write bursts -system.physmem.perBankRdBursts::7 75034 # Per bank write bursts -system.physmem.perBankRdBursts::8 70647 # Per bank write bursts -system.physmem.perBankRdBursts::9 127770 # Per bank write bursts -system.physmem.perBankRdBursts::10 77193 # Per bank write bursts -system.physmem.perBankRdBursts::11 73706 # Per bank write bursts -system.physmem.perBankRdBursts::12 69495 # Per bank write bursts -system.physmem.perBankRdBursts::13 70758 # Per bank write bursts -system.physmem.perBankRdBursts::14 68705 # Per bank write bursts -system.physmem.perBankRdBursts::15 70478 # Per bank write bursts -system.physmem.perBankWrBursts::0 131375 # Per bank write bursts -system.physmem.perBankWrBursts::1 133100 # Per bank write bursts -system.physmem.perBankWrBursts::2 134570 # Per bank write bursts -system.physmem.perBankWrBursts::3 130352 # Per bank write bursts -system.physmem.perBankWrBursts::4 132576 # Per bank write bursts -system.physmem.perBankWrBursts::5 140660 # Per bank write bursts -system.physmem.perBankWrBursts::6 130709 # Per bank write bursts -system.physmem.perBankWrBursts::7 134220 # Per bank write bursts -system.physmem.perBankWrBursts::8 130946 # Per bank write bursts -system.physmem.perBankWrBursts::9 136651 # Per bank write bursts -system.physmem.perBankWrBursts::10 131424 # Per bank write bursts -system.physmem.perBankWrBursts::11 131217 # Per bank write bursts -system.physmem.perBankWrBursts::12 125851 # Per bank write bursts -system.physmem.perBankWrBursts::13 128099 # Per bank write bursts -system.physmem.perBankWrBursts::14 126227 # Per bank write bursts -system.physmem.perBankWrBursts::15 127885 # Per bank write bursts +system.physmem.num_writes::total 1471209 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1270176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1490635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1821211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1821610 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1821211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1270575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3312245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1202070 # Number of read requests accepted +system.physmem.writeReqs 2120779 # Number of write requests accepted +system.physmem.readBursts 1202070 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2120779 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 76896960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue +system.physmem.bytesWritten 132496640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 76931656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 135585764 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50494 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39336 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 72977 # Per bank write bursts +system.physmem.perBankRdBursts::1 77412 # Per bank write bursts +system.physmem.perBankRdBursts::2 73227 # Per bank write bursts +system.physmem.perBankRdBursts::3 70716 # Per bank write bursts +system.physmem.perBankRdBursts::4 69716 # Per bank write bursts +system.physmem.perBankRdBursts::5 78531 # Per bank write bursts +system.physmem.perBankRdBursts::6 70002 # Per bank write bursts +system.physmem.perBankRdBursts::7 72888 # Per bank write bursts +system.physmem.perBankRdBursts::8 66687 # Per bank write bursts +system.physmem.perBankRdBursts::9 126636 # Per bank write bursts +system.physmem.perBankRdBursts::10 72169 # Per bank write bursts +system.physmem.perBankRdBursts::11 76842 # Per bank write bursts +system.physmem.perBankRdBursts::12 69750 # Per bank write bursts +system.physmem.perBankRdBursts::13 69617 # Per bank write bursts +system.physmem.perBankRdBursts::14 66498 # Per bank write bursts +system.physmem.perBankRdBursts::15 67847 # Per bank write bursts +system.physmem.perBankWrBursts::0 128572 # Per bank write bursts +system.physmem.perBankWrBursts::1 129591 # Per bank write bursts +system.physmem.perBankWrBursts::2 133621 # Per bank write bursts +system.physmem.perBankWrBursts::3 133794 # Per bank write bursts +system.physmem.perBankWrBursts::4 127990 # Per bank write bursts +system.physmem.perBankWrBursts::5 135547 # Per bank write bursts +system.physmem.perBankWrBursts::6 129190 # Per bank write bursts +system.physmem.perBankWrBursts::7 132517 # Per bank write bursts +system.physmem.perBankWrBursts::8 125103 # Per bank write bursts +system.physmem.perBankWrBursts::9 133352 # Per bank write bursts +system.physmem.perBankWrBursts::10 128272 # Per bank write bursts +system.physmem.perBankWrBursts::11 129497 # Per bank write bursts +system.physmem.perBankWrBursts::12 125797 # Per bank write bursts +system.physmem.perBankWrBursts::13 127747 # Per bank write bursts +system.physmem.perBankWrBursts::14 124476 # Per bank write bursts +system.physmem.perBankWrBursts::15 125194 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 155 # Number of times write queue was full causing retry -system.physmem.totGap 51690386784000 # Total gap between requests +system.physmem.numWrRetry 166 # Number of times write queue was full causing retry +system.physmem.totGap 51609997338500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1234783 # Read request sizes (log2) +system.physmem.readPktSize::6 1202055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2153295 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1198377 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 29223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2118206 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1132428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,158 +159,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 52281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 61850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 106555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 108316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 116449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 154618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 128128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 118111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 116108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 109682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 109242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 142032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 116099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 110906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 124147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 111898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 106882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 105751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 7481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 4655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 272 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 737863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 289.702517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.794717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.456499 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 301335 40.84% 40.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 180643 24.48% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 66243 8.98% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 37149 5.03% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25772 3.49% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 17225 2.33% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13400 1.82% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11666 1.58% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 84430 11.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 737863 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 101448 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.165149 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 123.730461 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 101445 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 51481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 61019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 101890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 106045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 113976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 152332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 126167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 115190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 114656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 140408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 114567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 109101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 121792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 109844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 105744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 103641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 344 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 720627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 290.570872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.798815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.942314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 295355 40.99% 40.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 175877 24.41% 65.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 63976 8.88% 74.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35683 4.95% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24604 3.41% 82.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16955 2.35% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13020 1.81% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11401 1.58% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 83756 11.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 720627 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 99482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.077512 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 124.901364 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 99480 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 101448 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 101448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.758044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.253158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.739377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 97720 96.33% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 2404 2.37% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 434 0.43% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 505 0.50% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 168 0.17% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 63 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 44 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 12 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 10 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 11 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 20 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 26 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-575 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-607 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-639 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-703 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-735 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-767 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::832-863 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-959 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 101448 # Writes before turning the bus around for reads -system.physmem.totQLat 16140892467 # Total ticks spent queuing -system.physmem.totMemAccLat 39281317467 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6170780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13078.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 99482 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 99482 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.810398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.292150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.172998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 95801 96.30% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1933 1.94% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 403 0.41% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 315 0.32% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 148 0.15% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 160 0.16% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 333 0.33% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 129 0.13% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 31 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 15 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 63 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 32 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 14 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 4 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 9 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 20 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 8 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 99482 # Writes before turning the bus around for reads +system.physmem.totQLat 16741886044 # Total ticks spent queuing +system.physmem.totMemAccLat 39270292294 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6007575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13933.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31828.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.53 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32683.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing -system.physmem.readRowHits 952465 # Number of row buffer hits during reads -system.physmem.writeRowHits 1649689 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes -system.physmem.avgGap 15244906.69 # Average gap between requests -system.physmem.pageHitRate 77.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2866207680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1563903000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4722104400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6917801760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1320834277260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29855603520000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34568672372100 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764092 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49666580122402 # Time in different power states -system.physmem_0.memoryStateTime::REF 1726055500000 # Time in different power states +system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing +system.physmem.readRowHits 927538 # Number of row buffer hits during reads +system.physmem.writeRowHits 1623609 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.42 # Row buffer hit rate for writes +system.physmem.avgGap 15531851.53 # Average gap between requests +system.physmem.pageHitRate 77.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2802990960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1529409750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4566611400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6809326560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308588544890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29818114243500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34513325311620 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.733317 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49604286854347 # Time in different power states +system.physmem_0.memoryStateTime::REF 1723371260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 297752382598 # Time in different power states +system.physmem_0.memoryStateTime::ACT 282340388153 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2712036600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1479781875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4904265600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6728184000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1311236111385 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29864022963750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34567247901210 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.736534 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49680605946994 # Time in different power states -system.physmem_1.memoryStateTime::REF 1726055500000 # Time in different power states +system.physmem_1.actEnergy 2644949160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1443176625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4805158800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6605958240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3370914184560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1300507873200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29825202552000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34512123852585 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.710038 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49616091454429 # Time in different power states +system.physmem_1.memoryStateTime::REF 1723371260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 283722031756 # Time in different power states +system.physmem_1.memoryStateTime::ACT 270535519321 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -334,15 +345,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261231631 # Number of BP lookups -system.cpu.branchPred.condPredicted 183305796 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12196019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193363774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136711559 # Number of BTB hits +system.cpu.branchPred.lookups 260066829 # Number of BP lookups +system.cpu.branchPred.condPredicted 182351604 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12179122 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 192997810 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135975989 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.701743 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31664930 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2143732 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.454680 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31593975 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2147293 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -373,68 +384,61 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 585994 # Table walker walks requested -system.cpu.dtb.walker.walksLong 585994 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21793 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191747 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 585994 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 585994 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 585994 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 213540 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24710.005137 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20824.581984 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15872.776829 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 123160 57.68% 57.68% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 87731 41.08% 98.76% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1449 0.68% 99.44% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 786 0.37% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 33 0.02% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 127 0.06% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-229375 51 0.02% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-262143 62 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 77 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::360448-393215 10 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-491519 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 213540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 583127 # Table walker walks requested +system.cpu.dtb.walker.walksLong 583127 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22581 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191165 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 583127 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 583127 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 583127 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213746 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24576.454072 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20707.683114 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15710.461946 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 211230 98.82% 98.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2148 1.00% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 131 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 118 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 73 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213746 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 191748 89.79% 89.79% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 21793 10.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 213541 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 585994 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 191166 89.44% 89.44% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 22581 10.56% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213747 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 583127 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 585994 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213541 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 583127 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213747 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213541 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 799535 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213747 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 796874 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183604569 # DTB read hits -system.cpu.dtb.read_misses 484391 # DTB read misses -system.cpu.dtb.write_hits 162970808 # DTB write hits -system.cpu.dtb.write_misses 101603 # DTB write misses +system.cpu.dtb.read_hits 182952995 # DTB read hits +system.cpu.dtb.read_misses 481784 # DTB read misses +system.cpu.dtb.write_hits 162354187 # DTB write hits +system.cpu.dtb.write_misses 101343 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80226 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 794 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 80213 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 854 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14789 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23565 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184088960 # DTB read accesses -system.cpu.dtb.write_accesses 163072411 # DTB write accesses +system.cpu.dtb.perms_faults 23472 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 183434779 # DTB read accesses +system.cpu.dtb.write_accesses 162455530 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 346575377 # DTB hits -system.cpu.dtb.misses 585994 # DTB misses -system.cpu.dtb.accesses 347161371 # DTB accesses +system.cpu.dtb.hits 345307182 # DTB hits +system.cpu.dtb.misses 583127 # DTB misses +system.cpu.dtb.accesses 345890309 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -464,175 +468,183 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136676 # Table walker walks requested -system.cpu.itb.walker.walksLong 136676 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118957 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136676 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136676 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136676 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 120036 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27117.842072 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23228.726671 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17468.785563 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 117053 97.51% 97.51% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2702 2.25% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 172 0.14% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 64 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 25 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 17 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 120036 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 136411 # Table walker walks requested +system.cpu.itb.walker.walksLong 136411 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118764 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136411 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136411 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136411 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 119838 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26864.678099 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23079.638443 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17315.603436 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 117018 97.65% 97.65% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2553 2.13% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 159 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 57 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 28 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 119838 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118957 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1079 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 120036 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 118764 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 119838 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136676 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136676 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136411 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136411 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120036 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 120036 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 256712 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 454948976 # ITB inst hits -system.cpu.itb.inst_misses 136676 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119838 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 119838 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256249 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 452746266 # ITB inst hits +system.cpu.itb.inst_misses 136411 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57709 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47075 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1109 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57592 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 370702 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 369764 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 455085652 # ITB inst accesses -system.cpu.itb.hits 454948976 # DTB hits -system.cpu.itb.misses 136676 # DTB misses -system.cpu.itb.accesses 455085652 # DTB accesses -system.cpu.numCycles 2543244455 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 452882677 # ITB inst accesses +system.cpu.itb.hits 452746266 # DTB hits +system.cpu.itb.misses 136411 # DTB misses +system.cpu.itb.accesses 452882677 # DTB accesses +system.cpu.numCycles 2486475408 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 951311494 # Number of instructions committed -system.cpu.committedOps 1117847862 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97312681 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7756 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100838701590 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.673409 # CPI: cycles per instruction -system.cpu.ipc 0.374054 # IPC: instructions per cycle +system.cpu.committedInsts 947659008 # Number of instructions committed +system.cpu.committedOps 1113505098 # Number of ops (including micro ops) committed +system.cpu.discardedOps 96546934 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7735 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100734690731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.623808 # CPI: cycles per instruction +system.cpu.ipc 0.381125 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16616 # number of quiesce instructions executed -system.cpu.tickCycles 1803568308 # Number of cycles that the object actually ticked -system.cpu.idleCycles 739676147 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11160252 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.957398 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 330283218 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11160764 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.593245 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 16595 # number of quiesce instructions executed +system.cpu.tickCycles 1791502894 # Number of cycles that the object actually ticked +system.cpu.idleCycles 694972514 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11092406 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957332 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 328965151 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11092918 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.655421 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.957398 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957332 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1387540349 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1387540349 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 169325544 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 169325544 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 152117254 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 152117254 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336638 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 336638 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4103260 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4103260 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4350721 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4350721 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 321442798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 321442798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 321442798 # number of overall hits -system.cpu.dcache.overall_hits::total 321442798 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 8046914 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 8046914 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4320227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4320227 # number of WriteReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245138 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245138 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 249194 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 249194 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1382417296 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1382417296 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 168207875 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 168207875 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 151549113 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 151549113 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 490930 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 490930 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335942 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 335942 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4008865 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4008865 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4323127 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4323127 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 319756988 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 319756988 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320247918 # number of overall hits +system.cpu.dcache.overall_hits::total 320247918 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6578537 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6578537 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4302299 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4302299 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1473808 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1473808 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1244599 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1244599 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 315993 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 315993 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 12367141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12367141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12367141 # number of overall misses -system.cpu.dcache.overall_misses::total 12367141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 131461867675 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 131461867675 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 154903534956 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 154903534956 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35707428702 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35707428702 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3656528250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 3656528250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 10880836 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10880836 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12354644 # number of overall misses +system.cpu.dcache.overall_misses::total 12354644 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 106697920457 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 106697920457 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 153242376598 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 153242376598 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35461255171 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35461255171 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4805977234 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4805977234 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 286365402631 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 286365402631 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 286365402631 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 286365402631 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177372458 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177372458 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 156437481 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 156437481 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581776 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1581776 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4352454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4352454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4350722 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4350722 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 333809939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 333809939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 333809939 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 333809939 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045367 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.045367 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027616 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027616 # miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787177 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787177 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057254 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057254 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 259940297055 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 259940297055 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 259940297055 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 259940297055 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 174786412 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 174786412 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 155851412 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 155851412 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1964738 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1964738 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1580541 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1580541 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4324858 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4324858 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4323128 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4323128 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 330637824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 330637824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 332602562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 332602562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037638 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037638 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027605 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027605 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750130 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.750130 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787451 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787451 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073064 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073064 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037048 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037048 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037048 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037048 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16336.929620 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16336.929620 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.415689 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.415689 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28677.486915 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28677.486915 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14673.420106 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14673.420106 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032909 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032909 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037145 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037145 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.095592 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.095592 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35618.718410 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35618.718410 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28492.112858 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28492.112858 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15209.125626 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15209.125626 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23155.343877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23155.343877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23889.735775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23889.735775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21039.885654 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21039.885654 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,82 +653,90 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8571803 # number of writebacks -system.cpu.dcache.writebacks::total 8571803 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 759012 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 759012 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1891728 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1891728 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 152 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 152 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2650740 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2650740 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2650740 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2650740 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7287902 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7287902 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2428499 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2428499 # number of WriteReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244986 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244986 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 249191 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 249191 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 8509656 # number of writebacks +system.cpu.dcache.writebacks::total 8509656 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799615 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 799615 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1895946 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1895946 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 144 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 144 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69791 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 69791 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2695561 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2695561 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2695561 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2695561 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5778922 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5778922 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2406353 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2406353 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1466300 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1466300 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244455 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244455 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246202 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 246202 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9716401 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9716401 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9716401 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9716401 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108232242328 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 108232242328 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80044946410 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80044946410 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33835516298 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33835516298 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3281036750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3281036750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 8185275 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 78901247228 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22730570766 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22730570766 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33591268829 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33591268829 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3240983258 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3240983258 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 188277188738 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 188277188738 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188277188738 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 188277188738 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5752052750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5752052750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611431750 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611431750 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363484500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363484500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041088 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041088 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015524 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015524 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787081 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787081 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057253 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057253 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163468245028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163468245028 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186198815794 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 186198815794 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751743992 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751743992 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611366250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611366250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363110242 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363110242 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033063 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033063 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746308 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746308 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787360 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787360 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056927 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029108 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029108 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14850.946449 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14850.946449 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32960.666819 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32960.666819 # average WriteReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27177.427134 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27177.427134 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.754618 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.754618 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024756 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024756 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029018 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029018 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14633.697738 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14633.697738 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32788.725190 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32788.725190 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15501.991929 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15501.991929 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 26992.754924 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26992.754924 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13163.919294 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13163.919294 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19971.014416 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -724,58 +744,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24658319 # number of replacements -system.cpu.icache.tags.tagsinuse 511.926866 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 429907589 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24658831 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.434224 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 23112715250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.926866 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 24538707 # number of replacements +system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 427825373 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24539219 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.434352 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 22330853250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.926996 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 479225270 # Number of tag accesses -system.cpu.icache.tags.data_accesses 479225270 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 429907589 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 429907589 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 429907589 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044596 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013712 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.442009 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.442009 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780049 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.780049 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10451903750 # 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mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.302032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.302032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.106358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006626 # 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average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33684.334226 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17742.304086 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17742.304086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.297836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.297836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006438 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018129 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004383 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104132 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032112 # 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average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33699.036547 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33699.036547 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17744.117563 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17744.117563 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69377.787528 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69377.787528 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1115,56 +1134,56 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 33999690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33991608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8571803 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8509656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49295 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2378926 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2378926 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49422267 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31128556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2275060 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 83523491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581512448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1263125858 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2313872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7794488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2854746666 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 562001 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 46265986 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002499 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.049932 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 49296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2357319 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2357319 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49183042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30929702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 693856 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2262449 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83069049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1573857216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1254806154 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2290296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 565529 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 46009467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002514 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.050072 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 46150346 99.75% 99.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 115640 0.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 45893822 99.75% 99.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115645 0.25% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46265986 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32968786985 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 46009467 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1168500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37104005805 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36924053878 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15790852218 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15679140875 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 409077948 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 408249695 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1301562725 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1295905979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40307 # Transaction distribution -system.iobus.trans_dist::ReadResp 40307 # Transaction distribution +system.iobus.trans_dist::ReadReq 40311 # Transaction distribution +system.iobus.trans_dist::ReadResp 40311 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1184,11 +1203,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230972 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230972 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1205,11 +1224,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1238,71 +1257,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 606946752 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607011706 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148389141 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148422470 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115468 # number of replacements -system.iocache.tags.tagsinuse 10.447877 # Cycle average of tags in use +system.iocache.tags.replacements 115472 # number of replacements +system.iocache.tags.tagsinuse 10.439528 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115484 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13143236480000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519281 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928596 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219955 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433037 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652992 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13142428728000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.524738 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.914790 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.220296 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432174 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652471 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039731 # Number of tag accesses -system.iocache.tags.data_accesses 1039731 # Number of data accesses +system.iocache.tags.tag_accesses 1039767 # Number of tag accesses +system.iocache.tags.data_accesses 1039767 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8822 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8859 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8822 # number of demand (read+write) misses -system.iocache.demand_misses::total 8862 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8826 # number of demand (read+write) misses +system.iocache.demand_misses::total 8866 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8822 # number of overall misses -system.iocache.overall_misses::total 8862 # number of overall misses +system.iocache.overall_misses::realview.ide 8826 # number of overall misses +system.iocache.overall_misses::total 8866 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1598742761 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1603814761 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1599431674 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1604503674 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19786721850 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 19786721850 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19839532562 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19839532562 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1598742761 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1604167261 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1599431674 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1604856174 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1598742761 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1604167261 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1599431674 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1604856174 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8822 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8859 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8822 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8862 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8826 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8866 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8822 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8862 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8826 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8866 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1317,54 +1336,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 181222.258105 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 181037.900553 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 181218.181962 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181033.924630 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185505.154973 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 185505.154973 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186000.267775 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186000.267775 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 181016.391447 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 181012.426573 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 181016.391447 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 108614 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 181218.181962 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 181012.426573 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 109629 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16000 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16167 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.788375 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.781035 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8822 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8859 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8822 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8862 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8826 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8866 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8822 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8862 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8826 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8866 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1138893007 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1142035007 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1139388578 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1142530578 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14240157886 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14240157886 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292968598 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292968598 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1138893007 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1142228507 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1139388578 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1142724078 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1138893007 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1142228507 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1139388578 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1142724078 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1379,70 +1398,70 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129096.917592 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 128912.406254 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129094.559030 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128910.140810 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133504.817802 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133504.817802 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133999.930605 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133999.930605 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 129094.559030 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 128888.346267 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 553634 # Transaction distribution -system.membus.trans_dist::ReadResp 553634 # Transaction distribution -system.membus.trans_dist::WriteReq 33707 # Transaction distribution -system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::Writeback 1496537 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 656758 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 656758 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39666 # Transaction distribution +system.membus.trans_dist::ReadReq 537267 # Transaction distribution +system.membus.trans_dist::ReadResp 537267 # Transaction distribution +system.membus.trans_dist::WriteReq 33705 # Transaction distribution +system.membus.trans_dist::WriteResp 33705 # Transaction distribution +system.membus.trans_dist::Writeback 1468636 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 649570 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 649570 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39342 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39667 # Transaction distribution -system.membus.trans_dist::ReadExReq 717891 # Transaction distribution -system.membus.trans_dist::ReadExResp 717891 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39343 # Transaction distribution +system.membus.trans_dist::ReadExReq 701468 # Transaction distribution +system.membus.trans_dist::ReadExResp 701468 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5031846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5161506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335307 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335307 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5496813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4923341 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5052989 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5388362 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202791724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202962146 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14065984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14065984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 217028130 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3038 # Total snoops (count) -system.membus.snoop_fanout::samples 3378648 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198447468 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 198617866 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14069952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2980 # Total snoops (count) +system.membus.snoop_fanout::samples 3310460 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3378648 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3310460 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3378648 # Request fanout histogram -system.membus.reqLayer0.occupancy 100002500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3310460 # Request fanout histogram +system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5714500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5637000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 12721299869 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 12263986868 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7256295209 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7071367467 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 151537359 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151550030 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal index 5c853e457..2bb89eb2c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal @@ -34,133 +34,133 @@ [ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000026] Console: colour dummy device 80x25
[ 0.000029] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000030] pid_max: default: 32768 minimum: 301
-[ 0.000044] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000174] hw perfevents: no hardware support available
-[ 1.060092] CPU1: failed to come online
-[ 2.080180] CPU2: failed to come online
-[ 3.100268] CPU3: failed to come online
-[ 3.100271] Brought up 1 CPUs
-[ 3.100273] SMP: Total of 1 processors activated.
-[ 3.100341] devtmpfs: initialized
-[ 3.101042] atomic64_test: passed
-[ 3.101098] regulator-dummy: no parameters
-[ 3.101606] NET: Registered protocol family 16
-[ 3.101773] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101783] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.102080] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.102082] Serial: AMBA PL011 UART driver
-[ 3.102304] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.102346] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102874] console [ttyAMA0] enabled
-[ 3.102953] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102989] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.103025] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.103058] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130671] 3V3: 3300 mV
-[ 3.130723] vgaarb: loaded
-[ 3.130779] SCSI subsystem initialized
-[ 3.130831] libata version 3.00 loaded.
-[ 3.130889] usbcore: registered new interface driver usbfs
-[ 3.130910] usbcore: registered new interface driver hub
-[ 3.130951] usbcore: registered new device driver usb
-[ 3.130982] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130991] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131010] PTP clock support registered
-[ 3.131159] Switched to clocksource arch_sys_counter
-[ 3.132645] NET: Registered protocol family 2
-[ 3.132738] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.132758] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.132782] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.132801] TCP: reno registered
-[ 3.132808] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132822] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132867] NET: Registered protocol family 1
-[ 3.132915] RPC: Registered named UNIX socket transport module.
-[ 3.132925] RPC: Registered udp transport module.
-[ 3.132933] RPC: Registered tcp transport module.
-[ 3.132941] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132953] PCI: CLS 0 bytes, default 64
-[ 3.133150] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.133293] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.135708] fuse init (API version 7.23)
-[ 3.135822] msgmni has been set to 469
-[ 3.138911] io scheduler noop registered
-[ 3.138984] io scheduler cfq registered (default)
-[ 3.139445] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.139457] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.139469] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.139481] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.139491] pci_bus 0000:00: scanning bus
-[ 3.139501] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.139514] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.139528] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.139574] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.139586] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.139597] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.139607] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.139618] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.139629] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.139640] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.139683] pci_bus 0000:00: fixups for bus
-[ 3.139691] pci_bus 0000:00: bus scan returning with max=00
-[ 3.139703] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.139723] pci 0000:00:00.0: fixup irq: got 33
-[ 3.139731] pci 0000:00:00.0: assigning IRQ 33
-[ 3.139742] pci 0000:00:01.0: fixup irq: got 34
-[ 3.139750] pci 0000:00:01.0: assigning IRQ 34
-[ 3.139762] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.139775] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.139788] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.139801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.139812] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.139823] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.139835] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.139846] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.140504] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.140842] ata_piix 0000:00:01.0: version 2.13
-[ 3.140853] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.140875] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.141475] scsi0 : ata_piix
-[ 3.141603] scsi1 : ata_piix
-[ 3.141641] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.141654] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.141783] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.141795] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.141811] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.141823] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301188] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301198] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301227] ata1.00: configured for UDMA/33
-[ 3.301281] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.301428] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.301457] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.301505] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.301514] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.301538] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.301694] sda: sda1
-[ 3.301852] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.421479] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.421492] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.421515] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.421525] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.421549] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.421561] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.421651] usbcore: registered new interface driver usb-storage
-[ 3.421719] mousedev: PS/2 mouse device common for all mice
-[ 3.421922] usbcore: registered new interface driver usbhid
-[ 3.421931] usbhid: USB HID core driver
-[ 3.421965] TCP: cubic registered
-[ 3.421972] NET: Registered protocol family 17
- -[ 3.422426] devtmpfs: mounted
+[ 0.000031] pid_max: default: 32768 minimum: 301
+[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000180] hw perfevents: no hardware support available
+[ 1.060095] CPU1: failed to come online
+[ 2.080185] CPU2: failed to come online
+[ 3.100275] CPU3: failed to come online
+[ 3.100278] Brought up 1 CPUs
+[ 3.100280] SMP: Total of 1 processors activated.
+[ 3.100349] devtmpfs: initialized
+[ 3.100980] atomic64_test: passed
+[ 3.101035] regulator-dummy: no parameters
+[ 3.101538] NET: Registered protocol family 16
+[ 3.101703] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.101713] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.102141] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.102147] Serial: AMBA PL011 UART driver
+[ 3.102394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.102440] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.102971] console [ttyAMA0] enabled
+[ 3.103068] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.103104] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.103141] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.103175] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130690] 3V3: 3300 mV
+[ 3.130742] vgaarb: loaded
+[ 3.130800] SCSI subsystem initialized
+[ 3.130851] libata version 3.00 loaded.
+[ 3.130907] usbcore: registered new interface driver usbfs
+[ 3.130928] usbcore: registered new interface driver hub
+[ 3.130968] usbcore: registered new device driver usb
+[ 3.130999] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131008] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131027] PTP clock support registered
+[ 3.131174] Switched to clocksource arch_sys_counter
+[ 3.132602] NET: Registered protocol family 2
+[ 3.132697] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.132719] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.132744] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.132760] TCP: reno registered
+[ 3.132768] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132782] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.132828] NET: Registered protocol family 1
+[ 3.132876] RPC: Registered named UNIX socket transport module.
+[ 3.132886] RPC: Registered udp transport module.
+[ 3.132894] RPC: Registered tcp transport module.
+[ 3.132902] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.132914] PCI: CLS 0 bytes, default 64
+[ 3.133108] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.133253] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.135428] fuse init (API version 7.23)
+[ 3.135535] msgmni has been set to 469
+[ 3.138600] io scheduler noop registered
+[ 3.138667] io scheduler cfq registered (default)
+[ 3.139158] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.139171] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.139182] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.139194] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.139204] pci_bus 0000:00: scanning bus
+[ 3.139215] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.139228] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.139243] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.139286] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.139299] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.139310] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.139320] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.139331] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.139342] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.139353] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.139394] pci_bus 0000:00: fixups for bus
+[ 3.139403] pci_bus 0000:00: bus scan returning with max=00
+[ 3.139414] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.139435] pci 0000:00:00.0: fixup irq: got 33
+[ 3.139444] pci 0000:00:00.0: assigning IRQ 33
+[ 3.139455] pci 0000:00:01.0: fixup irq: got 34
+[ 3.139463] pci 0000:00:01.0: assigning IRQ 34
+[ 3.139475] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.139488] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.139501] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.139514] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.139525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.139537] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.139548] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.139559] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.140184] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.140520] ata_piix 0000:00:01.0: version 2.13
+[ 3.140531] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.140555] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.140911] scsi0 : ata_piix
+[ 3.141038] scsi1 : ata_piix
+[ 3.141075] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.141087] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.141242] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.141254] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.141271] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.141283] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301203] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301213] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301243] ata1.00: configured for UDMA/33
+[ 3.301299] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.301438] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.301467] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.301514] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.301523] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.301547] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.301695] sda: sda1
+[ 3.301842] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.421490] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.421503] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.421526] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.421536] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.421559] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.421571] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.421656] usbcore: registered new interface driver usb-storage
+[ 3.421723] mousedev: PS/2 mouse device common for all mice
+[ 3.421911] usbcore: registered new interface driver usbhid
+[ 3.421921] usbhid: USB HID core driver
+[ 3.421955] TCP: cubic registered
+[ 3.421963] NET: Registered protocol family 17
+ +[ 3.422420] devtmpfs: mounted
[ 3.422455] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.464515] udevd[607]: starting version 182
+[ 3.464312] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.614679] random: dd urandom read with 21 bits of entropy available
+[ 3.594630] random: dd urandom read with 20 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.781391] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.751405] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|