diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
3 files changed, 2839 insertions, 2813 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 07942a1c8..e2d527772 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538055 # Number of seconds simulated -sim_ticks 2538055224500 # Number of ticks simulated -final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538087 # Number of seconds simulated +sim_ticks 2538087368500 # Number of ticks simulated +final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74782 # Simulator instruction rate (inst/s) -host_op_rate 96192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3131579061 # Simulator tick rate (ticks/s) -host_mem_usage 390232 # Number of bytes of host memory used -host_seconds 810.47 # Real time elapsed on the host -sim_insts 60608338 # Number of instructions simulated -sim_ops 77960937 # Number of ops (including micro ops) simulated +host_inst_rate 75387 # Simulator instruction rate (inst/s) +host_op_rate 96971 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3156986836 # Simulator tick rate (ticks/s) +host_mem_usage 390016 # Number of bytes of host memory used +host_seconds 803.96 # Real time elapsed on the host +sim_insts 60608307 # Number of instructions simulated +sim_ops 77960925 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64349 # number of replacements -system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use -system.l2c.total_refs 1966684 # Total number of references to valid blocks. -system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor +system.l2c.replacements 64372 # number of replacements +system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use +system.l2c.total_refs 1967256 # Total number of references to valid blocks. +system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387818 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1500728 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112928 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112928 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500746 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613656 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122661 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11547 # number of overall hits -system.l2c.overall_hits::cpu.inst 978702 # number of overall hits -system.l2c.overall_hits::cpu.data 500746 # number of overall hits -system.l2c.overall_hits::total 1613656 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits +system.l2c.Writeback_hits::total 608347 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits +system.l2c.overall_hits::cpu.inst 978266 # number of overall hits +system.l2c.overall_hits::cpu.data 500583 # number of overall hits +system.l2c.overall_hits::total 1613985 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2903 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133164 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133164 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # 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number of overall misses +system.l2c.overall_misses::cpu.data 143884 # number of overall misses +system.l2c.overall_misses::total 156312 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3194000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 658900997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 562244999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1224396496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7068682495 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7068682495 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3190500 # 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mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,9 +332,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052335 # DTB read hits +system.cpu.checker.dtb.read_hits 15052368 # DTB read hits system.cpu.checker.dtb.read_misses 7317 # DTB read misses -system.cpu.checker.dtb.write_hits 11295995 # DTB write hits +system.cpu.checker.dtb.write_hits 11296020 # DTB write hits system.cpu.checker.dtb.write_misses 2195 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -345,13 +345,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15059652 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298190 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15059685 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11298215 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26348330 # DTB hits +system.cpu.checker.dtb.hits 26348388 # DTB hits system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 26357842 # DTB accesses -system.cpu.checker.itb.inst_hits 61787107 # ITB inst hits +system.cpu.checker.dtb.accesses 26357900 # DTB accesses +system.cpu.checker.itb.inst_hits 61787075 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -368,36 +368,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61791578 # ITB inst accesses -system.cpu.checker.itb.hits 61787107 # DTB hits +system.cpu.checker.itb.inst_accesses 61791546 # ITB inst accesses +system.cpu.checker.itb.hits 61787075 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61791578 # DTB accesses -system.cpu.checker.numCycles 78251513 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61791546 # DTB accesses +system.cpu.checker.numCycles 78251500 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51779226 # DTB read hits -system.cpu.dtb.read_misses 81574 # DTB read misses -system.cpu.dtb.write_hits 11882622 # DTB write hits -system.cpu.dtb.write_misses 18093 # DTB write misses +system.cpu.dtb.read_hits 51778790 # DTB read hits +system.cpu.dtb.read_misses 81353 # DTB read misses +system.cpu.dtb.write_hits 11881898 # DTB write hits +system.cpu.dtb.write_misses 18166 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8066 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8033 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860800 # DTB read accesses -system.cpu.dtb.write_accesses 11900715 # DTB write accesses +system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860143 # DTB read accesses +system.cpu.dtb.write_accesses 11900064 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63661848 # DTB hits -system.cpu.dtb.misses 99667 # DTB misses -system.cpu.dtb.accesses 63761515 # DTB accesses -system.cpu.itb.inst_hits 13144692 # ITB inst hits -system.cpu.itb.inst_misses 11967 # ITB inst misses +system.cpu.dtb.hits 63660688 # DTB hits +system.cpu.dtb.misses 99519 # DTB misses +system.cpu.dtb.accesses 63760207 # DTB accesses +system.cpu.itb.inst_hits 13142674 # ITB inst hits +system.cpu.itb.inst_misses 12012 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -406,122 +406,122 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5259 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5318 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13156659 # ITB inst accesses -system.cpu.itb.hits 13144692 # DTB hits -system.cpu.itb.misses 11967 # DTB misses -system.cpu.itb.accesses 13156659 # DTB accesses -system.cpu.numCycles 487285069 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154686 # ITB inst accesses +system.cpu.itb.hits 13142674 # DTB hits +system.cpu.itb.misses 12012 # DTB misses +system.cpu.itb.accesses 13154686 # DTB accesses +system.cpu.numCycles 487300785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits +system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -549,13 +549,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued @@ -568,10 +568,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued @@ -583,361 +583,361 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued -system.cpu.iq.rate 0.259591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued +system.cpu.iq.rate 0.259577 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255493 # number of nop insts executed -system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed -system.cpu.iew.exec_branches 11931891 # Number of branches executed -system.cpu.iew.exec_stores 12393835 # Number of stores executed -system.cpu.iew.exec_rate 0.253013 # Inst execution rate -system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47524907 # num instructions producing a value -system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value +system.cpu.iew.exec_nop 255111 # number of nop insts executed +system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed +system.cpu.iew.exec_branches 11930392 # Number of branches executed +system.cpu.iew.exec_stores 12393079 # Number of stores executed +system.cpu.iew.exec_rate 0.253002 # Inst execution rate +system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47523827 # num instructions producing a value +system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758719 # Number of instructions committed -system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758688 # Number of instructions committed +system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520132 # Number of memory references committed -system.cpu.commit.loads 15719739 # Number of loads committed -system.cpu.commit.membars 413350 # Number of memory barriers committed -system.cpu.commit.branches 10163894 # Number of branches committed +system.cpu.commit.refs 27520186 # Number of memory references committed +system.cpu.commit.loads 15719769 # Number of loads committed +system.cpu.commit.membars 413359 # Number of memory barriers committed +system.cpu.commit.branches 10163898 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996264 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. +system.cpu.commit.function_calls 996262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256736769 # The number of ROB reads -system.cpu.rob.rob_writes 209812510 # The number of ROB writes -system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608338 # Number of Instructions Simulated -system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated -system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558055788 # number of integer regfile reads -system.cpu.int_regfile_writes 90157821 # number of integer regfile writes -system.cpu.fp_regfile_reads 8288 # number of floating regfile reads -system.cpu.fp_regfile_writes 2908 # number of floating regfile writes -system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads -system.cpu.misc_regfile_writes 913357 # number of misc regfile writes -system.cpu.icache.replacements 991945 # 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Number of Instructions Simulated +system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated +system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558050325 # number of integer regfile reads +system.cpu.int_regfile_writes 90161621 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads +system.cpu.misc_regfile_writes 913390 # number of misc regfile writes +system.cpu.icache.replacements 991554 # number of replacements +system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use +system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits -system.cpu.icache.overall_hits::total 12062971 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061582 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # 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mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644089 # number of replacements -system.cpu.dcache.tagsinuse 511.991456 # Cycle average of tags in use -system.cpu.dcache.total_refs 21738846 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644601 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724499 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor +system.cpu.dcache.replacements 643955 # number of replacements +system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use +system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908205 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -959,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b2358caab..37534da99 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.617033 # Number of seconds simulated -sim_ticks 2617033170500 # Number of ticks simulated -final_tick 2617033170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.617165 # Number of seconds simulated +sim_ticks 2617165375500 # Number of ticks simulated +final_tick 2617165375500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88113 # Simulator instruction rate (inst/s) -host_op_rate 113402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3655705591 # Simulator tick rate (ticks/s) -host_mem_usage 391256 # Number of bytes of host memory used -host_seconds 715.88 # Real time elapsed on the host -sim_insts 63077791 # Number of instructions simulated -sim_ops 81181923 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4357428 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5244336 # Number of bytes read from this memory -system.physmem.bytes_read::total 131535204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 820992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4255104 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7284240 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81969 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301800 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66486 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823770 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46277796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1665026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 162456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2003924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50261191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 162456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1625927 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1150974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1625927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46277796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1671522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 162456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3154898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53044587 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 89131 # Simulator instruction rate (inst/s) +host_op_rate 114699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3698456604 # Simulator tick rate (ticks/s) +host_mem_usage 391036 # Number of bytes of host memory used +host_seconds 707.64 # Real time elapsed on the host +sim_insts 63072219 # Number of instructions simulated +sim_ops 81165616 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -84,237 +29,310 @@ system.realview.nvmem.bw_inst_read::total 171 # I system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72594 # number of replacements -system.l2c.tagsinuse 53100.305923 # Cycle average of tags in use -system.l2c.total_refs 1970249 # Total number of references to valid blocks. -system.l2c.sampled_refs 137794 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.298511 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 388160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4317812 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 434112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5305072 # Number of bytes read from this memory +system.physmem.bytes_read::total 131557540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 388160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 434112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4272576 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7301712 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6783 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82918 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302149 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66759 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824043 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46275459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 148313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1649805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 165871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2027030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50267186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 148313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 165871 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314184 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1632520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1150915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2789931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1632520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46275459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 148313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1656300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 165871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3177945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53057118 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72943 # number of replacements +system.l2c.tagsinuse 53116.867697 # Cycle average of tags in use +system.l2c.total_refs 1971460 # Total number of references to valid blocks. +system.l2c.sampled_refs 138142 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.271257 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37791.704596 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.504480 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.004560 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4202.741800 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2939.105076 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.484693 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4025.080355 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4123.680364 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.576656 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37786.311031 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 4.267723 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000236 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4199.901742 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2938.535340 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 12.943065 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.004375 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4043.458423 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4131.445760 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.576573 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000065 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064129 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.044847 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061418 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062922 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810246 # 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mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40411.328872 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40388.960103 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40404.341603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40734.530859 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.288451 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.098817 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.500000 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40019.795658 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.245675 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40016.164585 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41094.922774 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40730.693596 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40895.030032 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40423.935251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40727.858238 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.058335 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.889669 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40027.883460 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.546261 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.054422 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40017.066086 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41076.199160 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40760.780552 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40900.455825 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +537,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9087709 # DTB read hits -system.cpu0.dtb.read_misses 37707 # DTB read misses -system.cpu0.dtb.write_hits 5292852 # DTB write hits -system.cpu0.dtb.write_misses 6797 # DTB write misses +system.cpu0.dtb.read_hits 7439931 # DTB read hits +system.cpu0.dtb.read_misses 24509 # DTB read misses +system.cpu0.dtb.write_hits 4439969 # DTB write hits +system.cpu0.dtb.write_misses 3332 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2252 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1465 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1349 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9125416 # DTB read accesses -system.cpu0.dtb.write_accesses 5299649 # DTB write accesses +system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7464440 # DTB read accesses +system.cpu0.dtb.write_accesses 4443301 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14380561 # DTB hits -system.cpu0.dtb.misses 44504 # DTB misses -system.cpu0.dtb.accesses 14425065 # DTB accesses -system.cpu0.itb.inst_hits 4426363 # ITB inst hits -system.cpu0.itb.inst_misses 5791 # ITB inst misses +system.cpu0.dtb.hits 11879900 # DTB hits +system.cpu0.dtb.misses 27841 # DTB misses +system.cpu0.dtb.accesses 11907741 # DTB accesses +system.cpu0.itb.inst_hits 3552097 # ITB inst hits +system.cpu0.itb.inst_misses 3937 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,542 +566,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1661 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 929 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4432154 # ITB inst accesses -system.cpu0.itb.hits 4426363 # DTB hits -system.cpu0.itb.misses 5791 # DTB misses -system.cpu0.itb.accesses 4432154 # DTB accesses -system.cpu0.numCycles 73540541 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 3556034 # ITB inst accesses +system.cpu0.itb.hits 3552097 # DTB hits +system.cpu0.itb.misses 3937 # DTB misses +system.cpu0.itb.accesses 3556034 # DTB accesses +system.cpu0.numCycles 63548405 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6354280 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4863798 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 316535 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 4079773 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3047693 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5090505 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 3902323 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 231356 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3310708 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2517095 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700511 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 30883 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12981968 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33339853 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6354280 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3748204 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7827899 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1608255 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 88516 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 23525864 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 77679 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 91798 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4424514 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 175463 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2818 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 45755598 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.940589 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.320885 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 576022 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 23707 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 10651881 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 26843573 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5090505 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3093117 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 6356133 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1209317 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66372 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20477375 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 36616 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 72183 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 3550824 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 136175 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2156 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 38533087 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.905766 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.281431 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 37936221 82.91% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 625086 1.37% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 819758 1.79% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 695394 1.52% 87.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 800497 1.75% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578636 1.26% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 719119 1.57% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 370554 0.81% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3210333 7.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32183362 83.52% 83.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 497864 1.29% 84.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 649099 1.68% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 569855 1.48% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 713173 1.85% 89.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 461238 1.20% 91.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 562037 1.46% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 306432 0.80% 93.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2590027 6.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 45755598 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086405 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.453353 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13479181 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 23559009 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7020718 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 606128 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1090562 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 996028 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66487 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41577642 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 218603 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1090562 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14092626 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6784553 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14469405 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6963849 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2354603 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40318960 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2633 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 472928 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1334672 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 351 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40667832 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 182121697 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 182086780 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34917 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31702592 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8965239 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 463825 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 419023 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5696158 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7936117 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5894118 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139492 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1233570 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 38069002 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 950684 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38295497 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6802670 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14391567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 261548 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 45755598 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.836958 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.462966 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 38533087 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.080104 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.422411 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 11016691 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20495843 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 5693231 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512184 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 815138 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 784502 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 52422 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 33794983 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 170156 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 815138 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 11512212 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6110309 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12456624 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 5662288 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1976516 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 32836773 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1958 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 434728 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1081609 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 147 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 32827027 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 148293172 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 148253410 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 39762 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 25938752 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 6888275 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 379434 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 344458 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4684493 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6313022 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4948082 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 931233 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 932024 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 31038582 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 848484 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 31613010 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 68951 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5311616 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10469723 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 281141 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 38533087 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.820412 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.447904 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 29855724 65.25% 65.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6336412 13.85% 79.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3245721 7.09% 86.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2523061 5.51% 91.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2111675 4.62% 96.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 936021 2.05% 98.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 511535 1.12% 99.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 181147 0.40% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54302 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 25332313 65.74% 65.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5318332 13.80% 79.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2653261 6.89% 86.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2120070 5.50% 91.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1758280 4.56% 96.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 743996 1.93% 98.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 416585 1.08% 99.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 146664 0.38% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 43586 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 45755598 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 38533087 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27761 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 835942 77.99% 80.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207752 19.38% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 17185 1.90% 1.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.05% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 711308 78.54% 80.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 176706 19.51% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 23003680 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50163 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9567598 24.98% 85.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5620993 14.68% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 39793 0.13% 0.13% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 18975009 60.02% 60.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42063 0.13% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 627 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7818427 24.73% 85.02% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4737084 14.98% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38295497 # Type of FU issued -system.cpu0.iq.rate 0.520740 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1071919 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.027991 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 123548516 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45830842 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35351164 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8368 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39310727 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4345 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 327037 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 31613010 # Type of FU issued +system.cpu0.iq.rate 0.497463 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 905651 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028648 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 102751361 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 37203152 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 29110459 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 9929 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5392 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4352 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 32473546 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5322 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 253493 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1508258 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3980 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13847 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 614652 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1084760 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3550 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10332 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 476904 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149655 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5288 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1893731 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4858 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1090562 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4675196 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 127491 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39158193 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 88903 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7936117 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5894118 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 617815 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49276 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17780 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13847 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 160769 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144529 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 305298 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37872918 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9405503 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 422579 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 815138 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4299477 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 104449 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 31945570 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 72737 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 6313022 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4948082 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 576088 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 33936 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17434 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10332 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 115531 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 108245 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 223776 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 31278568 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7699224 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 334442 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 138507 # number of nop insts executed -system.cpu0.iew.exec_refs 14971538 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5077620 # Number of branches executed -system.cpu0.iew.exec_stores 5566035 # Number of stores executed -system.cpu0.iew.exec_rate 0.514994 # Inst execution rate -system.cpu0.iew.wb_sent 37653849 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35355057 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18700837 # num instructions producing a value -system.cpu0.iew.wb_consumers 35658328 # num instructions consuming a value +system.cpu0.iew.exec_nop 58504 # number of nop insts executed +system.cpu0.iew.exec_refs 12394115 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4158454 # Number of branches executed +system.cpu0.iew.exec_stores 4694891 # Number of stores executed +system.cpu0.iew.exec_rate 0.492201 # Inst execution rate +system.cpu0.iew.wb_sent 31120630 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 29114811 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 15418480 # num instructions producing a value +system.cpu0.iew.wb_consumers 29202336 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.480756 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524445 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.458152 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.527988 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6703968 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 689136 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 267907 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 44701440 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.716325 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.672707 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5043051 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 567343 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 195875 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 37746791 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.699150 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.656907 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32554343 72.83% 72.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6077315 13.60% 86.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1947893 4.36% 90.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1038743 2.32% 93.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 803562 1.80% 94.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 505193 1.13% 96.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 401469 0.90% 96.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 200976 0.45% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1171946 2.62% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 27673007 73.31% 73.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5099673 13.51% 86.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1632700 4.33% 91.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 816219 2.16% 93.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 659263 1.75% 95.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 376754 1.00% 96.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 343613 0.91% 96.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 170043 0.45% 97.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 975519 2.58% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 44701440 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24280608 # Number of instructions committed -system.cpu0.commit.committedOps 32020757 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 37746791 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 19900047 # Number of instructions committed +system.cpu0.commit.committedOps 26390683 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11707325 # Number of memory references committed -system.cpu0.commit.loads 6427859 # Number of loads committed -system.cpu0.commit.membars 234599 # Number of memory barriers committed -system.cpu0.commit.branches 4418672 # Number of branches committed -system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28286546 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500309 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1171946 # number cycles where commit BW limit reached +system.cpu0.commit.refs 9699440 # Number of memory references committed +system.cpu0.commit.loads 5228262 # Number of loads committed +system.cpu0.commit.membars 194354 # Number of memory barriers committed +system.cpu0.commit.branches 3620828 # Number of branches committed +system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 23422561 # Number of committed integer instructions. +system.cpu0.commit.function_calls 422942 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 975519 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 81369547 # The number of ROB reads -system.cpu0.rob.rob_writes 78542452 # The number of ROB writes -system.cpu0.timesIdled 427204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27784943 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5160481977 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24199866 # Number of Instructions Simulated -system.cpu0.committedOps 31940015 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24199866 # Number of Instructions Simulated -system.cpu0.cpi 3.038882 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.038882 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.329068 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.329068 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176731885 # number of integer regfile reads -system.cpu0.int_regfile_writes 35129220 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3381 # number of floating regfile reads -system.cpu0.fp_regfile_writes 940 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47656068 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527809 # number of misc regfile writes -system.cpu0.icache.replacements 407270 # number of replacements -system.cpu0.icache.tagsinuse 511.577657 # Cycle average of tags in use -system.cpu0.icache.total_refs 3982592 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 407782 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.766473 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7275068000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.577657 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3982592 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3982592 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3982592 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3982592 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3982592 # number of overall hits -system.cpu0.icache.overall_hits::total 3982592 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 441782 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 441782 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 441782 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 441782 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 441782 # number of overall misses -system.cpu0.icache.overall_misses::total 441782 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7132710997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7132710997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7132710997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7132710997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7132710997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7132710997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4424374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4424374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4424374 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4424374 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4424374 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4424374 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099852 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099852 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099852 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099852 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099852 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099852 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16145.318272 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16145.318272 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16145.318272 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16145.318272 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1383498 # number of cycles access was blocked +system.cpu0.rob.rob_reads 67501483 # The number of ROB reads +system.cpu0.rob.rob_writes 63684069 # The number of ROB writes +system.cpu0.timesIdled 366948 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25015318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5170100782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 19875493 # Number of Instructions Simulated +system.cpu0.committedOps 26366129 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 19875493 # Number of Instructions Simulated +system.cpu0.cpi 3.197325 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.197325 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.312761 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.312761 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 145756307 # number of integer regfile reads +system.cpu0.int_regfile_writes 28747856 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4243 # number of floating regfile reads +system.cpu0.fp_regfile_writes 404 # number of floating regfile writes +system.cpu0.misc_regfile_reads 38262536 # number of misc regfile reads +system.cpu0.misc_regfile_writes 444175 # number of misc regfile writes +system.cpu0.icache.replacements 335591 # number of replacements +system.cpu0.icache.tagsinuse 511.578004 # Cycle average of tags in use +system.cpu0.icache.total_refs 3187209 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 336103 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.482834 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7275076000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.578004 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999176 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999176 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3187209 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3187209 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3187209 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3187209 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3187209 # number of overall hits +system.cpu0.icache.overall_hits::total 3187209 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 363477 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 363477 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 363477 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 363477 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 363477 # number of overall misses +system.cpu0.icache.overall_misses::total 363477 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5925752494 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5925752494 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5925752494 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5925752494 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5925752494 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5925752494 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 3550686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 3550686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 3550686 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 3550686 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 3550686 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 3550686 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102368 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.102368 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102368 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.102368 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102368 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.102368 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16302.964133 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16302.964133 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16302.964133 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16302.964133 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1276494 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 156 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8186.378698 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8182.653846 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33988 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33988 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33988 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33988 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33988 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33988 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407794 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 407794 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 407794 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 407794 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 407794 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 407794 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5471235499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5471235499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5471235499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5471235499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5471235499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5471235499 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092170 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.092170 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.092170 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13416.665029 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 27366 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 27366 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 27366 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 27366 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 27366 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 27366 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 336111 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 336111 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 336111 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 336111 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 336111 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 336111 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4556806494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4556806494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4556806494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4556806494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4556806494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4556806494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8394000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8394000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8394000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8394000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.094661 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.094661 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.094661 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13557.445290 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275687 # number of replacements -system.cpu0.dcache.tagsinuse 476.019935 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9558592 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276199 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.607627 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.019935 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.929726 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.929726 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5937166 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5937166 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3229422 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3229422 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174299 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174299 # 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number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1995851 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1995851 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1995851 # number of overall misses -system.cpu0.dcache.overall_misses::total 1995851 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7292954000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7292954000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71657694355 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71657694355 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113831500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 113831500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90370500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 90370500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 78950648355 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 78950648355 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 78950648355 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 78950648355 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6338722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6338722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823717 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4823717 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183313 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183313 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179339 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179339 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11162439 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11162439 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11162439 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11162439 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063350 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063350 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330512 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330512 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049173 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049173 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043382 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043382 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178801 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178801 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178801 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178801 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18161.735848 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18161.735848 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44946.320697 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44946.320697 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12628.300422 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12628.300422 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11615.745501 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11615.745501 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39557.385975 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39557.385975 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7317992 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1712000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1467 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 85 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4988.406271 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20141.176471 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 225959 # number of replacements +system.cpu0.dcache.tagsinuse 476.340528 # Cycle average of tags in use +system.cpu0.dcache.total_refs 7674381 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 226327 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.908376 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 51455000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 476.340528 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.930353 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.930353 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 4719087 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4719087 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 2610456 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2610456 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 155489 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 155489 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152427 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 152427 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7329543 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7329543 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7329543 # number of overall hits +system.cpu0.dcache.overall_hits::total 7329543 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 331165 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 331165 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1441313 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1441313 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8607 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8607 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7989 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7989 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1772478 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1772478 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1772478 # number of overall misses +system.cpu0.dcache.overall_misses::total 1772478 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6024148000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6024148000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68192376390 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 68192376390 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105659500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 105659500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 91795500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 91795500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 74216524390 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 74216524390 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 74216524390 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 74216524390 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5050252 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5050252 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4051769 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4051769 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 164096 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 164096 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160416 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 160416 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9102021 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9102021 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9102021 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9102021 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.065574 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.065574 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.355724 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.355724 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052451 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052451 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049802 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049802 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.194735 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.194735 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.194735 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.194735 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18190.774991 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18190.774991 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47312.676976 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 47312.676976 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12275.996282 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12275.996282 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11490.236575 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11490.236575 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41871.619501 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41871.619501 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 5649995 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1774500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1210 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 93 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4669.417355 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 19080.645161 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks -system.cpu0.dcache.writebacks::total 255942 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 212150 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 212150 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463164 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1463164 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 530 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 530 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1675314 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1675314 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1675314 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1675314 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189406 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189406 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131131 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131131 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8484 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8484 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320537 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320537 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320537 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320537 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2811014487 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2811014487 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4674099005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4674099005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79244002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79244002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65918035 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65918035 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7485113492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7485113492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7485113492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7485113492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13455989500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13455989500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1298746899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1298746899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14754736399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14754736399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029881 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029881 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027185 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027185 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046281 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046281 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043342 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043342 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028716 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028716 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14841.211403 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14841.211403 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35644.500576 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35644.500576 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9340.405705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9340.405705 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8480.385308 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8480.385308 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 209818 # number of writebacks +system.cpu0.dcache.writebacks::total 209818 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 177491 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 177491 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1323875 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1323875 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 700 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1501366 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1501366 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1501366 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1501366 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 153674 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 153674 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 117438 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 117438 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7907 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7907 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7979 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7979 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 271112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 271112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 271112 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 271112 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2311816775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2311816775 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4408331005 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4408331005 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70347504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70347504 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66656537 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66656537 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6720147780 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6720147780 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6720147780 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6720147780 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12100601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12100601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1292553399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1292553399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13393154899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13393154899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030429 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030429 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048185 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.048185 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029786 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029786 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15043.642874 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15043.642874 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37537.517711 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37537.517711 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8896.864045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8896.864045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8353.996365 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8353.996365 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1081,27 +1107,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43452334 # DTB read hits -system.cpu1.dtb.read_misses 46277 # DTB read misses -system.cpu1.dtb.write_hits 7091337 # DTB write hits -system.cpu1.dtb.write_misses 12150 # DTB write misses +system.cpu1.dtb.read_hits 45088968 # DTB read hits +system.cpu1.dtb.read_misses 60619 # DTB read misses +system.cpu1.dtb.write_hits 7938217 # DTB write hits +system.cpu1.dtb.write_misses 15813 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2524 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3762 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2729 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3748 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43498611 # DTB read accesses -system.cpu1.dtb.write_accesses 7103487 # DTB write accesses +system.cpu1.dtb.perms_faults 727 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 45149587 # DTB read accesses +system.cpu1.dtb.write_accesses 7954030 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50543671 # DTB hits -system.cpu1.dtb.misses 58427 # DTB misses -system.cpu1.dtb.accesses 50602098 # DTB accesses -system.cpu1.itb.inst_hits 9232744 # ITB inst hits -system.cpu1.itb.inst_misses 6115 # ITB inst misses +system.cpu1.dtb.hits 53027185 # DTB hits +system.cpu1.dtb.misses 76432 # DTB misses +system.cpu1.dtb.accesses 53103617 # DTB accesses +system.cpu1.itb.inst_hits 10093689 # ITB inst hits +system.cpu1.itb.inst_misses 8052 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1110,542 +1136,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1606 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1586 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1727 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2426 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9238859 # ITB inst accesses -system.cpu1.itb.hits 9232744 # DTB hits -system.cpu1.itb.misses 6115 # DTB misses -system.cpu1.itb.accesses 9238859 # DTB accesses -system.cpu1.numCycles 420389270 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10101741 # ITB inst accesses +system.cpu1.itb.hits 10093689 # DTB hits +system.cpu1.itb.misses 8052 # DTB misses +system.cpu1.itb.accesses 10101741 # DTB accesses +system.cpu1.numCycles 430376404 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9847995 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8081754 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 448433 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6818773 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5657403 # Number of BTB hits +system.cpu1.BPredUnit.lookups 11102078 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 9036479 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 529963 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7542756 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 6181694 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 833939 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50420 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22177481 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71987538 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9847995 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6491342 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15338669 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4640041 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 86616 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 81067805 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5869 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 63713 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142087 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9230611 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 860735 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 122048207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.712843 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.062128 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 958293 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 57467 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 24500240 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 78456444 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 11102078 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 7139987 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 16800094 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5031478 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 107954 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 84138717 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 105572 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 161210 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10091008 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 896138 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 4286 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 129269647 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.735584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.091589 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 106717875 87.44% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 829211 0.68% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1015415 0.83% 88.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2063306 1.69% 90.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1641471 1.34% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 615009 0.50% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2274741 1.86% 94.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 467540 0.38% 94.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6423639 5.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 112479856 87.01% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 952035 0.74% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1186228 0.92% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2188812 1.69% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1732150 1.34% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 728800 0.56% 92.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2428875 1.88% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 531185 0.41% 94.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7041706 5.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 122048207 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.023426 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.171240 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23807304 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 80829213 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13786228 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 560401 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3065061 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1241341 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102643 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 81234919 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 343119 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3065061 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25364340 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34010393 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 42304537 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12707018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4596858 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74746383 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 20429 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 720817 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3279864 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33412 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79106997 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 344419030 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 344359691 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59339 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50193146 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28913851 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 487769 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 421850 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8399849 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14034972 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8614706 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1072487 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1529720 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67446295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1206628 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91979521 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 109681 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18910261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53596675 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 286825 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 122048207 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.753633 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.492572 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 129269647 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.025796 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.182297 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 26260600 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 83914684 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15106265 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 652780 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3335318 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1450901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 116510 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 88966869 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 389379 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3335318 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 27931781 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34696050 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 44327698 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 14003132 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4975668 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 82212740 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 21319 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 759400 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3532141 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33925 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 86942184 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 378153831 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 378105448 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 48383 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 55944710 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 30997473 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 570448 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 494970 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9410070 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15640035 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 9547074 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1284923 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1813164 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 74425843 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1310750 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 98630822 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 132915 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 20366425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 57377380 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 269048 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 129269647 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.762985 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.495609 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 90230410 73.93% 73.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9124502 7.48% 81.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4577298 3.75% 85.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4017634 3.29% 88.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10703333 8.77% 97.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1977632 1.62% 98.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1055737 0.87% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 281681 0.23% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 79980 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 94766617 73.31% 73.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10139907 7.84% 81.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 5158815 3.99% 85.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4427747 3.43% 88.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 11055431 8.55% 97.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2157635 1.67% 98.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1155512 0.89% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 316791 0.25% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 91192 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 122048207 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 129269647 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28913 0.37% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7574685 95.84% 96.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298874 3.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 39597 0.49% 0.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1008 0.01% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7696421 95.46% 95.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 325487 4.04% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39479578 42.92% 43.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61492 0.07% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1697 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44651207 48.54% 91.88% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7471778 8.12% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 326092 0.33% 0.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 43501050 44.10% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 69634 0.07% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 16 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1718 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.51% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 46384595 47.03% 91.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 8347697 8.46% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91979521 # Type of FU issued -system.cpu1.iq.rate 0.218796 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7903470 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.085926 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 314063875 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 87576510 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55784562 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14814 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8109 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99561488 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7766 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 369403 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 98630822 # Type of FU issued +system.cpu1.iq.rate 0.229173 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 8062513 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.081744 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 334791339 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 96121166 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 62008917 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11647 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6672 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5500 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 106361230 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6013 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 441985 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4042367 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6847 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 22042 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1594624 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4452276 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7115 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 25628 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1723414 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965742 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1047944 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 32221586 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1050708 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3065061 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25634357 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 409319 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68777683 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 134755 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14034972 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8614706 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 896270 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 80399 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 14951 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 22042 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 226446 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 198201 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 424647 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 89117462 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43838045 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2862059 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3335318 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26012639 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 434151 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 75941872 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 151121 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15640035 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 9547074 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 940187 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 96009 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 15502 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 25628 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 268769 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 233332 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 502101 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 95691641 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 45532774 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2939181 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 124760 # number of nop insts executed -system.cpu1.iew.exec_refs 51234744 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7395685 # Number of branches executed -system.cpu1.iew.exec_stores 7396699 # Number of stores executed -system.cpu1.iew.exec_rate 0.211988 # Inst execution rate -system.cpu1.iew.wb_sent 87946957 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55791363 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30796912 # num instructions producing a value -system.cpu1.iew.wb_consumers 54575062 # num instructions consuming a value +system.cpu1.iew.exec_nop 205279 # number of nop insts executed +system.cpu1.iew.exec_refs 53793996 # number of memory reference insts executed +system.cpu1.iew.exec_branches 8312135 # Number of branches executed +system.cpu1.iew.exec_stores 8261222 # Number of stores executed +system.cpu1.iew.exec_rate 0.222344 # Inst execution rate +system.cpu1.iew.wb_sent 94462198 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 62014417 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 34071785 # num instructions producing a value +system.cpu1.iew.wb_consumers 60996509 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132714 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.564304 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.144093 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.558586 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 19037243 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919803 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 377326 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 119031582 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.414273 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.369590 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 20655264 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1041702 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 445913 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 125990352 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.435949 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.396620 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 101746657 85.48% 85.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8535054 7.17% 92.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2209116 1.86% 94.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1312161 1.10% 95.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1288209 1.08% 96.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 590684 0.50% 97.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 998098 0.84% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 485890 0.41% 98.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1865713 1.57% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 106643597 84.64% 84.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9506424 7.55% 92.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2528568 2.01% 94.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1530167 1.21% 95.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1425850 1.13% 96.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 711007 0.56% 97.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1063442 0.84% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 518210 0.41% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 2063087 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 119031582 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38947564 # Number of instructions committed -system.cpu1.commit.committedOps 49311547 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 125990352 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 43322553 # Number of instructions committed +system.cpu1.commit.committedOps 54925314 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17012687 # Number of memory references committed -system.cpu1.commit.loads 9992605 # Number of loads committed -system.cpu1.commit.membars 202357 # Number of memory barriers committed -system.cpu1.commit.branches 6222202 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43701968 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556417 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1865713 # number cycles where commit BW limit reached +system.cpu1.commit.refs 19011419 # Number of memory references committed +system.cpu1.commit.loads 11187759 # Number of loads committed +system.cpu1.commit.membars 242679 # Number of memory barriers committed +system.cpu1.commit.branches 7019269 # Number of branches committed +system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 48550450 # Number of committed integer instructions. +system.cpu1.commit.function_calls 633769 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 2063087 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 184400014 # The number of ROB reads -system.cpu1.rob.rob_writes 139856425 # The number of ROB writes -system.cpu1.timesIdled 1519588 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 298341063 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4812976632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38877925 # Number of Instructions Simulated -system.cpu1.committedOps 49241908 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38877925 # Number of Instructions Simulated -system.cpu1.cpi 10.813058 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.813058 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092481 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092481 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 398800057 # number of integer regfile reads -system.cpu1.int_regfile_writes 58498146 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4943 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91875872 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429758 # number of misc regfile writes -system.cpu1.icache.replacements 623101 # number of replacements -system.cpu1.icache.tagsinuse 498.730815 # Cycle average of tags in use -system.cpu1.icache.total_refs 8556871 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 623613 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.721444 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 75785780000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.730815 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974084 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974084 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8556871 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8556871 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8556871 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8556871 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8556871 # number of overall hits -system.cpu1.icache.overall_hits::total 8556871 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 673686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 673686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 673686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 673686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 673686 # number of overall misses -system.cpu1.icache.overall_misses::total 673686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10642693998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10642693998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10642693998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10642693998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10642693998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10642693998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9230557 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9230557 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9230557 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9230557 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9230557 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9230557 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072984 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.072984 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072984 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.072984 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072984 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.072984 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15797.706941 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15797.706941 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15797.706941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15797.706941 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1133998 # number of cycles access was blocked +system.cpu1.rob.rob_reads 198211439 # The number of ROB reads +system.cpu1.rob.rob_writes 154591902 # The number of ROB writes +system.cpu1.timesIdled 1579473 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 301106757 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4803892671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 43196726 # Number of Instructions Simulated +system.cpu1.committedOps 54799487 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 43196726 # Number of Instructions Simulated +system.cpu1.cpi 9.963172 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 9.963172 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.100370 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.100370 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 429674423 # number of integer regfile reads +system.cpu1.int_regfile_writes 64872300 # number of integer regfile writes +system.cpu1.fp_regfile_reads 3964 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1982 # number of floating regfile writes +system.cpu1.misc_regfile_reads 101230364 # number of misc regfile reads +system.cpu1.misc_regfile_writes 513642 # number of misc regfile writes +system.cpu1.icache.replacements 694768 # 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number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11830653994 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11830653994 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10090954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10090954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10090954 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10090954 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10090954 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10090954 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074499 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.074499 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074499 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.074499 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074499 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.074499 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15737.107717 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15737.107717 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15737.107717 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15737.107717 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1257996 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 174 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 215 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6517.229885 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5851.144186 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50044 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50044 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50044 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50044 # 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number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 695309 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 695309 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 695309 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 695309 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9048159496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 9048159496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9048159496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 9048159496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9048159496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 9048159496 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067563 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067563 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067563 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13067.356750 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068904 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068904 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068904 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068904 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13013.148824 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363581 # number of replacements -system.cpu1.dcache.tagsinuse 487.223522 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13117187 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363929 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.043258 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71474573000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.223522 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951608 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951608 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8616147 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8616147 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4254446 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4254446 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105790 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105790 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100736 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100736 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12870593 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12870593 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12870593 # number of overall hits -system.cpu1.dcache.overall_hits::total 12870593 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 410065 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 410065 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1595508 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1595508 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10912 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10912 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2005573 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2005573 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2005573 # number of overall misses -system.cpu1.dcache.overall_misses::total 2005573 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8126055000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8126055000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66044305227 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66044305227 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166791500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 166791500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95304000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 95304000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 74170360227 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 74170360227 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 74170360227 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 74170360227 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9026212 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9026212 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5849954 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5849954 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120068 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 120068 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111648 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 111648 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14876166 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14876166 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14876166 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134818 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134818 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19816.504700 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19816.504700 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41393.904153 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41393.904153 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11681.713125 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11681.713125 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8733.870968 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8733.870968 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 36982.129410 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 36982.129410 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29670016 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5568500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6658 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4456.295584 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32187.861272 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 413009 # number of replacements +system.cpu1.dcache.tagsinuse 487.394187 # Cycle average of tags in use +system.cpu1.dcache.total_refs 14990250 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 413521 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.250275 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 71474582000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.394187 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951942 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951942 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9825576 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9825576 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4872589 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4872589 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123205 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 123205 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119861 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 119861 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 14698165 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 14698165 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 14698165 # number of overall hits +system.cpu1.dcache.overall_hits::total 14698165 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 478795 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 478795 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1745196 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1745196 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14728 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14728 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10805 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10805 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2223991 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2223991 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2223991 # number of overall misses +system.cpu1.dcache.overall_misses::total 2223991 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9322511500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9322511500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 69699331710 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 69699331710 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 175643000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 175643000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94845500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 94845500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 79021843210 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 79021843210 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 79021843210 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 79021843210 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10304371 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10304371 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6617785 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6617785 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137933 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 137933 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130666 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 130666 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16922156 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16922156 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16922156 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16922156 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046465 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.046465 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263713 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.263713 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106776 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106776 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.082692 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.082692 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131425 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.131425 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131425 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.131425 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19470.778726 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19470.778726 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39937.824582 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39937.824582 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11925.787615 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11925.787615 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8777.926886 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8777.926886 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35531.548109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35531.548109 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 31184009 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5513500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4502.455819 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33213.855422 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328251 # number of writebacks -system.cpu1.dcache.writebacks::total 328251 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178277 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 178277 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432587 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1432587 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1464 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1464 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1610864 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1610864 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1610864 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1610864 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231788 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231788 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162921 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162921 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12814 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12814 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394709 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394709 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394709 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394709 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3566201462 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3566201462 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5537603585 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5537603585 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104573506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104573506 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61265506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61265506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9103805047 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9103805047 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9103805047 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9103805047 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169309741500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169309741500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40933880282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40933880282 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210243621782 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210243621782 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025679 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025679 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027850 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027850 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106723 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106723 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097709 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097709 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026533 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026533 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15385.617297 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15385.617297 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33989.501568 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33989.501568 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8160.879195 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8160.879195 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5616.051517 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5616.051517 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 373664 # number of writebacks +system.cpu1.dcache.writebacks::total 373664 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211355 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 211355 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1568704 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1568704 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1302 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1302 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1780059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1780059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1780059 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1780059 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 267440 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 267440 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 176492 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 176492 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13426 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13426 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10800 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10800 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 443932 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 443932 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 443932 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 443932 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4040609191 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4040609191 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5818534579 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5818534579 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 114031007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 114031007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61142007 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61142007 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9859143770 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9859143770 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9859143770 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9859143770 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170666816500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170666816500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40957900116 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40957900116 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 211624716616 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 211624716616 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025954 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025954 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097337 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097337 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.082653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.082653 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026234 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026234 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15108.469904 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15108.469904 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32967.695867 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32967.695867 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8493.297110 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8493.297110 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5661.296944 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5661.296944 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1667,18 +1693,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323189312111 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323189312111 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323290279244 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323290279244 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43824 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 36101 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 61677 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index c4b0f36dd..5e48f5c5e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538055 # Number of seconds simulated -sim_ticks 2538055224500 # Number of ticks simulated -final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538087 # Number of seconds simulated +sim_ticks 2538087368500 # Number of ticks simulated +final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88262 # Simulator instruction rate (inst/s) -host_op_rate 113532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3696075323 # Simulator tick rate (ticks/s) -host_mem_usage 390228 # Number of bytes of host memory used -host_seconds 686.69 # Real time elapsed on the host -sim_insts 60608338 # Number of instructions simulated -sim_ops 77960937 # Number of ops (including micro ops) simulated +host_inst_rate 89486 # Simulator instruction rate (inst/s) +host_op_rate 115106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3747392596 # Simulator tick rate (ticks/s) +host_mem_usage 390008 # Number of bytes of host memory used +host_seconds 677.29 # Real time elapsed on the host +sim_insts 60608307 # Number of instructions simulated +sim_ops 77960925 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64349 # number of replacements -system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use -system.l2c.total_refs 1966684 # Total number of references to valid blocks. -system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor +system.l2c.replacements 64372 # number of replacements +system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use +system.l2c.total_refs 1967256 # Total number of references to valid blocks. +system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387818 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1500728 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112928 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112928 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500746 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613656 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122661 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11547 # number of overall hits -system.l2c.overall_hits::cpu.inst 978702 # number of overall hits -system.l2c.overall_hits::cpu.data 500746 # number of overall hits -system.l2c.overall_hits::total 1613656 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits +system.l2c.Writeback_hits::total 608347 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits +system.l2c.overall_hits::cpu.inst 978266 # number of overall hits +system.l2c.overall_hits::cpu.data 500583 # number of overall hits +system.l2c.overall_hits::total 1613985 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2903 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133164 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133164 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12372 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143855 # number of demand (read+write) misses -system.l2c.demand_misses::total 156289 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses +system.l2c.demand_misses::total 156312 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12372 # number of overall misses -system.l2c.overall_misses::cpu.data 143855 # number of overall misses -system.l2c.overall_misses::total 156289 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3190500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu.inst 12366 # number of overall misses +system.l2c.overall_misses::cpu.data 143884 # number of overall misses +system.l2c.overall_misses::total 156312 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3194000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 658900997 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 562244999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1224396496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7068682495 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7068682495 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3190500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 658485498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 561949499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1223688997 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1101000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1101000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7073691498 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7073691498 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3194000 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198827716888 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198833036888 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026679 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015132 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.987079 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541115 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015120 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,27 +332,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51779226 # DTB read hits -system.cpu.dtb.read_misses 81574 # DTB read misses -system.cpu.dtb.write_hits 11882622 # DTB write hits -system.cpu.dtb.write_misses 18093 # DTB write misses +system.cpu.dtb.read_hits 51778790 # DTB read hits +system.cpu.dtb.read_misses 81353 # DTB read misses +system.cpu.dtb.write_hits 11881898 # DTB write hits +system.cpu.dtb.write_misses 18166 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4488 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4472 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860800 # DTB read accesses -system.cpu.dtb.write_accesses 11900715 # DTB write accesses +system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860143 # DTB read accesses +system.cpu.dtb.write_accesses 11900064 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63661848 # DTB hits -system.cpu.dtb.misses 99667 # DTB misses -system.cpu.dtb.accesses 63761515 # DTB accesses -system.cpu.itb.inst_hits 13144692 # ITB inst hits -system.cpu.itb.inst_misses 11967 # ITB inst misses +system.cpu.dtb.hits 63660688 # DTB hits +system.cpu.dtb.misses 99519 # DTB misses +system.cpu.dtb.accesses 63760207 # DTB accesses +system.cpu.itb.inst_hits 13142674 # ITB inst hits +system.cpu.itb.inst_misses 12012 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -361,122 +361,122 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2661 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13156659 # ITB inst accesses -system.cpu.itb.hits 13144692 # DTB hits -system.cpu.itb.misses 11967 # DTB misses -system.cpu.itb.accesses 13156659 # DTB accesses -system.cpu.numCycles 487285069 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154686 # ITB inst accesses +system.cpu.itb.hits 13142674 # DTB hits +system.cpu.itb.misses 12012 # DTB misses +system.cpu.itb.accesses 13154686 # DTB accesses +system.cpu.numCycles 487300785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits +system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -504,13 +504,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued @@ -523,10 +523,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued @@ -538,361 +538,361 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued -system.cpu.iq.rate 0.259591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued +system.cpu.iq.rate 0.259577 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255493 # number of nop insts executed -system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed -system.cpu.iew.exec_branches 11931891 # Number of branches executed -system.cpu.iew.exec_stores 12393835 # Number of stores executed -system.cpu.iew.exec_rate 0.253013 # Inst execution rate -system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47524907 # num instructions producing a value -system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value +system.cpu.iew.exec_nop 255111 # number of nop insts executed +system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed +system.cpu.iew.exec_branches 11930392 # Number of branches executed +system.cpu.iew.exec_stores 12393079 # Number of stores executed +system.cpu.iew.exec_rate 0.253002 # Inst execution rate +system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47523827 # num instructions producing a value +system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758719 # Number of instructions committed -system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758688 # Number of instructions committed +system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520132 # Number of memory references committed -system.cpu.commit.loads 15719739 # Number of loads committed -system.cpu.commit.membars 413350 # Number of memory barriers committed -system.cpu.commit.branches 10163894 # Number of branches committed +system.cpu.commit.refs 27520186 # Number of memory references committed +system.cpu.commit.loads 15719769 # Number of loads committed +system.cpu.commit.membars 413359 # Number of memory barriers committed +system.cpu.commit.branches 10163898 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996264 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. +system.cpu.commit.function_calls 996262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256736769 # The number of ROB reads -system.cpu.rob.rob_writes 209812510 # The number of ROB writes -system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608338 # Number of Instructions Simulated -system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated -system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558055785 # number of integer regfile reads -system.cpu.int_regfile_writes 90157820 # number of integer regfile writes -system.cpu.fp_regfile_reads 8288 # number of floating regfile reads -system.cpu.fp_regfile_writes 2908 # number of floating regfile writes -system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads -system.cpu.misc_regfile_writes 913357 # number of misc regfile writes -system.cpu.icache.replacements 991945 # number of replacements -system.cpu.icache.tagsinuse 511.576100 # Cycle average of tags in use -system.cpu.icache.total_refs 12062971 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992457 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.154654 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225347000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576100 # Average occupied blocks per requestor +system.cpu.rob.rob_reads 256700614 # The number of ROB reads +system.cpu.rob.rob_writes 209796185 # The number of ROB writes +system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60608307 # Number of Instructions Simulated +system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated +system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558050322 # number of integer regfile reads +system.cpu.int_regfile_writes 90161620 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads +system.cpu.misc_regfile_writes 913390 # number of misc regfile writes +system.cpu.icache.replacements 991554 # number of replacements +system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use +system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits -system.cpu.icache.overall_hits::total 12062971 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1077319 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1077319 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1077319 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits +system.cpu.icache.overall_hits::total 12061582 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # 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number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6662.821101 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84824 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84824 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84824 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84824 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84824 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992495 # 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number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # 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Cycle average of tags in use +system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908205 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908205 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258424 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258424 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283313 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283313 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285772 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285772 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21166629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21166629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21166629 # number of overall hits -system.cpu.dcache.overall_hits::total 21166629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 766922 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 766922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2994004 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2994004 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13808 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13808 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -914,16 +914,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |