diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
5 files changed, 6020 insertions, 6022 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 9fdc8420f..d9f8483a2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,114 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523518 # Number of seconds simulated -sim_ticks 2523517846500 # Number of ticks simulated -final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523205 # Number of seconds simulated +sim_ticks 2523204701000 # Number of ticks simulated +final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18924 # Simulator instruction rate (inst/s) -host_op_rate 24341 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 788054860 # Simulator tick rate (ticks/s) -host_mem_usage 403628 # Number of bytes of host memory used -host_seconds 3202.21 # Real time elapsed on the host -sim_insts 60597240 # Number of instructions simulated -sim_ops 77945362 # Number of ops (including micro ops) simulated +host_inst_rate 55288 # Simulator instruction rate (inst/s) +host_op_rate 71140 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2313219719 # Simulator tick rate (ticks/s) +host_mem_usage 409988 # Number of bytes of host memory used +host_seconds 1090.78 # Real time elapsed on the host +sim_insts 60306320 # Number of instructions simulated +sim_ops 77597310 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096842 # Total number of read requests seen -system.physmem.writeReqs 813129 # Total number of write requests seen -system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966197888 # Total number of bytes read from memory -system.physmem.bytesWritten 52040256 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096856 # Total number of read requests seen +system.physmem.writeReqs 813138 # Total number of write requests seen +system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966198784 # Total number of bytes read from memory +system.physmem.bytesWritten 52040832 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis +system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523516727500 # Total gap between requests +system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523203522000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154598 # Categorize read packet sizes +system.physmem.readPktSize::6 154612 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1937150 # categorize write packet sizes +system.physmem.writePktSize::2 1943854 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59111 # categorize write packet sizes +system.physmem.writePktSize::6 59120 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +129,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,72 +165,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests -system.physmem.totBusLat 60385948000 # Total cycles spent in databus access -system.physmem.totBankLat 16343502000 # Total cycles spent in bank access -system.physmem.avgQLat 21736.41 # Average queueing delay per request -system.physmem.avgBankLat 1082.60 # Average bank access latency per request +system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests +system.physmem.totBusLat 60386192000 # Total cycles spent in databus access +system.physmem.totBankLat 16356620000 # Total cycles spent in bank access +system.physmem.avgQLat 21743.10 # Average queueing delay per request +system.physmem.avgBankLat 1083.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26819.01 # Average memory access latency -system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26826.57 # Average memory access latency +system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 11.85 # Average write queue length over time -system.physmem.readRowHits 15052691 # Number of row buffer hits during reads -system.physmem.writeRowHits 784814 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.68 # Average write queue length over time +system.physmem.readRowHits 15052450 # Number of row buffer hits during reads +system.physmem.writeRowHits 784654 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes -system.physmem.avgGap 158612.28 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes +system.physmem.avgGap 158592.36 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048937 # DTB read hits -system.cpu.checker.dtb.read_misses 7310 # DTB read misses -system.cpu.checker.dtb.write_hits 11294198 # DTB write hits +system.cpu.checker.dtb.read_hits 14986991 # DTB read hits +system.cpu.checker.dtb.read_misses 7307 # DTB read misses +system.cpu.checker.dtb.write_hits 11227488 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056247 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296387 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994298 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229677 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26343135 # DTB hits -system.cpu.checker.dtb.misses 9499 # DTB misses -system.cpu.checker.dtb.accesses 26352634 # DTB accesses -system.cpu.checker.itb.inst_hits 61775993 # ITB inst hits +system.cpu.checker.dtb.hits 26214479 # DTB hits +system.cpu.checker.dtb.misses 9496 # DTB misses +system.cpu.checker.dtb.accesses 26223975 # DTB accesses +system.cpu.checker.itb.inst_hits 61480313 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -263,36 +263,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61780464 # ITB inst accesses -system.cpu.checker.itb.hits 61775993 # DTB hits +system.cpu.checker.itb.inst_accesses 61484784 # ITB inst accesses +system.cpu.checker.itb.hits 61480313 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61780464 # DTB accesses -system.cpu.checker.numCycles 78235922 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484784 # DTB accesses +system.cpu.checker.numCycles 77883110 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51295505 # DTB read hits -system.cpu.dtb.read_misses 73548 # DTB read misses -system.cpu.dtb.write_hits 11769416 # DTB write hits -system.cpu.dtb.write_misses 17308 # DTB write misses +system.cpu.dtb.read_hits 51212683 # DTB read hits +system.cpu.dtb.read_misses 73387 # DTB read misses +system.cpu.dtb.write_hits 11701466 # DTB write hits +system.cpu.dtb.write_misses 17011 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7698 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7759 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51369053 # DTB read accesses -system.cpu.dtb.write_accesses 11786724 # DTB write accesses +system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51286070 # DTB read accesses +system.cpu.dtb.write_accesses 11718477 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63064921 # DTB hits -system.cpu.dtb.misses 90856 # DTB misses -system.cpu.dtb.accesses 63155777 # DTB accesses -system.cpu.itb.inst_hits 11599470 # ITB inst hits -system.cpu.itb.inst_misses 11387 # ITB inst misses +system.cpu.dtb.hits 62914149 # DTB hits +system.cpu.dtb.misses 90398 # DTB misses +system.cpu.dtb.accesses 63004547 # DTB accesses +system.cpu.itb.inst_hits 11530598 # ITB inst hits +system.cpu.itb.inst_misses 11503 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -301,122 +301,122 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5136 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5166 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11610857 # ITB inst accesses -system.cpu.itb.hits 11599470 # DTB hits -system.cpu.itb.misses 11387 # DTB misses -system.cpu.itb.accesses 11610857 # DTB accesses -system.cpu.numCycles 470965317 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11542101 # ITB inst accesses +system.cpu.itb.hits 11530598 # DTB hits +system.cpu.itb.misses 11503 # DTB misses +system.cpu.itb.accesses 11542101 # DTB accesses +system.cpu.numCycles 469830472 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits +system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -444,383 +444,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued -system.cpu.iq.rate 0.262043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued +system.cpu.iq.rate 0.261848 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221628 # number of nop insts executed -system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed -system.cpu.iew.exec_branches 11537560 # Number of branches executed -system.cpu.iew.exec_stores 12281337 # Number of stores executed -system.cpu.iew.exec_rate 0.257635 # Inst execution rate -system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47183541 # num instructions producing a value -system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value +system.cpu.iew.exec_nop 221038 # number of nop insts executed +system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed +system.cpu.iew.exec_branches 11477980 # Number of branches executed +system.cpu.iew.exec_stores 12213052 # Number of stores executed +system.cpu.iew.exec_rate 0.257448 # Inst execution rate +system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47051195 # num instructions producing a value +system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747621 # Number of instructions committed -system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456701 # Number of instructions committed +system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514551 # Number of memory references committed -system.cpu.commit.loads 15716032 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023101 # Number of branches committed +system.cpu.commit.refs 27385892 # Number of memory references committed +system.cpu.commit.loads 15654083 # Number of loads committed +system.cpu.commit.membars 403583 # Number of memory barriers committed +system.cpu.commit.branches 9961154 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134175 # Number of committed integer instructions. -system.cpu.commit.function_calls 995982 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68853054 # Number of committed integer instructions. +system.cpu.commit.function_calls 991222 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239713879 # The number of ROB reads -system.cpu.rob.rob_writes 197204165 # The number of ROB writes -system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597240 # Number of Instructions Simulated -system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated -system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 549724993 # number of integer regfile reads -system.cpu.int_regfile_writes 88045460 # number of integer regfile writes -system.cpu.fp_regfile_reads 8276 # number of floating regfile reads -system.cpu.fp_regfile_writes 2926 # number of floating regfile writes -system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads -system.cpu.misc_regfile_writes 912900 # number of misc regfile writes -system.cpu.icache.replacements 981280 # number of replacements -system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use -system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10533801 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10533801 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10533801 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10533801 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10533801 # number of overall hits -system.cpu.icache.overall_hits::total 10533801 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061888 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061888 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061888 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061888 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061888 # number of overall misses -system.cpu.icache.overall_misses::total 1061888 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13967491489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13967491489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13967491489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13967491489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13967491489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13967491489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11595689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11595689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11595689 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11595689 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11595689 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11595689 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091576 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5396 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1220 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.808581 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 610 # average number of cycles each access was blocked +system.cpu.rob.rob_reads 238273902 # The number of ROB reads +system.cpu.rob.rob_writes 196332947 # The number of ROB writes +system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60306320 # Number of Instructions Simulated +system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated +system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547824488 # number of integer regfile reads +system.cpu.int_regfile_writes 87698032 # number of integer regfile writes +system.cpu.fp_regfile_reads 8340 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads +system.cpu.misc_regfile_writes 831851 # number of misc regfile writes +system.cpu.icache.replacements 979772 # number of replacements +system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use +system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits +system.cpu.icache.overall_hits::total 10466836 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses +system.cpu.icache.overall_misses::total 1059904 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80057 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80057 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80057 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80057 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80057 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981831 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981831 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981831 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981831 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981831 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11353310491 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11353310491 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11353310491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11353310491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11353310491 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11353310491 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980321 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980321 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980321 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11335281493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11335281493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11335281493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11335281493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11335281493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11335281493 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084672 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.084672 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.084672 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.406015 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.406015 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085048 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085048 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085048 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.826353 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.826353 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64370 # number of replacements -system.cpu.l2cache.tagsinuse 51358.666800 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1910788 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129761 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.725441 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2488452468500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36927.008868 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 28.274765 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8177.411143 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6225.971675 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563461 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000431 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64384 # number of replacements +system.cpu.l2cache.tagsinuse 51365.557849 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1909698 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129778 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.715114 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2488155004000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36926.744718 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 36.464010 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003926 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8168.761699 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6233.583496 # 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number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607596 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607596 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 78725 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10899 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966625 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499971 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1556220 # 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average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.165453 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.165453 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -941,161 +941,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643581 # number of replacements -system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use -system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks. +system.cpu.dcache.replacements 643386 # number of replacements +system.cpu.dcache.tagsinuse 511.994223 # Cycle average of tags in use +system.cpu.dcache.total_refs 21524162 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643898 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.427906 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.994223 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21105442 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21105442 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21105442 # number of overall hits -system.cpu.dcache.overall_hits::total 21105442 # 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 296044 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285756 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285756 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24798531 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24798531 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24798531 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24798531 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050305 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050305 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288884 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288884 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35129.315689 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35129.315689 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13276.813938 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13276.813938 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30757.883639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30757.883639 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32046 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.377752 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.697211 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13769851 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13769851 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7260574 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7260574 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243031 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243031 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21030425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21030425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21030425 # number of overall hits +system.cpu.dcache.overall_hits::total 21030425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731035 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731035 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2961528 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2961528 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13553 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13553 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692563 # number of overall misses +system.cpu.dcache.overall_misses::total 3692563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9558145500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9558145500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 103975545233 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 103975545233 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 229500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 229500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113533690733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113533690733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113533690733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113533690733 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14500886 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14500886 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222102 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222102 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256584 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256584 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247612 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247612 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24722988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24722988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24722988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24722988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050413 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050413 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289718 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052821 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052821 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks -system.cpu.dcache.writebacks::total 607832 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345983 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345983 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks +system.cpu.dcache.writebacks::total 607596 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1117,16 +1117,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index de425fd79..69e508f78 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,131 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603185 # Number of seconds simulated -sim_ticks 2603185215000 # Number of ticks simulated -final_tick 2603185215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.092969 # Number of seconds simulated +sim_ticks 1092968826500 # Number of ticks simulated +final_tick 1092968826500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24146 # Simulator instruction rate (inst/s) -host_op_rate 31077 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 996702828 # Simulator tick rate (ticks/s) -host_mem_usage 410224 # Number of bytes of host memory used -host_seconds 2611.80 # Real time elapsed on the host -sim_insts 63063952 # Number of instructions simulated -sim_ops 81166306 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4383412 # Number of bytes read from this memory +host_inst_rate 64747 # Simulator instruction rate (inst/s) +host_op_rate 83356 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1148881552 # Simulator tick rate (ticks/s) +host_mem_usage 415112 # Number of bytes of host memory used +host_seconds 951.33 # Real time elapsed on the host +sim_insts 61595972 # Number of instructions simulated +sim_ops 79298956 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 59 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 351 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 410 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 59 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 351 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 410 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 59 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 351 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 408768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4356148 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5252400 # Number of bytes read from this memory -system.physmem.bytes_read::total 131570212 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4280832 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 407360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5254000 # Number of bytes read from this memory +system.physmem.bytes_read::total 59186980 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 407360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 816128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4265536 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7309968 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6192 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68563 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7292880 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68137 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82095 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302347 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66888 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66649 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824172 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46523977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1683865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2017682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50542010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1644459 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1157096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2808086 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1644459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46523977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1690395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3174778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53350096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302347 # Total number of read requests seen -system.physmem.writeReqs 824172 # Total number of write requests seen -system.physmem.cpureqs 284728 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979350208 # Total number of bytes read from memory -system.physmem.bytesWritten 52747008 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131570212 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7309968 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 346 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14078 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956557 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956475 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955970 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956952 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956364 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956322 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956317 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956502 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955936 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51032 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50766 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50996 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51588 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51566 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51588 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51672 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51523 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823485 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44611322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 373998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3985610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 372710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4807090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54152487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 373998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 372710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 746707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3902706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15554 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2754282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6672542 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3902706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44611322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 373998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4001164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 372710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7561372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60825028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257887 # Total number of read requests seen +system.physmem.writeReqs 823485 # Total number of write requests seen +system.physmem.cpureqs 281561 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400504768 # Total number of bytes read from memory +system.physmem.bytesWritten 52703040 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59186980 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7292880 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 99 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12576 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391078 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 391295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390638 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 390722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391599 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 391075 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 391119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 391200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 391075 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 390939 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51048 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50959 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50974 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51767 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51577 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51575 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51637 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51582 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1182222 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603183939000 # Total gap between requests +system.physmem.numWrRetry 1176096 # Number of times wr buffer was full causing retry +system.physmem.totGap 1092967540000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 15138816 # Categorize read packet sizes +system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163426 # Categorize read packet sizes +system.physmem.readPktSize::6 162934 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1939506 # categorize write packet sizes +system.physmem.writePktSize::2 1932932 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66888 # categorize write packet sizes +system.physmem.writePktSize::6 66649 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,31 +152,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 14078 # categorize neither packet sizes +system.physmem.neitherpktsize::6 12576 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1062295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 996413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 951405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 986255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2765519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2772335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5446641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 44668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 31245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 58473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 38578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 65793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 496879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 431716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 387410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 401103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1104120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1111115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2162095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 27972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 13923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 13366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 13210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 24040 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 31247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -170,309 +188,291 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31462 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 332610890470 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 410507230470 # Sum of mem lat for all requests -system.physmem.totBusLat 61208004000 # Total cycles spent in databus access -system.physmem.totBankLat 16688336000 # Total cycles spent in bank access -system.physmem.avgQLat 21736.43 # Average queueing delay per request -system.physmem.avgBankLat 1090.60 # Average bank access latency per request +system.physmem.totQLat 164150101325 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 197462743325 # Sum of mem lat for all requests +system.physmem.totBusLat 25031152000 # Total cycles spent in databus access +system.physmem.totBankLat 8281490000 # Total cycles spent in bank access +system.physmem.avgQLat 26231.33 # Average queueing delay per request +system.physmem.avgBankLat 1323.39 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26827.03 # Average memory access latency -system.physmem.avgRdBW 376.21 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31554.72 # Average memory access latency +system.physmem.avgRdBW 366.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 48.22 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 54.15 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.48 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 12.97 # Average write queue length over time -system.physmem.readRowHits 15255805 # Number of row buffer hits during reads -system.physmem.writeRowHits 789541 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes -system.physmem.avgGap 161422.56 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 73139 # number of replacements -system.l2c.tagsinuse 53098.784053 # Cycle average of tags in use -system.l2c.total_refs 1903330 # Total number of references to valid blocks. -system.l2c.sampled_refs 138315 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.760836 # Average number of references to valid blocks. +system.physmem.busUtil 2.59 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.18 # Average read queue length over time +system.physmem.avgWrQLen 9.65 # Average write queue length over time +system.physmem.readRowHits 6229568 # Number of row buffer hits during reads +system.physmem.writeRowHits 789194 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 95.84 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13396281803 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1815064 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171985608060 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 185388263090 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036771 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030877 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017352 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801526 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809758 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.804992 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772837 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.737794 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.758845 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.564146 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.568739 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566661 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.243924 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245125 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097021 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.243924 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000344 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245125 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097021 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42305.825574 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45005.592047 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42204.637453 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10063.119052 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10164.958245 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10106.257920 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.617418 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.299020 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10055.683159 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36480.013486 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42399.350868 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39732.745877 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37013.277426 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42596.874934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40110.722150 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52547.272727 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39496.977167 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37013.277426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72178.352941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41888.785195 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42596.874934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40110.722150 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -665,27 +665,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9024363 # DTB read hits -system.cpu0.dtb.read_misses 35062 # DTB read misses -system.cpu0.dtb.write_hits 5257895 # DTB write hits -system.cpu0.dtb.write_misses 6477 # DTB write misses +system.cpu0.dtb.read_hits 8918270 # DTB read hits +system.cpu0.dtb.read_misses 33761 # DTB read misses +system.cpu0.dtb.write_hits 5143475 # DTB write hits +system.cpu0.dtb.write_misses 6030 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2160 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2137 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1055 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 365 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9059425 # DTB read accesses -system.cpu0.dtb.write_accesses 5264372 # DTB write accesses +system.cpu0.dtb.perms_faults 538 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8952031 # DTB read accesses +system.cpu0.dtb.write_accesses 5149505 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14282258 # DTB hits -system.cpu0.dtb.misses 41539 # DTB misses -system.cpu0.dtb.accesses 14323797 # DTB accesses -system.cpu0.itb.inst_hits 4307156 # ITB inst hits -system.cpu0.itb.inst_misses 5205 # ITB inst misses +system.cpu0.dtb.hits 14061745 # DTB hits +system.cpu0.dtb.misses 39791 # DTB misses +system.cpu0.dtb.accesses 14101536 # DTB accesses +system.cpu0.itb.inst_hits 4226389 # ITB inst hits +system.cpu0.itb.inst_misses 5148 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -694,538 +694,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1360 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1370 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4312361 # ITB inst accesses -system.cpu0.itb.hits 4307156 # DTB hits -system.cpu0.itb.misses 5205 # DTB misses -system.cpu0.itb.accesses 4312361 # DTB accesses -system.cpu0.numCycles 69075583 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4231537 # ITB inst accesses +system.cpu0.itb.hits 4226389 # DTB hits +system.cpu0.itb.misses 5148 # DTB misses +system.cpu0.itb.accesses 4231537 # DTB accesses +system.cpu0.numCycles 67785734 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6134621 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4681383 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 299233 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3810859 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2992358 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6012491 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4585363 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 296577 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3765620 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2919015 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 688987 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 28743 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12013253 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32740564 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6134621 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3681345 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7677557 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1482239 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 64559 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21828282 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 53864 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 90312 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 236 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4305560 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 159104 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2370 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42798314 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.987162 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.368020 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 674578 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 28863 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11763968 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32049970 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6012491 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3593593 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7526717 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1460555 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 62547 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20715231 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 54522 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85492 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4224665 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 156872 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2292 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41263116 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.003783 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.384047 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35128127 82.08% 82.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 610328 1.43% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 795353 1.86% 85.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 689183 1.61% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 781372 1.83% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 569733 1.33% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 711695 1.66% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 364225 0.85% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3148298 7.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33743827 81.78% 81.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 566856 1.37% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818944 1.98% 85.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676218 1.64% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773991 1.88% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 560705 1.36% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 670652 1.63% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352961 0.86% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098962 7.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42798314 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088810 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.473982 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12517044 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21792466 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6901256 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 586970 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1000578 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 954803 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64851 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40861344 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213562 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1000578 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13092600 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5813788 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13806762 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6861684 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2222902 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39740402 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2257 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 444272 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1240471 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 77 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40148585 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 179562690 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 179528337 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34353 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31678708 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8469876 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 458191 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 414927 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5465728 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7827563 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5820560 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1149873 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1213359 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37598856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 946637 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37967135 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 82667 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6387129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13438267 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 258027 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42798314 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.887118 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.498670 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41263116 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088698 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.472813 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12272697 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20662299 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6831890 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 510283 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 985947 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 936613 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64715 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40060631 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213244 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 985947 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12836550 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5831447 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12738222 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6726939 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2144011 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38954643 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2110 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 419770 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1235917 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39310777 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175935751 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175901847 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 33904 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30931608 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8379168 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411632 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370766 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5325827 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7663556 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5690026 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120184 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1252239 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36870649 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 896350 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37273811 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81085 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6313763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13211798 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257333 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41263116 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.903320 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.511259 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27228481 63.62% 63.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6024200 14.08% 77.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3238541 7.57% 85.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2496476 5.83% 91.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2116280 4.94% 96.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 952748 2.23% 98.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 498209 1.16% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 188721 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54658 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26116346 63.29% 63.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5727985 13.88% 77.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3164328 7.67% 84.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2471717 5.99% 90.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2127646 5.16% 95.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 929575 2.25% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 487199 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 186194 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52126 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42798314 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41263116 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25719 2.40% 2.40% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 458 0.04% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 838558 78.31% 80.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 206136 19.25% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25847 2.42% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.04% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842941 78.82% 81.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200262 18.72% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22801553 60.06% 60.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48143 0.13% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9487186 24.99% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5577397 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52409 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22347449 59.95% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46908 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9376305 25.16% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5450017 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37967135 # Type of FU issued -system.cpu0.iq.rate 0.549646 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070871 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028205 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 119919123 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44940813 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35094596 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8245 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4688 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3877 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38981568 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4289 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 319568 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37273811 # Type of FU issued +system.cpu0.iq.rate 0.549877 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1069503 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028693 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116992528 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44088817 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34369527 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8360 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3860 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38286519 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307254 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1406645 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2495 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13426 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 546497 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1385688 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2397 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13227 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538655 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149373 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5419 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192760 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5477 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1000578 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4177293 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 102909 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38663154 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 84882 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7827563 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5820560 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 615194 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 41110 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3269 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13426 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 151880 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 119782 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 271662 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37584827 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9341263 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 382308 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 985947 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4198442 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 101973 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37885007 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 86572 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7663556 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5690026 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571892 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40888 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13227 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150955 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118096 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 269051 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36896358 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9233299 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 377453 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117661 # number of nop insts executed -system.cpu0.iew.exec_refs 14871823 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4965899 # Number of branches executed -system.cpu0.iew.exec_stores 5530560 # Number of stores executed -system.cpu0.iew.exec_rate 0.544112 # Inst execution rate -system.cpu0.iew.wb_sent 37390069 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35098473 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18662098 # num instructions producing a value -system.cpu0.iew.wb_consumers 35837598 # num instructions consuming a value +system.cpu0.iew.exec_nop 118008 # number of nop insts executed +system.cpu0.iew.exec_refs 14636338 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4860481 # Number of branches executed +system.cpu0.iew.exec_stores 5403039 # Number of stores executed +system.cpu0.iew.exec_rate 0.544309 # Inst execution rate +system.cpu0.iew.wb_sent 36702505 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34373387 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18311880 # num instructions producing a value +system.cpu0.iew.wb_consumers 35235348 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.508117 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520741 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.507089 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519702 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6206788 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688610 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 235451 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41797736 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.765444 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.723461 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6136748 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 639017 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232971 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40277169 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.776860 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.743491 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29752237 71.18% 71.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5970878 14.29% 85.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1965315 4.70% 90.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 999760 2.39% 92.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 803961 1.92% 94.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 518760 1.24% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395530 0.95% 96.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 220150 0.53% 97.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1171145 2.80% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28628964 71.08% 71.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5718437 14.20% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1895078 4.71% 89.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 977858 2.43% 92.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 774389 1.92% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 507385 1.26% 95.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386799 0.96% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 213802 0.53% 97.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1174457 2.92% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41797736 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24265529 # Number of instructions committed -system.cpu0.commit.committedOps 31993822 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40277169 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23678178 # Number of instructions committed +system.cpu0.commit.committedOps 31289712 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11694981 # Number of memory references committed -system.cpu0.commit.loads 6420918 # Number of loads committed -system.cpu0.commit.membars 234476 # Number of memory barriers committed -system.cpu0.commit.branches 4347395 # Number of branches committed +system.cpu0.commit.refs 11429239 # Number of memory references committed +system.cpu0.commit.loads 6277868 # Number of loads committed +system.cpu0.commit.membars 229666 # Number of memory barriers committed +system.cpu0.commit.branches 4244753 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28261624 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500034 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1171145 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27646281 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489273 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1174457 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77942939 # The number of ROB reads -system.cpu0.rob.rob_writes 77403720 # The number of ROB writes -system.cpu0.timesIdled 364282 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26277269 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137251054 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24184787 # Number of Instructions Simulated -system.cpu0.committedOps 31913080 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24184787 # Number of Instructions Simulated -system.cpu0.cpi 2.856158 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.856158 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.350121 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.350121 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 175453235 # number of integer regfile reads -system.cpu0.int_regfile_writes 34873256 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3235 # number of floating regfile reads -system.cpu0.fp_regfile_writes 908 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13424511 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527689 # number of misc regfile writes -system.cpu0.icache.replacements 399628 # number of replacements -system.cpu0.icache.tagsinuse 511.593033 # Cycle average of tags in use -system.cpu0.icache.total_refs 3873847 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 400140 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.681229 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6818802000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.593033 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999205 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999205 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3873847 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3873847 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3873847 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3873847 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3873847 # number of overall hits -system.cpu0.icache.overall_hits::total 3873847 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 431582 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 431582 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 431582 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 431582 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 431582 # number of overall misses -system.cpu0.icache.overall_misses::total 431582 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5855735994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5855735994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5855735994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5855735994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5855735994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5855735994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4305429 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4305429 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4305429 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4305429 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4305429 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4305429 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100241 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100241 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100241 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100241 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100241 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100241 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13568.072797 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13568.072797 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13568.072797 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13568.072797 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13568.072797 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13568.072797 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2448 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75678018 # The number of ROB reads +system.cpu0.rob.rob_writes 75840987 # The number of ROB writes +system.cpu0.timesIdled 360810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26522618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2118110205 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23597436 # Number of Instructions Simulated +system.cpu0.committedOps 31208970 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23597436 # Number of Instructions Simulated +system.cpu0.cpi 2.872589 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.872589 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.348118 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.348118 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 172012852 # number of integer regfile reads +system.cpu0.int_regfile_writes 34120799 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads +system.cpu0.fp_regfile_writes 892 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13056447 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451188 # number of misc regfile writes +system.cpu0.icache.replacements 392549 # number of replacements +system.cpu0.icache.tagsinuse 511.079018 # Cycle average of tags in use +system.cpu0.icache.total_refs 3800627 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393061 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.669306 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6496390000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.079018 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998201 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998201 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3800627 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3800627 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3800627 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3800627 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3800627 # number of overall hits +system.cpu0.icache.overall_hits::total 3800627 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423907 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423907 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423907 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423907 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423907 # number of overall misses +system.cpu0.icache.overall_misses::total 423907 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5778558992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5778558992 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5778558992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5778558992 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5778558992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5778558992 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4224534 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4224534 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4224534 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4224534 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4224534 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4224534 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100344 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100344 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100344 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100344 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100344 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100344 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13631.666833 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13631.666833 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13631.666833 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13631.666833 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3110 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 142 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.239437 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.326797 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31419 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31419 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31419 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31419 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31419 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31419 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400163 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 400163 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 400163 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 400163 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 400163 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 400163 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4791432494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4791432494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4791432494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4791432494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4791432494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4791432494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30826 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30826 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30826 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30826 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30826 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30826 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393081 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393081 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393081 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393081 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393081 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393081 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4722265492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4722265492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4722265492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4722265492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4722265492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4722265492 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092944 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.092944 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.092944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11973.701951 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11973.701951 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11973.701951 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093047 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093047 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093047 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12013.466670 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 274722 # number of replacements -system.cpu0.dcache.tagsinuse 476.919366 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9525271 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275234 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.607901 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 276186 # number of replacements +system.cpu0.dcache.tagsinuse 460.207954 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9271152 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276698 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.506393 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.919366 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931483 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931483 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5895102 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5895102 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3238989 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3238989 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174455 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174455 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171581 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171581 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9134091 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9134091 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9134091 # number of overall hits -system.cpu0.dcache.overall_hits::total 9134091 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 390587 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 390587 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1579573 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1579573 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8896 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8896 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7728 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7728 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1970160 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1970160 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1970160 # number of overall misses -system.cpu0.dcache.overall_misses::total 1970160 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5389048500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5389048500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60454939374 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60454939374 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88150000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88150000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50211500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50211500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 65843987874 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 65843987874 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 65843987874 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 65843987874 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6285689 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6285689 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818562 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4818562 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183351 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183351 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179309 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179309 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11104251 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11104251 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11104251 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11104251 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062139 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062139 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327810 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.327810 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048519 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048519 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043099 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043099 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177424 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.177424 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177424 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.177424 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.306362 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.306362 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38272.963246 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38272.963246 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9908.947842 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9908.947842 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6497.347308 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6497.347308 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33420.629733 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33420.629733 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8059 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2986 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 556 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.494604 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 37.325000 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 460.207954 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.898844 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.898844 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5791916 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5791916 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159128 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159128 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139197 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139197 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137104 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137104 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8951044 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8951044 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8951044 # number of overall hits +system.cpu0.dcache.overall_hits::total 8951044 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 391497 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 391497 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1585211 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1585211 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8805 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8805 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7503 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7503 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976708 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976708 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976708 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976708 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5419802000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5419802000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59847292371 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 59847292371 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88405500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88405500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46738000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46738000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65267094371 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65267094371 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65267094371 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65267094371 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6183413 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6183413 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744339 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744339 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144607 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144607 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10927752 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10927752 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10927752 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10927752 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063314 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063314 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334127 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334127 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059492 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059492 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051885 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051885 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180889 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.180889 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180889 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.180889 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13843.789352 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13843.789352 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37753.518220 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 37753.518220 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10040.374787 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10040.374787 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6229.241637 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6229.241637 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33018.075695 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33018.075695 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8715 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3535 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 594 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.671717 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 42.590361 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255180 # number of writebacks -system.cpu0.dcache.writebacks::total 255180 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202008 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202008 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1448555 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1448555 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650563 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1650563 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650563 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1650563 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188579 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188579 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131018 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131018 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8412 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8412 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7726 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7726 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319597 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319597 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319597 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319597 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2343972000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2343972000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029495991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029495991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66259000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66259000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34759500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34759500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6373467991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6373467991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6373467991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6373467991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432446000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432446000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199878877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199878877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14632324877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14632324877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030001 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030001 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045879 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045879 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043088 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043088 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028781 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028781 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12429.655476 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12429.655476 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30755.285465 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30755.285465 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7876.723728 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7876.723728 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4499.029252 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4499.029252 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256562 # number of writebacks +system.cpu0.dcache.writebacks::total 256562 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202833 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202833 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454685 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454685 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 458 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 458 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657518 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657518 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657518 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657518 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188664 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188664 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130526 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130526 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8347 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8347 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7503 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7503 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319190 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319190 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319190 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319190 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2355812500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2355812500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3979098490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3979098490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66495500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66495500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31732000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31732000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6334910990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6334910990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6334910990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6334910990 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504511500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504511500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128583377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128583377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14633094877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14633094877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030511 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030511 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027512 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027512 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056398 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056398 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051885 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051885 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12486.815185 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12486.815185 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30485.102508 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30485.102508 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7966.395112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7966.395112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4229.241637 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4229.241637 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1235,27 +1235,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43034108 # DTB read hits -system.cpu1.dtb.read_misses 42641 # DTB read misses -system.cpu1.dtb.write_hits 7001737 # DTB write hits -system.cpu1.dtb.write_misses 11814 # DTB write misses +system.cpu1.dtb.read_hits 42721233 # DTB read hits +system.cpu1.dtb.read_misses 41267 # DTB read misses +system.cpu1.dtb.write_hits 6827437 # DTB write hits +system.cpu1.dtb.write_misses 11457 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2370 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2838 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2630 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43076749 # DTB read accesses -system.cpu1.dtb.write_accesses 7013551 # DTB write accesses +system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42762500 # DTB read accesses +system.cpu1.dtb.write_accesses 6838894 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50035845 # DTB hits -system.cpu1.dtb.misses 54455 # DTB misses -system.cpu1.dtb.accesses 50090300 # DTB accesses -system.cpu1.itb.inst_hits 7783284 # ITB inst hits -system.cpu1.itb.inst_misses 5669 # ITB inst misses +system.cpu1.dtb.hits 49548670 # DTB hits +system.cpu1.dtb.misses 52724 # DTB misses +system.cpu1.dtb.accesses 49601394 # DTB accesses +system.cpu1.itb.inst_hits 7583980 # ITB inst hits +system.cpu1.itb.inst_misses 5601 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1264,542 +1264,538 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1584 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1561 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1542 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1591 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7788953 # ITB inst accesses -system.cpu1.itb.hits 7783284 # DTB hits -system.cpu1.itb.misses 5669 # DTB misses -system.cpu1.itb.accesses 7788953 # DTB accesses -system.cpu1.numCycles 409060969 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7589581 # ITB inst accesses +system.cpu1.itb.hits 7583980 # DTB hits +system.cpu1.itb.misses 5601 # DTB misses +system.cpu1.itb.accesses 7589581 # DTB accesses +system.cpu1.numCycles 406854445 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9019142 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7341577 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 421290 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 5896961 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5059614 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8781590 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7165099 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 410272 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5784510 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 4949628 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 812166 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 44802 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 19538569 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61710735 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9019142 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5871780 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13457716 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3440559 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 72159 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78167878 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5662 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 49809 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 140998 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7781352 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 538014 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3102 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 113786982 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.664391 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.995438 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 773605 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 42847 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 18987687 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60514486 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8781590 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5723233 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13164545 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3370379 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 67214 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77426772 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4687 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 46358 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129737 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 707 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7581976 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 531329 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3060 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 112134243 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.659620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.988948 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100336589 88.18% 88.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 821334 0.72% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 966420 0.85% 89.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1725152 1.52% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1418529 1.25% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 601242 0.53% 93.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1958088 1.72% 94.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 436465 0.38% 95.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5523163 4.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 98977030 88.27% 88.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796888 0.71% 88.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 939707 0.84% 89.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1694875 1.51% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1403619 1.25% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 573280 0.51% 93.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1928107 1.72% 94.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410374 0.37% 95.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5410363 4.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 113786982 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022048 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.150860 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20926147 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77797918 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12266013 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 542191 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2254713 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1149115 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100993 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71511004 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 338807 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2254713 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22129407 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32117603 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41299485 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11510444 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4475330 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67658360 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19594 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 697706 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3178110 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 32539 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 70993653 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 310596355 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 310537273 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59082 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50200074 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20793579 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 474201 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 414075 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8134070 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12921007 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8155176 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1083797 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1589261 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62166896 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1195329 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89153414 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 99788 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13746763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36760953 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 275268 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 113786982 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783512 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519359 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 112134243 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021584 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.148737 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20329334 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77067438 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11999240 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 528326 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2209905 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105816 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98089 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69983071 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327113 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2209905 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21512186 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32033439 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40715711 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11249430 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4413572 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 66189803 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19593 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 681290 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3157378 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32035 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69538015 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 303909752 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 303850528 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59224 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49060717 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20477298 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 445152 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388313 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7961235 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12608499 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7947542 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1037744 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1535939 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60784720 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1155099 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87803920 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 97322 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13491429 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36062520 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 274254 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 112134243 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.783025 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519999 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83183185 73.10% 73.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8664055 7.61% 80.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4355929 3.83% 84.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3746204 3.29% 87.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10471181 9.20% 97.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1956933 1.72% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1074012 0.94% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 258436 0.23% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 77047 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 82080142 73.20% 73.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8453890 7.54% 80.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4228870 3.77% 84.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3673146 3.28% 87.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10396618 9.27% 97.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1923791 1.72% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1051838 0.94% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 251187 0.22% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 74761 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 113786982 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 112134243 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29283 0.37% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 991 0.01% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7571422 95.88% 96.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 294824 3.73% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29715 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7547628 96.04% 96.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 280810 3.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37493479 42.06% 42.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61246 0.07% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43910750 49.25% 91.73% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7372221 8.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36673483 41.77% 42.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59172 0.07% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1514 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43579800 49.63% 91.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7175925 8.17% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89153414 # Type of FU issued -system.cpu1.iq.rate 0.217947 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7896520 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088572 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300129512 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 77117892 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54483079 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14896 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8093 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96728092 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7845 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 354516 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87803920 # Type of FU issued +system.cpu1.iq.rate 0.215812 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7859149 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089508 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 295735701 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75439999 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53226631 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15376 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8066 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6868 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95340871 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8201 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 343143 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2925065 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4096 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17562 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1131401 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2852269 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3976 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17384 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1106708 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31964883 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 695794 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31919671 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 693087 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2254713 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24187633 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 367329 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63466208 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 114663 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12921007 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8155176 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 887376 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 69283 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3741 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17562 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 208254 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 160111 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 368365 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87428231 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43415449 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1725183 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2209905 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24121244 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 365124 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 62044608 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 111941 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12608499 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7947542 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 865588 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 68372 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3578 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17384 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 203207 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155936 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 359143 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86098386 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43091016 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1705534 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103983 # number of nop insts executed -system.cpu1.iew.exec_refs 50722611 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7090027 # Number of branches executed -system.cpu1.iew.exec_stores 7307162 # Number of stores executed -system.cpu1.iew.exec_rate 0.213729 # Inst execution rate -system.cpu1.iew.wb_sent 86641966 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54489882 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30361493 # num instructions producing a value -system.cpu1.iew.wb_consumers 54263873 # num instructions consuming a value +system.cpu1.iew.exec_nop 104789 # number of nop insts executed +system.cpu1.iew.exec_refs 50204478 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6908033 # Number of branches executed +system.cpu1.iew.exec_stores 7113462 # Number of stores executed +system.cpu1.iew.exec_rate 0.211620 # Inst execution rate +system.cpu1.iew.wb_sent 85323128 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53233499 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29734399 # num instructions producing a value +system.cpu1.iew.wb_consumers 53052149 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133207 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559516 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.130842 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560475 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13678793 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 920061 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 321962 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111532269 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.442230 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.412276 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13410332 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880845 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 313641 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 109924338 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.438116 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.408415 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94330377 84.58% 84.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8440609 7.57% 92.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2214130 1.99% 94.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1297536 1.16% 95.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1275593 1.14% 96.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 591609 0.53% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 995873 0.89% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 566603 0.51% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1819939 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 93165965 84.75% 84.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8233685 7.49% 92.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2134554 1.94% 94.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1255111 1.14% 95.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1238932 1.13% 96.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 576271 0.52% 96.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 972518 0.88% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 559108 0.51% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1788194 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111532269 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38948804 # Number of instructions committed -system.cpu1.commit.committedOps 49322865 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 109924338 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38068175 # Number of instructions committed +system.cpu1.commit.committedOps 48159625 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17019717 # Number of memory references committed -system.cpu1.commit.loads 9995942 # Number of loads committed -system.cpu1.commit.membars 202353 # Number of memory barriers committed -system.cpu1.commit.branches 6138218 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43713249 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556359 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1819939 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16597064 # Number of memory references committed +system.cpu1.commit.loads 9756230 # Number of loads committed +system.cpu1.commit.membars 190160 # Number of memory barriers committed +system.cpu1.commit.branches 5968166 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42694155 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534687 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1788194 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171599349 # The number of ROB reads -system.cpu1.rob.rob_writes 128350222 # The number of ROB writes -system.cpu1.timesIdled 1423694 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295273987 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796667155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38879165 # Number of Instructions Simulated -system.cpu1.committedOps 49253226 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38879165 # Number of Instructions Simulated -system.cpu1.cpi 10.521341 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.521341 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.095045 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.095045 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391632222 # number of integer regfile reads -system.cpu1.int_regfile_writes 56613239 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4857 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2306 # number of floating regfile writes -system.cpu1.misc_regfile_reads 19006571 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429961 # number of misc regfile writes -system.cpu1.icache.replacements 614526 # number of replacements -system.cpu1.icache.tagsinuse 498.795598 # Cycle average of tags in use -system.cpu1.icache.total_refs 7119619 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 615038 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 11.575901 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74541182500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.795598 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974210 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974210 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7119619 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7119619 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7119619 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7119619 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7119619 # number of overall hits -system.cpu1.icache.overall_hits::total 7119619 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 661683 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 661683 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 661683 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 661683 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 661683 # number of overall misses -system.cpu1.icache.overall_misses::total 661683 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8857903496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8857903496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8857903496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8857903496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8857903496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8857903496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7781302 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7781302 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7781302 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7781302 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7781302 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7781302 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085035 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.085035 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085035 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.085035 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085035 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.085035 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13386.929233 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13386.929233 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13386.929233 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13386.929233 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2804 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # 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Number of Instructions Simulated +system.cpu1.cpi 10.707108 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.707108 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093396 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093396 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 385381686 # number of integer regfile reads +system.cpu1.int_regfile_writes 55406618 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18496665 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405533 # number of misc regfile writes +system.cpu1.icache.replacements 597187 # number of replacements +system.cpu1.icache.tagsinuse 480.515152 # Cycle average of tags in use +system.cpu1.icache.total_refs 6939274 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 597699 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 11.609981 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74121232000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.515152 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938506 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938506 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6939274 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6939274 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6939274 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6939274 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6939274 # number of overall hits +system.cpu1.icache.overall_hits::total 6939274 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 642651 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 642651 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7581925 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7581925 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7581925 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7581925 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084761 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084761 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084761 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084761 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084761 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084761 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13398.076083 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13398.076083 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13398.076083 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13398.076083 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13398.076083 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13398.076083 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2076 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 753 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.069767 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 753 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2902500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2902500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079044 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.079044 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.079044 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11793.215345 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44927 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44927 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44927 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44927 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44927 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44927 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597724 # 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number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078835 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078835 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.078835 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11791.226375 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # 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miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.132671 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14995.710360 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14995.710360 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40964.872491 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40964.872491 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.448300 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.448300 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5367.158841 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5367.158841 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35655.251306 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 35655.251306 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35655.251306 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 35655.251306 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 28539 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 15177 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3269 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.730193 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 91.427711 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360661 # number of replacements +system.cpu1.dcache.tagsinuse 473.725553 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12688668 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 361027 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.146036 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70279173000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 473.725553 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.925245 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.925245 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8315910 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8315910 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4141838 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4141838 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97575 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97575 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94901 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94901 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12457748 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12457748 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12457748 # number of overall hits +system.cpu1.dcache.overall_hits::total 12457748 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 397655 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 397655 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1555408 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1555408 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13937 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10609 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10609 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1953063 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1953063 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1953063 # number of overall misses +system.cpu1.dcache.overall_misses::total 1953063 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5962620500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5962620500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 63820949998 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 63820949998 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128371500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 128371500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53750500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53750500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 69783570498 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 69783570498 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 69783570498 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 69783570498 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8713565 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8713565 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5697246 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5697246 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111512 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111512 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105510 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105510 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14410811 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14410811 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14410811 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14410811 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045636 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045636 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273011 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273011 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124982 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124982 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100550 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100550 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135528 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135528 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135528 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135528 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14994.456250 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14994.456250 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41031.645715 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41031.645715 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9210.841645 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9210.841645 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5066.500141 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5066.500141 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35730.322318 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35730.322318 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 26431 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 15171 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 158 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.193118 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 96.018987 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327455 # number of writebacks -system.cpu1.dcache.writebacks::total 327455 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170587 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 170587 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400204 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1400204 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1432 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1432 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570791 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1570791 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570791 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1570791 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231195 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231195 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163115 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163115 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10902 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10902 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394310 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394310 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394310 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394310 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2860496500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2860496500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5258978708 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5258978708 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89750500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89750500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36721500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36721500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8119475208 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8119475208 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8119475208 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8119475208 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298302500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298302500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27190030960 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27190030960 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196488333460 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196488333460 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025809 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025809 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027865 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027865 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107575 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107575 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097590 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097590 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026621 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026621 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12372.657281 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12372.657281 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32240.926389 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32240.926389 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7041.463989 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7041.463989 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3368.326912 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3368.326912 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324726 # number of writebacks +system.cpu1.dcache.writebacks::total 324726 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169327 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 169327 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393847 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1393847 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1563174 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1563174 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1563174 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1563174 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228328 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228328 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161561 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161561 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12488 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12488 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10607 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10607 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389889 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389889 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389889 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389889 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2825835000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2825835000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5223945209 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5223945209 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87441500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87441500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32536500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32536500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8049780209 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8049780209 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8049780209 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8049780209 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168995979000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168995979000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27123329043 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27123329043 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196119308043 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196119308043 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026204 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026204 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028358 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028358 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111988 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111988 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100531 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100531 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027055 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027055 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.208787 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12376.208787 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32334.197046 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32334.197046 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7002.041960 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7002.041960 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3067.455454 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3067.455454 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1821,18 +1817,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1162989936366 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1162989936366 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 497798121418 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 497798121418 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 497798121418 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 497798121418 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43794 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41715 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53929 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b454be827..e98399cb1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,114 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523518 # Number of seconds simulated -sim_ticks 2523517846500 # Number of ticks simulated -final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523205 # Number of seconds simulated +sim_ticks 2523204701000 # Number of ticks simulated +final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24932 # Simulator instruction rate (inst/s) -host_op_rate 32070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1038273503 # Simulator tick rate (ticks/s) -host_mem_usage 403456 # Number of bytes of host memory used -host_seconds 2430.49 # Real time elapsed on the host -sim_insts 60597240 # Number of instructions simulated -sim_ops 77945362 # Number of ops (including micro ops) simulated +host_inst_rate 64094 # Simulator instruction rate (inst/s) +host_op_rate 82471 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2681679652 # Simulator tick rate (ticks/s) +host_mem_usage 409992 # Number of bytes of host memory used +host_seconds 940.90 # Real time elapsed on the host +sim_insts 60306320 # Number of instructions simulated +sim_ops 77597310 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096842 # Total number of read requests seen -system.physmem.writeReqs 813129 # Total number of write requests seen -system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966197888 # Total number of bytes read from memory -system.physmem.bytesWritten 52040256 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096856 # Total number of read requests seen +system.physmem.writeReqs 813138 # Total number of write requests seen +system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966198784 # Total number of bytes read from memory +system.physmem.bytesWritten 52040832 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis +system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523516727500 # Total gap between requests +system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523203522000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154598 # Categorize read packet sizes +system.physmem.readPktSize::6 154612 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1937150 # categorize write packet sizes +system.physmem.writePktSize::2 1943854 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59111 # categorize write packet sizes +system.physmem.writePktSize::6 59120 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +129,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,72 +165,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests -system.physmem.totBusLat 60385948000 # Total cycles spent in databus access -system.physmem.totBankLat 16343502000 # Total cycles spent in bank access -system.physmem.avgQLat 21736.41 # Average queueing delay per request -system.physmem.avgBankLat 1082.60 # Average bank access latency per request +system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests +system.physmem.totBusLat 60386192000 # Total cycles spent in databus access +system.physmem.totBankLat 16356620000 # Total cycles spent in bank access +system.physmem.avgQLat 21743.10 # Average queueing delay per request +system.physmem.avgBankLat 1083.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26819.01 # Average memory access latency -system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26826.57 # Average memory access latency +system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 11.85 # Average write queue length over time -system.physmem.readRowHits 15052691 # Number of row buffer hits during reads -system.physmem.writeRowHits 784814 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.68 # Average write queue length over time +system.physmem.readRowHits 15052450 # Number of row buffer hits during reads +system.physmem.writeRowHits 784654 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes -system.physmem.avgGap 158612.28 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes +system.physmem.avgGap 158592.36 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51295505 # DTB read hits -system.cpu.dtb.read_misses 73548 # DTB read misses -system.cpu.dtb.write_hits 11769416 # DTB write hits -system.cpu.dtb.write_misses 17308 # DTB write misses +system.cpu.dtb.read_hits 51212683 # DTB read hits +system.cpu.dtb.read_misses 73387 # DTB read misses +system.cpu.dtb.write_hits 11701466 # DTB write hits +system.cpu.dtb.write_misses 17011 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4227 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51369053 # DTB read accesses -system.cpu.dtb.write_accesses 11786724 # DTB write accesses +system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51286070 # DTB read accesses +system.cpu.dtb.write_accesses 11718477 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63064921 # DTB hits -system.cpu.dtb.misses 90856 # DTB misses -system.cpu.dtb.accesses 63155777 # DTB accesses -system.cpu.itb.inst_hits 11599470 # ITB inst hits -system.cpu.itb.inst_misses 11387 # ITB inst misses +system.cpu.dtb.hits 62914149 # DTB hits +system.cpu.dtb.misses 90398 # DTB misses +system.cpu.dtb.accesses 63004547 # DTB accesses +system.cpu.itb.inst_hits 11530598 # ITB inst hits +system.cpu.itb.inst_misses 11503 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -256,122 +256,122 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2571 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2585 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11610857 # ITB inst accesses -system.cpu.itb.hits 11599470 # DTB hits -system.cpu.itb.misses 11387 # DTB misses -system.cpu.itb.accesses 11610857 # DTB accesses -system.cpu.numCycles 470965317 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11542101 # ITB inst accesses +system.cpu.itb.hits 11530598 # DTB hits +system.cpu.itb.misses 11503 # DTB misses +system.cpu.itb.accesses 11542101 # DTB accesses +system.cpu.numCycles 469830472 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits +system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -399,383 +399,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued -system.cpu.iq.rate 0.262043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued +system.cpu.iq.rate 0.261848 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221628 # number of nop insts executed -system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed -system.cpu.iew.exec_branches 11537560 # Number of branches executed -system.cpu.iew.exec_stores 12281337 # Number of stores executed -system.cpu.iew.exec_rate 0.257635 # Inst execution rate -system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47183541 # num instructions producing a value -system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value +system.cpu.iew.exec_nop 221038 # number of nop insts executed +system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed +system.cpu.iew.exec_branches 11477980 # Number of branches executed +system.cpu.iew.exec_stores 12213052 # Number of stores executed +system.cpu.iew.exec_rate 0.257448 # Inst execution rate +system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47051195 # num instructions producing a value +system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747621 # Number of instructions committed -system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456701 # Number of instructions committed +system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514551 # Number of memory references committed -system.cpu.commit.loads 15716032 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023101 # Number of branches committed +system.cpu.commit.refs 27385892 # Number of memory references committed +system.cpu.commit.loads 15654083 # Number of loads committed +system.cpu.commit.membars 403583 # Number of memory barriers committed +system.cpu.commit.branches 9961154 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134175 # Number of committed integer instructions. -system.cpu.commit.function_calls 995982 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68853054 # Number of committed integer instructions. +system.cpu.commit.function_calls 991222 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239713879 # The number of ROB reads -system.cpu.rob.rob_writes 197204165 # The number of ROB writes -system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597240 # Number of Instructions Simulated -system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated -system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 549724990 # number of integer regfile reads -system.cpu.int_regfile_writes 88045459 # number of integer regfile writes -system.cpu.fp_regfile_reads 8276 # number of floating regfile reads -system.cpu.fp_regfile_writes 2926 # number of floating regfile writes -system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads -system.cpu.misc_regfile_writes 912900 # number of misc regfile writes -system.cpu.icache.replacements 981280 # number of replacements -system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use -system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10533801 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10533801 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10533801 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10533801 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10533801 # number of overall hits -system.cpu.icache.overall_hits::total 10533801 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061888 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061888 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061888 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061888 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061888 # number of overall misses -system.cpu.icache.overall_misses::total 1061888 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13967491489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13967491489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13967491489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13967491489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13967491489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13967491489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11595689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11595689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11595689 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11595689 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11595689 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11595689 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091576 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5396 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1220 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.808581 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 610 # average number of cycles each access was blocked +system.cpu.rob.rob_reads 238273902 # The number of ROB reads +system.cpu.rob.rob_writes 196332947 # The number of ROB writes +system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60306320 # Number of Instructions Simulated +system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated +system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547824485 # number of integer regfile reads +system.cpu.int_regfile_writes 87698031 # number of integer regfile writes +system.cpu.fp_regfile_reads 8340 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads +system.cpu.misc_regfile_writes 831851 # number of misc regfile writes +system.cpu.icache.replacements 979772 # number of replacements +system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use +system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits +system.cpu.icache.overall_hits::total 10466836 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses +system.cpu.icache.overall_misses::total 1059904 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80057 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80057 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80057 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80057 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80057 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981831 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981831 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981831 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981831 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981831 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11353310491 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11353310491 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11353310491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11353310491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11353310491 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11353310491 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # 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average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185384465080 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185388810235 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026801 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015728 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986833 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986833 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40200.065916 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42272.284682 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41202.872052 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37724.699758 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37724.699758 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.165453 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.165453 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -896,161 +896,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643581 # number of replacements -system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use -system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks. +system.cpu.dcache.replacements 643386 # number of replacements +system.cpu.dcache.tagsinuse 511.994223 # Cycle average of tags in use +system.cpu.dcache.total_refs 21524162 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643898 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.427906 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.994223 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21105442 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21105442 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21105442 # number of overall hits -system.cpu.dcache.overall_hits::total 21105442 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 731834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 731834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2961255 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2961255 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13603 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13603 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3693089 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3693089 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3693089 # number of overall misses -system.cpu.dcache.overall_misses::total 3693089 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9564740000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9564740000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104026861731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104026861731 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180604500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180604500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 244000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 244000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113591601731 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113591601731 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113591601731 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113591601731 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 296044 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285756 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285756 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24798531 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24798531 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24798531 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24798531 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050305 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050305 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288884 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288884 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35129.315689 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35129.315689 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13276.813938 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13276.813938 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30757.883639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30757.883639 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32046 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.377752 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.697211 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13769851 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13769851 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7260574 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7260574 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243031 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243031 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21030425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21030425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21030425 # number of overall hits +system.cpu.dcache.overall_hits::total 21030425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731035 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731035 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2961528 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2961528 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13553 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13553 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692563 # number of overall misses +system.cpu.dcache.overall_misses::total 3692563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9558145500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9558145500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 103975545233 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 103975545233 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 229500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 229500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113533690733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113533690733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113533690733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113533690733 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14500886 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14500886 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222102 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222102 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256584 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256584 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247612 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247612 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24722988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24722988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24722988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24722988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050413 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050413 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289718 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052821 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052821 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks -system.cpu.dcache.writebacks::total 607832 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345983 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345983 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks +system.cpu.dcache.writebacks::total 607596 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1072,16 +1072,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 41aab5e9e..9c74b1b1d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,164 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401421 # Number of seconds simulated -sim_ticks 2401421439000 # Number of ticks simulated -final_tick 2401421439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401290 # Number of seconds simulated +sim_ticks 2401290348000 # Number of ticks simulated +final_tick 2401290348000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75201 # Simulator instruction rate (inst/s) -host_op_rate 96555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2986582566 # Simulator tick rate (ticks/s) -host_mem_usage 393856 # Number of bytes of host memory used -host_seconds 804.07 # Real time elapsed on the host -sim_insts 60466509 # Number of instructions simulated -sim_ops 77636591 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 196762 # Simulator instruction rate (inst/s) +host_op_rate 252717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7831753482 # Simulator tick rate (ticks/s) +host_mem_usage 401668 # Number of bytes of host memory used +host_seconds 306.61 # Real time elapsed on the host +sim_insts 60329082 # Number of instructions simulated +sim_ops 77485321 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 478816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7027600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 486624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7022480 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 73664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 716876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 218496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1332556 # Number of bytes read from this memory -system.physmem.bytes_read::total 124668680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 478816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 73664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 218496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 770976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3748032 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1052216 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199484 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1764144 # Number of bytes written to this memory -system.physmem.bytes_written::total 6763876 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 77504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 723200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 203648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1332732 # Number of bytes read from this memory +system.physmem.bytes_read::total 124666476 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 486624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 77504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 203648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 767776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3747584 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1052224 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1764136 # Number of bytes written to this memory +system.physmem.bytes_written::total 6763400 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13684 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 109840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13806 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 109760 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1151 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20824 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512526 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58563 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 263054 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49871 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 441036 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812524 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47812962 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11300 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3182 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20838 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512500 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58556 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 263056 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 441034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812510 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47815572 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2926433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 202651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2924461 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 30675 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 298522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 90986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 554903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51914536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 30675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 90986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 321050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 438164 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83069 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 734625 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2816613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47812962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 301171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 84808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 555007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51916452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 202651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 84808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560654 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 438191 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 734662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2816569 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47815572 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3364597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 202651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3362652 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 30675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 381591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 90986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1289528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54731150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12619527 # Total number of read requests seen -system.physmem.writeReqs 508095 # Total number of write requests seen -system.physmem.cpureqs 56153 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807649728 # Total number of bytes read from memory -system.physmem.bytesWritten 32518080 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 103006296 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 3063660 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2356 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 788374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788516 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 788282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 788267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788268 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788411 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 789077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 789904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 789864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 789609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 789636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788160 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 30462 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 31339 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 31367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 31519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 31434 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 31463 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 31715 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 32144 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 32667 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 32642 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 32415 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 32370 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 31797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 31479 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 31921 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 31361 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 32276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 384233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 84808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1289668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54733021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12619459 # Total number of read requests seen +system.physmem.writeReqs 508288 # Total number of write requests seen +system.physmem.cpureqs 56279 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807645376 # Total number of bytes read from memory +system.physmem.bytesWritten 32530432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 103001404 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 3076552 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 788367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788340 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 788430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 788204 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 789073 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 789810 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 789739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 789543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 789483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788174 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788123 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 30454 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 30491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 30890 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 31526 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 31443 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 31484 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 31752 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 32161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 32686 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 32676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 32416 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 32334 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 31816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 31518 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 32440 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 32201 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 317403 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400386249000 # Total gap between requests +system.physmem.numWrRetry 316906 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400255112000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6 # Categorize read packet sizes +system.physmem.readPktSize::2 15 # Categorize read packet sizes system.physmem.readPktSize::3 12582912 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 36609 # Categorize read packet sizes +system.physmem.readPktSize::6 36532 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 808310 # categorize write packet sizes +system.physmem.writePktSize::2 807804 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 17188 # categorize write packet sizes +system.physmem.writePktSize::6 17390 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -167,26 +151,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 2356 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2357 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 817282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 787018 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 816081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2309777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2310026 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4565188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 24594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 24587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 47867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 24582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 47847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 817349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 786840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 815906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2309875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2310166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4565473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 24603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 24600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 47884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 47866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1286 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -203,341 +187,343 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 22096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 22090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 22088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 22084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 22079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 22076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 22064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 22061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 22055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 22051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 22047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 22044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 22104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 22101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 22095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 22093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 22091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 22082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 22071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 22068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 22063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 22058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 22054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 22052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17662 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 234691241923 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 297448055923 # Sum of mem lat for all requests -system.physmem.totBusLat 50478100000 # Total cycles spent in databus access -system.physmem.totBankLat 12278714000 # Total cycles spent in bank access -system.physmem.avgQLat 18597.47 # Average queueing delay per request -system.physmem.avgBankLat 972.99 # Average bank access latency per request +system.physmem.totQLat 234677385926 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 297433333926 # Sum of mem lat for all requests +system.physmem.totBusLat 50477836000 # Total cycles spent in databus access +system.physmem.totBankLat 12278112000 # Total cycles spent in bank access +system.physmem.avgQLat 18596.47 # Average queueing delay per request +system.physmem.avgBankLat 972.95 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23570.46 # Average memory access latency -system.physmem.avgRdBW 336.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 13.54 # Average achieved write bandwidth in MB/s +system.physmem.avgMemAccLat 23569.42 # Average memory access latency +system.physmem.avgRdBW 336.34 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 13.55 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 42.89 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.28 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.19 # Data bus utilization in percentage system.physmem.avgRdQLen 0.12 # Average read queue length over time -system.physmem.avgWrQLen 0.40 # Average write queue length over time -system.physmem.readRowHits 12589945 # Number of row buffer hits during reads -system.physmem.writeRowHits 499132 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.019761 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006589 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991886 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986014 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.502725 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347876 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365463 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.116332 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.130072 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 651827364 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 7180784034 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 7832611398 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25927282364 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 33760967560 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59688249924 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009546 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020335 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000470 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010911 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.019796 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006145 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992063 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.982915 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.502892 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.354429 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366743 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.118416 # 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average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10118.519427 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10039.934282 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 31789.320755 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41472.149695 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38132.557628 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39434.677126 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42803.544782 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56635.200000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 45576.352923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 45588.650850 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44275.964562 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.938000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10009.178937 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10041.573748 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 31515.049734 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41152.282713 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37741.003999 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56635.200000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45576.352923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41675.876843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39165.597102 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 32857.540661 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41896.169910 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39347.363093 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39434.677126 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 32702.234186 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56635.200000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45576.352923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41675.876843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39165.597102 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency @@ -712,26 +686,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7902224 # DTB read hits -system.cpu0.dtb.read_misses 6242 # DTB read misses -system.cpu0.dtb.write_hits 6537817 # DTB write hits -system.cpu0.dtb.write_misses 1923 # DTB write misses +system.cpu0.dtb.read_hits 7853690 # DTB read hits +system.cpu0.dtb.read_misses 6243 # DTB read misses +system.cpu0.dtb.write_hits 6487171 # DTB write hits +system.cpu0.dtb.write_misses 1921 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5670 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7908466 # DTB read accesses -system.cpu0.dtb.write_accesses 6539740 # DTB write accesses +system.cpu0.dtb.read_accesses 7859933 # DTB read accesses +system.cpu0.dtb.write_accesses 6489092 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14440041 # DTB hits -system.cpu0.dtb.misses 8165 # DTB misses -system.cpu0.dtb.accesses 14448206 # DTB accesses -system.cpu0.itb.inst_hits 31853127 # ITB inst hits +system.cpu0.dtb.hits 14340861 # DTB hits +system.cpu0.dtb.misses 8164 # DTB misses +system.cpu0.dtb.accesses 14349025 # DTB accesses +system.cpu0.itb.inst_hits 31512097 # ITB inst hits system.cpu0.itb.inst_misses 3518 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -748,440 +722,432 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 31856645 # ITB inst accesses -system.cpu0.itb.hits 31853127 # DTB hits +system.cpu0.itb.inst_accesses 31515615 # ITB inst accesses +system.cpu0.itb.hits 31512097 # DTB hits system.cpu0.itb.misses 3518 # DTB misses -system.cpu0.itb.accesses 31856645 # DTB accesses -system.cpu0.numCycles 112931028 # number of cpu cycles simulated +system.cpu0.itb.accesses 31515615 # DTB accesses +system.cpu0.numCycles 112564012 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31362077 # Number of instructions committed -system.cpu0.committedOps 41448320 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 36567470 # Number of integer alu accesses +system.cpu0.committedInsts 31022111 # Number of instructions committed +system.cpu0.committedOps 41078367 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 36251649 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5105 # Number of float alu accesses -system.cpu0.num_func_calls 1216492 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4268853 # number of instructions that are conditional controls -system.cpu0.num_int_insts 36567470 # number of integer instructions +system.cpu0.num_func_calls 1198861 # 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Number of store instructions -system.cpu0.num_idle_cycles 13401980962.617596 # Number of idle cycles -system.cpu0.num_busy_cycles -13289049934.617596 # Number of busy cycles -system.cpu0.not_idle_fraction -117.674037 # Percentage of non-idle cycles -system.cpu0.idle_fraction 118.674037 # Percentage of idle cycles +system.cpu0.num_mem_refs 15003639 # number of memory refs +system.cpu0.num_load_insts 8220534 # Number of load instructions +system.cpu0.num_store_insts 6783105 # Number of store instructions +system.cpu0.num_idle_cycles 13359160341.338484 # Number of idle cycles +system.cpu0.num_busy_cycles -13246596329.338484 # Number of busy cycles +system.cpu0.not_idle_fraction -117.680563 # Percentage of non-idle cycles +system.cpu0.idle_fraction 118.680563 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 84468 # number of quiesce instructions executed -system.cpu0.icache.replacements 892780 # number of replacements -system.cpu0.icache.tagsinuse 511.591234 # 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mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009527 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014911 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.073595 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009527 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11425.111293 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11781.272853 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11673.274939 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11425.111293 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11781.272853 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11673.274939 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11425.111293 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11781.272853 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11673.274939 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 629952 # number of replacements +system.cpu0.dcache.replacements 630017 # number of replacements system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23322161 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630464 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.992058 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 23260459 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630529 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.890387 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 497.280136 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 8.191597 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.525382 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.971250 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.015999 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012745 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 497.365080 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 8.139667 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.492369 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.971416 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.015898 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012680 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6763167 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1877822 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4718068 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13359057 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5963557 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1365617 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2102817 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9431991 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135570 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1394600 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2698693 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225310 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142092 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34426 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 95117 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 271635 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142092 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34425 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 91930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 268447 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13080616 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3330508 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7690674 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24101798 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13080616 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3330508 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7690674 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24101798 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026686 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030005 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.054871 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037288 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027472 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020782 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220802 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.077584 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045900 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047319 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.040056 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.044033 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000065 # 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average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9085.026796 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25053.514129 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32109.123237 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25033.034527 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.992020 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13445.144357 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6066.466015 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17810.179283 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26453.935285 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18737.407147 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17810.179283 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26453.935285 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18737.407147 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6963 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 952 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 771 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.031128 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20.695652 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1452391492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2141129992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 17815500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39577500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57393000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 101000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 101000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1388136000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3056742492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4444878492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1388136000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3056742492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4444878492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27612956500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29018137000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56631093500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1285303000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 12932223922 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14217526922 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28898259500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41950360922 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70848620422 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030320 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.024756 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013186 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021350 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019173 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008048 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046539 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043610 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020014 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026551 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.022786 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011005 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026551 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.022786 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011005 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12008.885646 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12899.097100 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12615.191904 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23174.242934 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27664.072913 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26041.157271 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11079.291045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11643.865843 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11462.552427 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14428.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14428.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15781.446112 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17281.643234 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16783.386417 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15781.446112 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17281.643234 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16783.386417 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2149941 # DTB read hits -system.cpu1.dtb.read_misses 2094 # DTB read misses -system.cpu1.dtb.write_hits 1479770 # DTB write hits +system.cpu1.dtb.read_hits 2135190 # DTB read hits +system.cpu1.dtb.read_misses 2107 # DTB read misses +system.cpu1.dtb.write_hits 1477401 # DTB write hits system.cpu1.dtb.write_misses 382 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1681 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1694 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 46 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2152035 # DTB read accesses -system.cpu1.dtb.write_accesses 1480152 # DTB write accesses +system.cpu1.dtb.read_accesses 2137297 # DTB read accesses +system.cpu1.dtb.write_accesses 1477783 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3629711 # DTB hits -system.cpu1.dtb.misses 2476 # DTB misses -system.cpu1.dtb.accesses 3632187 # DTB accesses -system.cpu1.itb.inst_hits 8564825 # ITB inst hits +system.cpu1.dtb.hits 3612591 # DTB hits +system.cpu1.dtb.misses 2489 # DTB misses +system.cpu1.dtb.accesses 3615080 # DTB accesses +system.cpu1.itb.inst_hits 8526904 # ITB inst hits system.cpu1.itb.inst_misses 1128 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1198,57 +1164,57 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8565953 # ITB inst accesses -system.cpu1.itb.hits 8564825 # DTB hits +system.cpu1.itb.inst_accesses 8528032 # ITB inst accesses +system.cpu1.itb.hits 8526904 # DTB hits system.cpu1.itb.misses 1128 # DTB misses -system.cpu1.itb.accesses 8565953 # DTB accesses -system.cpu1.numCycles 573618226 # number of cpu cycles simulated +system.cpu1.itb.accesses 8528032 # DTB accesses +system.cpu1.numCycles 573624739 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8360582 # Number of instructions committed -system.cpu1.committedOps 10552123 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9474069 # Number of integer alu accesses +system.cpu1.committedInsts 8322298 # Number of instructions committed +system.cpu1.committedOps 10507258 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9429869 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses -system.cpu1.num_func_calls 304948 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1122653 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9474069 # number of integer instructions +system.cpu1.num_func_calls 301953 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1117858 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9429869 # number of integer instructions system.cpu1.num_fp_insts 2062 # number of float instructions -system.cpu1.num_int_register_reads 54388368 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10296894 # number of times the integer registers were written +system.cpu1.num_int_register_reads 54131389 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10251114 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3801129 # number of memory refs -system.cpu1.num_load_insts 2242444 # Number of load instructions -system.cpu1.num_store_insts 1558685 # Number of store instructions -system.cpu1.num_idle_cycles -28470862.464355 # Number of idle cycles -system.cpu1.num_busy_cycles 602089088.464355 # Number of busy cycles -system.cpu1.not_idle_fraction 1.049634 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.049634 # Percentage of idle cycles +system.cpu1.num_mem_refs 3780360 # number of memory refs +system.cpu1.num_load_insts 2226594 # Number of load instructions +system.cpu1.num_store_insts 1553766 # Number of store instructions +system.cpu1.num_idle_cycles -28509606.904042 # Number of idle cycles +system.cpu1.num_busy_cycles 602134345.904042 # Number of busy cycles +system.cpu1.not_idle_fraction 1.049701 # Percentage of non-idle cycles +system.cpu1.idle_fraction -0.049701 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 11072336 # DTB read hits -system.cpu2.dtb.read_misses 27162 # DTB read misses -system.cpu2.dtb.write_hits 3379244 # DTB write hits -system.cpu2.dtb.write_misses 7485 # DTB write misses +system.cpu2.dtb.read_hits 11094758 # DTB read hits +system.cpu2.dtb.read_misses 26972 # DTB read misses +system.cpu2.dtb.write_hits 3400244 # DTB write hits +system.cpu2.dtb.write_misses 7099 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 3059 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 210 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 3080 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 792 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 201 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 417 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 11099498 # DTB read accesses -system.cpu2.dtb.write_accesses 3386729 # DTB write accesses +system.cpu2.dtb.perms_faults 424 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 11121730 # DTB read accesses +system.cpu2.dtb.write_accesses 3407343 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14451580 # DTB hits -system.cpu2.dtb.misses 34647 # DTB misses -system.cpu2.dtb.accesses 14486227 # DTB accesses -system.cpu2.itb.inst_hits 3940913 # ITB inst hits -system.cpu2.itb.inst_misses 4663 # ITB inst misses +system.cpu2.dtb.hits 14495002 # DTB hits +system.cpu2.dtb.misses 34071 # DTB misses +system.cpu2.dtb.accesses 14529073 # DTB accesses +system.cpu2.itb.inst_hits 3971406 # ITB inst hits +system.cpu2.itb.inst_misses 4850 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1257,292 +1223,292 @@ system.cpu2.itb.flush_tlb 276 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1673 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1791 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1033 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 3945576 # ITB inst accesses -system.cpu2.itb.hits 3940913 # DTB hits -system.cpu2.itb.misses 4663 # DTB misses -system.cpu2.itb.accesses 3945576 # DTB accesses -system.cpu2.numCycles 88228970 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 3976256 # ITB inst accesses +system.cpu2.itb.hits 3971406 # DTB hits +system.cpu2.itb.misses 4850 # DTB misses +system.cpu2.itb.accesses 3976256 # DTB accesses +system.cpu2.numCycles 88220053 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 4678533 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 3809806 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 231267 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 3069092 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 2498136 # Number of BTB hits +system.cpu2.BPredUnit.lookups 4714679 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 3830081 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 228509 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 3129435 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 2502665 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 412114 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 22380 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 9360105 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 31976282 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4678533 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2910250 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6786917 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1728503 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 53808 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19342330 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 913 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 36859 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 59251 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 389 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3939412 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 244088 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2174 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36830548 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.047719 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.434253 # Number of instructions fetched each cycle (Total) +system.cpu2.BPredUnit.usedRAS 416919 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 22256 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 9444272 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32171210 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4714679 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2919584 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6810047 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1714054 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 54378 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19370743 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 384 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 766 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 36586 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 56559 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 314 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3969766 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 243007 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2358 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36954315 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.048838 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.435241 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30048718 81.59% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 408687 1.11% 82.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 492187 1.34% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 812698 2.21% 86.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 611463 1.66% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 330922 0.90% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1062958 2.89% 91.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 224607 0.61% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2838308 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30149445 81.59% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 388045 1.05% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 515673 1.40% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 809442 2.19% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 613859 1.66% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 342479 0.93% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1057115 2.86% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 225211 0.61% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2853046 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36830548 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053027 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.362424 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9885763 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19327017 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6180149 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 300885 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1135792 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 597498 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 54848 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36565818 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 186819 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1135792 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10385247 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6621320 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11277395 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5962558 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1447335 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34838937 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2719 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 250879 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 912957 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 22201 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37227895 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159446068 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 159418988 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27080 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26794485 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10433409 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 254044 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 230219 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3142941 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6628278 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3915406 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 518992 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 767543 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32164019 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 534132 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 35030885 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 59969 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6868407 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 17749072 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 150741 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36830548 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.951137 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.612264 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36954315 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053442 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.364670 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9982984 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19336478 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6240183 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 267118 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1126648 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608561 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 54769 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36760882 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 185685 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1126648 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10483708 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6549966 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11350548 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5986699 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1455863 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35043442 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2820 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 275900 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 915207 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 16681 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37480121 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 160397903 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 160370485 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27418 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 27101892 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10378228 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 234776 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 210973 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3167835 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6643625 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3930476 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 536055 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 848060 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32398169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511180 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 35261741 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 57711 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6815727 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 17611211 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 150093 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36954315 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.954198 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.610437 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24216483 65.75% 65.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3835065 10.41% 76.16% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2287291 6.21% 82.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1980355 5.38% 87.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2800040 7.60% 95.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1007857 2.74% 98.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 517219 1.40% 99.49% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 152490 0.41% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 33748 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24234818 65.58% 65.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3845219 10.41% 75.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2339985 6.33% 82.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2011458 5.44% 87.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2820235 7.63% 95.39% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1010729 2.74% 98.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 509292 1.38% 99.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 148791 0.40% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 33788 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36830548 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36954315 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 17662 1.14% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1415792 91.50% 92.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 113850 7.36% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16803 1.09% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1412351 91.83% 92.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 108917 7.08% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 60995 0.17% 0.17% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19871242 56.72% 56.90% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 29695 0.08% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11515486 32.87% 89.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3553080 10.14% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 60938 0.17% 0.17% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 20064817 56.90% 57.08% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28831 0.08% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 373 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.16% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11537749 32.72% 89.88% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3569015 10.12% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 35030885 # Type of FU issued -system.cpu2.iq.rate 0.397045 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1547304 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044170 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108527324 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39572230 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28399462 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6790 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3711 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36513628 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3566 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 191014 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 35261741 # Type of FU issued +system.cpu2.iq.rate 0.399702 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1538071 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043619 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 109100819 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39730950 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28646602 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6706 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3736 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3123 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36735375 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3499 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 200241 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1467031 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2011 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9738 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 545094 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1445664 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1895 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9919 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 541092 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5365251 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 332989 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5363616 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 332725 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1135792 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4899150 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 89921 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32779082 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 64376 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6628278 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3915406 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 386018 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31359 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9738 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 111294 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 92702 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 203996 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 34250844 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11286425 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 780041 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1126648 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4836519 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 87210 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32990358 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 63317 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6643625 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3930476 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 365793 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29718 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2499 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9919 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 109460 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 91793 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 201253 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 34488012 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11310897 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 773729 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 80931 # number of nop insts executed -system.cpu2.iew.exec_refs 14805022 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3673391 # Number of branches executed -system.cpu2.iew.exec_stores 3518597 # Number of stores executed -system.cpu2.iew.exec_rate 0.388204 # Inst execution rate -system.cpu2.iew.wb_sent 33866957 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28402589 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16335424 # num instructions producing a value -system.cpu2.iew.wb_consumers 29431571 # num instructions consuming a value +system.cpu2.iew.exec_nop 81009 # number of nop insts executed +system.cpu2.iew.exec_refs 14846360 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3721674 # Number of branches executed +system.cpu2.iew.exec_stores 3535463 # Number of stores executed +system.cpu2.iew.exec_rate 0.390932 # Inst execution rate +system.cpu2.iew.wb_sent 34107524 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28649725 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16504855 # num instructions producing a value +system.cpu2.iew.wb_consumers 29777909 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.321919 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.555031 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.324753 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.554265 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 6831747 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 383391 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177223 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35694573 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.719725 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.780912 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 6780603 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 361087 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 174485 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35827443 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.724416 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.779563 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 26969912 75.56% 75.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4228252 11.85% 87.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1198360 3.36% 90.76% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 616402 1.73% 92.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 527161 1.48% 93.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 311066 0.87% 94.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 434912 1.22% 96.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 325428 0.91% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1083080 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 26972703 75.29% 75.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4272213 11.92% 87.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1247843 3.48% 90.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 631329 1.76% 92.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 544091 1.52% 93.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 320362 0.89% 94.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 435465 1.22% 96.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 326356 0.91% 96.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1077081 3.01% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35694573 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20797962 # Number of instructions committed -system.cpu2.commit.committedOps 25690260 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35827443 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 21038967 # Number of instructions committed +system.cpu2.commit.committedOps 25953990 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8531559 # Number of memory references committed -system.cpu2.commit.loads 5161247 # Number of loads committed -system.cpu2.commit.membars 98356 # Number of memory barriers committed -system.cpu2.commit.branches 3158165 # Number of branches committed +system.cpu2.commit.refs 8587345 # Number of memory references committed +system.cpu2.commit.loads 5197961 # Number of loads committed +system.cpu2.commit.membars 96306 # Number of memory barriers committed +system.cpu2.commit.branches 3207336 # Number of branches committed system.cpu2.commit.fp_insts 3087 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22900752 # Number of committed integer instructions. -system.cpu2.commit.function_calls 287889 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1083080 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 23136134 # Number of committed integer instructions. +system.cpu2.commit.function_calls 296648 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1077081 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66589270 # The number of ROB reads -system.cpu2.rob.rob_writes 66235051 # The number of ROB writes -system.cpu2.timesIdled 359715 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51398422 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3569788363 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20743850 # Number of Instructions Simulated -system.cpu2.committedOps 25636148 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20743850 # Number of Instructions Simulated -system.cpu2.cpi 4.253259 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.253259 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.235114 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.235114 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 159046643 # number of integer regfile reads -system.cpu2.int_regfile_writes 30194860 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22317 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20822 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9419199 # number of misc regfile reads -system.cpu2.misc_regfile_writes 278833 # number of misc regfile writes +system.cpu2.rob.rob_reads 66956650 # The number of ROB reads +system.cpu2.rob.rob_writes 66650908 # The number of ROB writes +system.cpu2.timesIdled 359376 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51265738 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3569532047 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20984673 # Number of Instructions Simulated +system.cpu2.committedOps 25899696 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20984673 # Number of Instructions Simulated +system.cpu2.cpi 4.204023 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.204023 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.237867 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.237867 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 160070437 # number of integer regfile reads +system.cpu2.int_regfile_writes 30477342 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22294 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20824 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9434068 # number of misc regfile reads +system.cpu2.misc_regfile_writes 244358 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1557,10 +1523,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925539770424 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 925539770424 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925539770424 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 925539770424 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925532055074 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 925532055074 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925532055074 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 925532055074 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 317771e8c..f50d6a5db 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,143 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.540587 # Number of seconds simulated -sim_ticks 2540587123500 # Number of ticks simulated -final_tick 2540587123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.540276 # Number of seconds simulated +sim_ticks 2540275734000 # Number of ticks simulated +final_tick 2540275734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 28859 # Simulator instruction rate (inst/s) -host_op_rate 37121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1209803028 # Simulator tick rate (ticks/s) -host_mem_usage 406188 # Number of bytes of host memory used -host_seconds 2100.00 # Real time elapsed on the host -sim_insts 60603607 # Number of instructions simulated -sim_ops 77954043 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 63914 # Simulator instruction rate (inst/s) +host_op_rate 82240 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2691970222 # Simulator tick rate (ticks/s) +host_mem_usage 413060 # Number of bytes of host memory used +host_seconds 943.65 # Real time elapsed on the host +sim_insts 60312498 # Number of instructions simulated +sim_ops 77605759 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 521152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4740560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 279808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4349656 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 521152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 279808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1619508 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1396592 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799204 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 405568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3860688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 395008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5229152 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 405568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 395008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783168 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1412956 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1603284 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799408 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 8143 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67969 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293448 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 404877 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 349148 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47670291 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 806 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 60357 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81713 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293445 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59112 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 353239 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 400821 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813172 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47676135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 605 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 205131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1865931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 110135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1712067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51564638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 110135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 637454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 549712 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676233 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47670291 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 159655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1519791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 155498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2058498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51570836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 159655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 155498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 556222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 631146 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47676135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 605 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2503385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 110135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2261780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54240872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293448 # Total number of read requests seen -system.physmem.writeReqs 813136 # Total number of write requests seen -system.physmem.cpureqs 218391 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978780672 # Total number of bytes read from memory -system.physmem.bytesWritten 52040704 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131004456 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799204 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955717 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955757 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955544 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955992 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 159655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2076012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 155498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2689643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54247478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293445 # Total number of read requests seen +system.physmem.writeReqs 813172 # Total number of write requests seen +system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978780480 # Total number of bytes read from memory +system.physmem.bytesWritten 52043008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131004144 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799408 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955910 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956214 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955656 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955538 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955410 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955590 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955922 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955987 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 955944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955714 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50106 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50364 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49972 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50676 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51298 # Track writes on a per bank basis +system.physmem.perBankRdReqs::12 956042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955918 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955719 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50035 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50823 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51116 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51361 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51295 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51031 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 677160 # Number of times wr buffer was full causing retry -system.physmem.totGap 2540585876000 # Total gap between requests +system.physmem.numWrRetry 693675 # Number of times wr buffer was full causing retry +system.physmem.totGap 2540274436500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 42 # Categorize read packet sizes +system.physmem.readPktSize::2 44 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154590 # Categorize read packet sizes +system.physmem.readPktSize::6 154585 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1431185 # categorize write packet sizes +system.physmem.writePktSize::2 1447735 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59111 # categorize write packet sizes +system.physmem.writePktSize::6 59112 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -146,31 +138,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1056941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 992282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 949580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 983982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2774748 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2777750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5475537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 36612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 31653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 59391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1057043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 992576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 949780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 984222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2774561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2777593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5475568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 36103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 57717 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 31668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 59387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -182,283 +174,311 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 31866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 31776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 31654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 31445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 31156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 30761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 30573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 30334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 31872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 31784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 31663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 31466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 31190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 30972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 30814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 30644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 30396 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 295225090687 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 372543516687 # Sum of mem lat for all requests -system.physmem.totBusLat 61173752000 # Total cycles spent in databus access -system.physmem.totBankLat 16144674000 # Total cycles spent in bank access -system.physmem.avgQLat 19304.04 # Average queueing delay per request -system.physmem.avgBankLat 1055.66 # Average bank access latency per request +system.physmem.totQLat 295222941913 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 372544627913 # Sum of mem lat for all requests +system.physmem.totBusLat 61173736000 # Total cycles spent in databus access +system.physmem.totBankLat 16147950000 # Total cycles spent in bank access +system.physmem.avgQLat 19303.90 # Average queueing delay per request +system.physmem.avgBankLat 1055.87 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24359.70 # Average memory access latency -system.physmem.avgRdBW 385.26 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.56 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 24359.78 # Average memory access latency +system.physmem.avgRdBW 385.30 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.49 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.57 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.54 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.12 # Average write queue length over time -system.physmem.readRowHits 15250784 # Number of row buffer hits during reads -system.physmem.writeRowHits 786076 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.11 # Average write queue length over time +system.physmem.readRowHits 15250779 # Number of row buffer hits during reads +system.physmem.writeRowHits 786181 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.67 # Row buffer hit rate for writes -system.physmem.avgGap 157735.86 # Average gap between requests -system.l2c.replacements 64360 # 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Sample count of references to valid blocks. +system.l2c.avg_refs 14.937369 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2504164034000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36931.020579 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 16.606352 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000348 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5181.760660 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3292.636698 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 8.768373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3037.851423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2944.578476 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563314 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000315 # 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mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.142857 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.076923 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.547060 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534591 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.540966 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000266 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015745 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.224784 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000195 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009181 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.221522 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.089652 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000266 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015745 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.224784 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000195 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009181 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.221522 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.089652 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750 # average ReadReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.495879 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578133 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540961 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.198791 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245611 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.089778 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.198791 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245611 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.089778 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39677.406231 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40528.689834 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40784.784538 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43264.007618 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40841.191511 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.750320 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.745156 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.649449 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41387.654116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42592.949196 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40941.666580 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10046.393474 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.465517 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42548.857363 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.012734 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38297.457621 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 38080.687217 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 38237.204887 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38172.367057 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39677.406231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42382.295842 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40784.784538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34363.643791 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 38673.343601 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58298.718750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39677.406231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42382.295842 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40784.784538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34363.643791 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 38673.343601 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -651,677 +687,677 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26104138 # DTB read hits -system.cpu0.dtb.read_misses 45655 # DTB read misses -system.cpu0.dtb.write_hits 6173225 # DTB write hits -system.cpu0.dtb.write_misses 11582 # DTB write misses -system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25321176 # DTB read hits +system.cpu0.dtb.read_misses 39544 # DTB read misses +system.cpu0.dtb.write_hits 5538222 # DTB write hits +system.cpu0.dtb.write_misses 9025 # DTB write misses +system.cpu0.dtb.flush_tlb 256 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 737 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 8687 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1569 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 7899 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1433 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 666 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26149793 # DTB read accesses -system.cpu0.dtb.write_accesses 6184807 # DTB write accesses +system.cpu0.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25360720 # DTB read accesses +system.cpu0.dtb.write_accesses 5547247 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32277363 # DTB hits -system.cpu0.dtb.misses 57237 # DTB misses -system.cpu0.dtb.accesses 32334600 # DTB accesses -system.cpu0.itb.inst_hits 6054056 # ITB inst hits -system.cpu0.itb.inst_misses 7505 # ITB inst misses +system.cpu0.dtb.hits 30859398 # DTB hits +system.cpu0.dtb.misses 48569 # DTB misses +system.cpu0.dtb.accesses 30907967 # DTB accesses +system.cpu0.itb.inst_hits 5399990 # ITB inst hits +system.cpu0.itb.inst_misses 6797 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 256 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 737 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2789 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2645 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1640 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1504 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6061561 # ITB inst accesses -system.cpu0.itb.hits 6054056 # DTB hits -system.cpu0.itb.misses 7505 # DTB misses -system.cpu0.itb.accesses 6061561 # DTB accesses -system.cpu0.numCycles 240389950 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5406787 # ITB inst accesses +system.cpu0.itb.hits 5399990 # DTB hits +system.cpu0.itb.misses 6797 # DTB misses +system.cpu0.itb.accesses 5406787 # DTB accesses +system.cpu0.numCycles 232916834 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 7650447 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 6071769 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 390619 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 4963412 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 4056247 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6894641 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 5490275 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 340467 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 4496048 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3641169 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 744385 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 39840 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 15652124 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47554546 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7650447 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4800632 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10611377 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2494725 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 89565 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50696365 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1967 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 55574 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 106827 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6051824 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 344537 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3471 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 78943853 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.750152 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.105781 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 672237 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 35025 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 14144008 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 42774388 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6894641 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4313406 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 9542116 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2097502 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 81571 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47928082 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 983 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1918 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 48764 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90424 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5397887 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 280481 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3116 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 73293713 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.724548 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.073228 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 68340077 86.57% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 702129 0.89% 87.46% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 881040 1.12% 88.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1224383 1.55% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1120463 1.42% 91.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 584523 0.74% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1319074 1.67% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 413717 0.52% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4358447 5.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63759289 86.99% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 642563 0.88% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816896 1.11% 88.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1076628 1.47% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1030388 1.41% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 525946 0.72% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1160801 1.58% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 367124 0.50% 94.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3914078 5.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 78943853 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031825 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.197823 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16656979 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 50446432 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9625401 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 575149 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1637749 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1050019 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 92865 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56438894 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 312308 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1637749 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17559275 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19379590 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27710296 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9215944 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3438937 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54038405 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 14132 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 614041 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2240889 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 19821 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55994087 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 246350981 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 246302367 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48614 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 41407239 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14586848 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 463494 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 411765 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6993142 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10396030 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7010506 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1100529 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1298753 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50240617 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1080191 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63997387 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 98424 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10068381 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24718063 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 263130 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 78943853 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.810670 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.516651 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 73293713 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029601 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.183647 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15070134 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 47635747 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8687716 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 522868 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1375117 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 927671 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 82962 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 50805033 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 279607 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1375117 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 15858431 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18747322 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 25731690 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8353206 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3225899 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 48905504 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13838 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 630791 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2093496 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 12811 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 50688794 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 222549147 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 222507399 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 41748 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38461100 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12227693 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 386484 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 344770 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6389877 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9452191 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6279292 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 988040 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1320602 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 45692134 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 977389 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 60037368 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 85152 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8499333 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 20279389 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 254746 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 73293713 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.819134 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.521823 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55721215 70.58% 70.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7438559 9.42% 80.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3764189 4.77% 84.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3138828 3.98% 88.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6266578 7.94% 96.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1507037 1.91% 98.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 806867 1.02% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 233373 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 67207 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 51609317 70.41% 70.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6835660 9.33% 79.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3457344 4.72% 84.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2997093 4.09% 88.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6031042 8.23% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1346418 1.84% 98.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 738853 1.01% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 217523 0.30% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 60463 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 78943853 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 73293713 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 28850 0.65% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 4 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4202057 94.56% 95.21% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 212765 4.79% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26194 0.60% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4172771 94.90% 95.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 196420 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30502224 47.66% 47.97% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 49600 0.08% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1274 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26758229 41.81% 89.86% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6489612 10.14% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 194561 0.32% 0.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28037950 46.70% 47.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 44753 0.07% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 838 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 25907736 43.15% 90.25% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5851514 9.75% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63997387 # Type of FU issued -system.cpu0.iq.rate 0.266223 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4443676 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.069435 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 211525282 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61397992 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 45248586 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12498 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6745 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5570 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 68238014 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6629 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 331719 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 60037368 # Type of FU issued +system.cpu0.iq.rate 0.257763 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4397050 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073239 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 197888427 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 55177485 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 41654501 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10625 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5737 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4733 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 64234192 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5665 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 298497 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2183838 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4014 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16143 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 861796 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1811405 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3010 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 725021 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17073193 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 345280 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17048224 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 266574 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1637749 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14492701 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 245337 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51437500 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107423 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10396030 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7010506 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 766368 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62240 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3660 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16143 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 190401 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 151763 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 342164 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62995358 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26449087 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1002029 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1375117 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14032156 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 223286 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 46775692 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 94480 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9452191 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6279292 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 703336 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 50186 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4000 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 14875 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 165277 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 131199 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 296476 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 59245437 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 25661722 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 791931 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116692 # number of nop insts executed -system.cpu0.iew.exec_refs 32879818 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6078109 # Number of branches executed -system.cpu0.iew.exec_stores 6430731 # Number of stores executed -system.cpu0.iew.exec_rate 0.262055 # Inst execution rate -system.cpu0.iew.wb_sent 62497341 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 45254156 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24800882 # num instructions producing a value -system.cpu0.iew.wb_consumers 45441474 # num instructions consuming a value +system.cpu0.iew.exec_nop 106169 # number of nop insts executed +system.cpu0.iew.exec_refs 31462090 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5561458 # Number of branches executed +system.cpu0.iew.exec_stores 5800368 # Number of stores executed +system.cpu0.iew.exec_rate 0.254363 # Inst execution rate +system.cpu0.iew.wb_sent 58848296 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 41659234 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23213315 # num instructions producing a value +system.cpu0.iew.wb_consumers 42468919 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.188253 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.545776 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.178859 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.546595 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9944794 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 817061 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 299135 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77306104 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.530438 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.512152 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 8329034 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 722643 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 258629 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 71918596 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.527800 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.514238 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 62653127 81.05% 81.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7139643 9.24% 90.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2117433 2.74% 93.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1152491 1.49% 94.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1052620 1.36% 95.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 581358 0.75% 96.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 718590 0.93% 97.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 381418 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1509424 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 58433692 81.25% 81.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6549576 9.11% 90.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1938281 2.70% 93.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1064527 1.48% 94.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 992329 1.38% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 495986 0.69% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 654165 0.91% 97.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 355670 0.49% 98.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1434370 1.99% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77306104 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 32015395 # Number of instructions committed -system.cpu0.commit.committedOps 41006110 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 71918596 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29885048 # Number of instructions committed +system.cpu0.commit.committedOps 37958605 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14360902 # Number of memory references committed -system.cpu0.commit.loads 8212192 # Number of loads committed -system.cpu0.commit.membars 221881 # Number of memory barriers committed -system.cpu0.commit.branches 5266033 # Number of branches committed -system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 36294613 # Number of committed integer instructions. -system.cpu0.commit.function_calls 520344 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1509424 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13195057 # Number of memory references committed +system.cpu0.commit.loads 7640786 # Number of loads committed +system.cpu0.commit.membars 194107 # Number of memory barriers committed +system.cpu0.commit.branches 4848128 # Number of branches committed +system.cpu0.commit.fp_insts 4699 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33604858 # Number of committed integer instructions. +system.cpu0.commit.function_calls 476381 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1434370 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 125738503 # The number of ROB reads -system.cpu0.rob.rob_writes 103590706 # The number of ROB writes -system.cpu0.timesIdled 892654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161446097 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2255175331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31936467 # Number of Instructions Simulated -system.cpu0.committedOps 40927182 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31936467 # Number of Instructions Simulated -system.cpu0.cpi 7.527130 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.527130 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.132853 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.132853 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 285784738 # number of integer regfile reads -system.cpu0.int_regfile_writes 46365180 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22828 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19904 # number of floating regfile writes -system.cpu0.misc_regfile_reads 16064067 # number of misc regfile reads -system.cpu0.misc_regfile_writes 471303 # number of misc regfile writes -system.cpu0.icache.replacements 986601 # number of replacements -system.cpu0.icache.tagsinuse 511.585602 # Cycle average of tags in use -system.cpu0.icache.total_refs 10225858 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 987113 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.359359 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6782112000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 321.917069 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 189.668533 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.628744 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.370446 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999191 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5498991 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 4726867 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10225858 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5498991 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 4726867 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10225858 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5498991 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 4726867 # number of overall hits -system.cpu0.icache.overall_hits::total 10225858 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 552708 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 515964 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1068672 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 552708 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 515964 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1068672 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 552708 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 515964 # number of overall misses -system.cpu0.icache.overall_misses::total 1068672 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7467633494 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6811010992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14278644486 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7467633494 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6811010992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14278644486 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7467633494 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6811010992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14278644486 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6051699 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5242831 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11294530 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6051699 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5242831 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11294530 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6051699 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5242831 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11294530 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.091331 # 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average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13343.588366 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13370.583496 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13400.917467 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13343.588366 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13370.583496 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13400.917467 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13343.588366 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13370.583496 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5202 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 775 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 345 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 6129367496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11618272991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5488905495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 6129367496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11618272991 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6767000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6767000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6767000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 6767000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084334 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.090940 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087401 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084334 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.090940 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.087401 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084334 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.090940 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.087401 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.227779 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11647.647557 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11789.090883 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.227779 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11647.647557 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11789.090883 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.227779 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11647.647557 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.090883 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087535 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.087535 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088895 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.087535 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11789.180744 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11789.180744 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.180744 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # 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number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 181000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 69289017289 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 56485049849 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125774067138 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 69289017289 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 56485049849 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125774067138 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7697771 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6914534 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14612305 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5345284 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4906570 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10251854 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 150078 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 147094 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 297172 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144162 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 141619 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 285781 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13043055 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11821104 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24864159 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13043055 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11821104 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24864159 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048946 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.053431 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051068 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.281714 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.296298 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.288694 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.050174 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6175136983 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7422009940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13597146923 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6175136983 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7422009940 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13597146923 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91055617500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91310638500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182366256000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 10805151656 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13444453545 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 24249605201 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105497698895 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100964086593 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206461785488 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.026145 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026724 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026419 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023832 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024789 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024290 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045070 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.036868 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.041010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000049 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025197 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025921 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025541 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025197 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025921 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025541 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13595.986823 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13240.839354 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13425.992172 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36426.519209 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31170.797992 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33859.432962 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12157.894737 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11562.511525 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11892.959711 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101860769156 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104755092045 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206615861201 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027033 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026070 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026538 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023340 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025264 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042559 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052019 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047414 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025637 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025637 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13553.062303 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13309.243275 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13429.947009 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31858.540118 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35387.300124 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33792.214211 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11734.680451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11935.658010 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.831444 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923.076923 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22445.327640 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20358.017222 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21438.214759 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22445.327640 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20358.017222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21438.214759 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12846.153846 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22401.807173 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21415.629008 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22401.807173 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21415.629008 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1338,321 +1374,321 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25160982 # DTB read hits -system.cpu1.dtb.read_misses 40128 # DTB read misses -system.cpu1.dtb.write_hits 5622181 # DTB write hits -system.cpu1.dtb.write_misses 9250 # DTB write misses +system.cpu1.dtb.read_hits 25842433 # DTB read hits +system.cpu1.dtb.read_misses 46174 # DTB read misses +system.cpu1.dtb.write_hits 6180963 # DTB write hits +system.cpu1.dtb.write_misses 11315 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 702 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 7925 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1386 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 276 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 8574 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1449 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 627 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25201110 # DTB read accesses -system.cpu1.dtb.write_accesses 5631431 # DTB write accesses +system.cpu1.dtb.perms_faults 622 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25888607 # DTB read accesses +system.cpu1.dtb.write_accesses 6192278 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 30783163 # DTB hits -system.cpu1.dtb.misses 49378 # DTB misses -system.cpu1.dtb.accesses 30832541 # DTB accesses -system.cpu1.itb.inst_hits 5244962 # ITB inst hits -system.cpu1.itb.inst_misses 6670 # ITB inst misses +system.cpu1.dtb.hits 32023396 # DTB hits +system.cpu1.dtb.misses 57489 # DTB misses +system.cpu1.dtb.accesses 32080885 # DTB accesses +system.cpu1.itb.inst_hits 5862958 # ITB inst hits +system.cpu1.itb.inst_misses 7630 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 702 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2650 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2762 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1456 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1655 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5251632 # ITB inst accesses -system.cpu1.itb.hits 5244962 # DTB hits -system.cpu1.itb.misses 6670 # DTB misses -system.cpu1.itb.accesses 5251632 # DTB accesses -system.cpu1.numCycles 232013377 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5870588 # ITB inst accesses +system.cpu1.itb.hits 5862958 # DTB hits +system.cpu1.itb.misses 7630 # DTB misses +system.cpu1.itb.accesses 5870588 # DTB accesses +system.cpu1.numCycles 238328292 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 6790425 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 5410391 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 343130 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 4365867 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 3552399 # Number of BTB hits +system.cpu1.BPredUnit.lookups 7461261 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 5924878 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 387688 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 4864845 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 3916001 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 675836 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 35150 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 14219364 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 41265528 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 6790425 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4228235 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9330468 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2101425 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82678 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47674573 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1954 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 48379 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 99398 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 108 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5242833 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 267586 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2984 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 72923984 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.712246 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.058401 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 732677 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 39651 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 15658024 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45723743 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7461261 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4648678 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10301295 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2449187 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 90048 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49530341 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2013 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 58322 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 105488 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 234 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5860623 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 343915 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3550 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 77436496 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.743507 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.098927 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 63601422 87.22% 87.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 651379 0.89% 88.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 811870 1.11% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1013874 1.39% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 943793 1.29% 91.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 538574 0.74% 92.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1195574 1.64% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 358365 0.49% 94.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3809133 5.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 67142740 86.71% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 670388 0.87% 87.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 904116 1.17% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1146258 1.48% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1035072 1.34% 91.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 585216 0.76% 92.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1324002 1.71% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 382858 0.49% 94.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4245846 5.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 72923984 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029267 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.177858 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15065111 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47459427 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8508787 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 504767 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1383740 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 935366 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 84721 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 49702311 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 283407 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1383740 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 15832821 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18424865 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25966015 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8176580 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3137893 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 47902393 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7520 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 511770 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2112759 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 14566 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 49459920 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 218567938 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 218526163 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 41775 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37332689 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12127230 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 420234 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 377586 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6217035 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9300150 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6339076 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 983520 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1172387 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 44745095 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 970903 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 59171295 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 83947 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 8398889 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 19786111 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 243126 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 72923984 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811411 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.516236 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 77436496 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.031307 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.191852 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16603606 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49335429 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9407116 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 490405 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1597859 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1045633 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 93792 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54840588 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 310696 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1597859 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17482170 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19064051 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27065673 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8938575 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3286155 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 52466184 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7798 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 497565 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2245284 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 18515 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54189093 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 239808372 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 239759506 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 48866 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39935280 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14253813 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 446450 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 393915 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6702948 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10122887 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6990261 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 974914 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1217289 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48733638 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1005144 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62551860 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 96432 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9690546 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24103101 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 245099 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 77436496 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.807783 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.518787 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 51567769 70.71% 70.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6722785 9.22% 79.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3414540 4.68% 84.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2860255 3.92% 88.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6054704 8.30% 96.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1326273 1.82% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 714361 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 204058 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59239 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54919142 70.92% 70.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7063904 9.12% 80.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3691282 4.77% 84.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2953327 3.81% 88.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6235094 8.05% 96.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1492250 1.93% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 791283 1.02% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 225625 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 64589 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 72923984 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 77436496 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24658 0.56% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 2 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4170684 95.00% 95.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 195004 4.44% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27571 0.62% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4198494 94.58% 95.20% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 213042 4.80% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167246 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 27298169 46.13% 46.42% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 44245 0.07% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 839 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.49% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 25732684 43.49% 89.98% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5928100 10.02% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 169105 0.27% 0.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29343777 46.91% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 48983 0.08% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1277 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26498919 42.36% 89.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6489779 10.38% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 59171295 # Type of FU issued -system.cpu1.iq.rate 0.255034 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4390348 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.074197 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 195779484 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 54123667 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 40860194 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10578 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5727 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4726 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 63388772 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5625 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 295886 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62551860 # Type of FU issued +system.cpu1.iq.rate 0.262461 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4439108 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070967 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 207120715 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59438377 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43832825 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12343 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6735 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5565 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66815352 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6511 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 325479 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1794199 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2827 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15001 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 687985 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2107508 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3797 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 16351 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 811464 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17035415 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 238532 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17060218 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 341441 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1383740 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13800740 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 226965 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 45822265 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96960 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9300150 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6339076 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 695770 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 48787 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3997 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15001 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167673 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132287 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 299960 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 58435443 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25502557 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 735852 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1597859 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14264833 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 247482 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49856426 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 107204 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 10122887 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6990261 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 704284 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 59901 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3604 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 16351 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 190247 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 149600 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 339847 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 61552998 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 26188496 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 998862 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106267 # number of nop insts executed -system.cpu1.iew.exec_refs 31379358 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5453104 # Number of branches executed -system.cpu1.iew.exec_stores 5876801 # Number of stores executed -system.cpu1.iew.exec_rate 0.251862 # Inst execution rate -system.cpu1.iew.wb_sent 58051293 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 40864920 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22407090 # num instructions producing a value -system.cpu1.iew.wb_consumers 41228321 # num instructions consuming a value +system.cpu1.iew.exec_nop 117644 # number of nop insts executed +system.cpu1.iew.exec_refs 32619530 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5900270 # Number of branches executed +system.cpu1.iew.exec_stores 6431034 # Number of stores executed +system.cpu1.iew.exec_rate 0.258270 # Inst execution rate +system.cpu1.iew.wb_sent 61059596 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43838390 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23681235 # num instructions producing a value +system.cpu1.iew.wb_consumers 43694541 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.176132 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543488 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.183941 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.541972 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 8312194 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 727777 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259619 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 71540244 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.518566 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.491714 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9661212 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 760045 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 295282 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75838637 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.524766 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.504226 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 58151016 81.28% 81.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6627858 9.26% 90.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1880092 2.63% 93.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1040741 1.45% 94.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 983750 1.38% 96.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 494100 0.69% 96.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 697389 0.97% 97.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 324169 0.45% 98.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1341129 1.87% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61579117 81.20% 81.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7021291 9.26% 90.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2015124 2.66% 93.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1085811 1.43% 94.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1003078 1.32% 95.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 577963 0.76% 96.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 742657 0.98% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378274 0.50% 98.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1435322 1.89% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 71540244 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 28738593 # Number of instructions committed -system.cpu1.commit.committedOps 37098314 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75838637 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30577831 # Number of instructions committed +system.cpu1.commit.committedOps 39797535 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13157042 # Number of memory references committed -system.cpu1.commit.loads 7505951 # Number of loads committed -system.cpu1.commit.membars 191336 # Number of memory barriers committed -system.cpu1.commit.branches 4758017 # Number of branches committed -system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 32847444 # Number of committed integer instructions. -system.cpu1.commit.function_calls 475803 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1341129 # number cycles where commit BW limit reached +system.cpu1.commit.refs 14194176 # Number of memory references committed +system.cpu1.commit.loads 8015379 # Number of loads committed +system.cpu1.commit.membars 209589 # Number of memory barriers committed +system.cpu1.commit.branches 5113967 # Number of branches committed +system.cpu1.commit.fp_insts 5513 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 35255841 # Number of committed integer instructions. +system.cpu1.commit.function_calls 515004 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1435322 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 114702650 # The number of ROB reads -system.cpu1.rob.rob_writes 92242025 # The number of ROB writes -system.cpu1.timesIdled 868716 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159089393 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2323530978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 28667140 # Number of Instructions Simulated -system.cpu1.committedOps 37026861 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 28667140 # Number of Instructions Simulated -system.cpu1.cpi 8.093356 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.093356 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.123558 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.123558 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 264545362 # number of integer regfile reads -system.cpu1.int_regfile_writes 41743183 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22037 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19620 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14602821 # number of misc regfile reads -system.cpu1.misc_regfile_writes 442325 # number of misc regfile writes +system.cpu1.rob.rob_reads 122900984 # The number of ROB reads +system.cpu1.rob.rob_writes 100566633 # The number of ROB writes +system.cpu1.timesIdled 901138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160891796 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2255172449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30498934 # Number of Instructions Simulated +system.cpu1.committedOps 39718638 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30498934 # Number of Instructions Simulated +system.cpu1.cpi 7.814315 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.814315 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127970 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127970 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 279110946 # number of integer regfile reads +system.cpu1.int_regfile_writes 44685160 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22658 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19886 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15820673 # number of misc regfile reads +system.cpu1.misc_regfile_writes 438571 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1667,17 +1703,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125347676632 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1125347676632 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125347676632 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1125347676632 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1125362728944 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1125362728944 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 88038 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83058 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |